JPH0983874A - Image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid useless signal processing in the case of picking up a dynamic through the use of a full picture element read type CCD. SOLUTION: When a mode selector switch 11 commands a dynamic image mode, a video signal from a CCD 2 picking up 1-frame image for 1-field period is processed by a camera signal processing circuit 4 and then processed by a video signal processing circuit 5. In this case, an image memory 8, a memory address control circuit 9 and a memory input buffer control circuit 10 are used to generate a dynamic image by using each line sequentially from consecutive different frame images. In a still image mode, the signal processing to obtain high image quality still image by using a same frame image is conducted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image pickup apparatus such as a video camera for recording a video signal picked up by an image pickup device.

[0002]

2. Description of the Related Art In a conventional image pickup apparatus, video data output from a camera signal processing circuit is interlaced field unit data. FIG. 6 shows a block diagram of a conventional image pickup apparatus. In FIG. 6, 1 is a lens, 2 is a CCD as an image sensor for photoelectrically converting a subject image, 3 is an A / D converter for converting an analog signal into a digital signal, and 4 is a digitized output of the CCD 2 in field units. Camera signal processing circuit that converts to video signal,
Reference numeral 5 is a video signal processing circuit for compressing a video signal and converting it into recording data suitable for magnetic recording, 6 is a recording device for magnetically recording the recording data on a magnetic tape or the like, and 7 is C
A CCD drive driver that controls the image pickup timing of the CD 2, 8 is an image memory that stores image data, and 9 is a memory address control circuit that controls the write address / read address of the image memory 8.

Next, the operation will be described. The subject image that has passed through the lens 1 is photoelectrically converted by the CCD 2 which is an image pickup device, and becomes an electric signal in field units which is even line or odd line information. The output of CCD2 is A
It is converted into a digital signal by the / D converter 3 and input to the camera signal processing circuit 4. The camera signal processing circuit 4 performs processing such as aperture processing, high brightness color suppression processing, white balance processing, gamma processing, matrix calculation processing, synchronization signal addition processing, AF detection, AE detection, etc.
An interlaced field-based luminance signal and a color-difference time-division multiplexed signal obtained by time-division-multiplexing two types of color-difference signals are output. These luminance signal and color difference time division multiplex signal are input to the video signal processing circuit 5.

In the video signal processing circuit 5, the image memory 8 controlled by the memory address control circuit 9 is used to create image data in frame units from two consecutive image data in field units and block this. Turn into. Then, a shuffling process that makes the reading order of the image data in block units equal to the order of reading from one frame area, an orthogonal transform process that transforms the image data in block units into orthogonal transform coefficients by orthogonal transform such as DCT transform, Quantization of orthogonal transform coefficients in block units according to the degree of deviation of orthogonal transform coefficients such as DCT coefficients to the low band or high band, and quantization processing to reduce the amount of data, coding for reducing the amount of data by Huffman coding, etc. Processing is performed.

Further, the image memory 8 controlled by the memory address control circuit 9 is used to perform a deshuffling process for deshuffling the shuffled block unit quantized data. In this way, the luminance signal and the color difference signal are converted into encoded data whose data amount is compressed.

Further, the video signal processing circuit 5 modulates the created encoded data into recording data suitable for magnetic recording, and this recording data is input to the recording circuit 6 and recorded on the magnetic medium.

[0007]

As a method of recording a still image using the above-mentioned conventional image pickup apparatus, a method of creating frame data using two field data picked up at different timings, Although there is a method of creating both field data from one field data and using them as frame data, there is a problem that the disturbance of edges and the vertical resolution decrease due to the time difference of the data. In order to solve this problem, if an image pickup element (all pixel readout type image pickup element) capable of picking up a frame image in a field unit period is used, the camera signal processing circuit 4 can output field data of two systems. Become. That is, in a certain field unit period, ODD field data that is odd line information is output, and in the next field unit time, EVEN field data that is even line information is output. It is possible to have a system for outputting the EVEN field data during the period during which is output, and the ODD field data during the period during which the EVEN field data is output).

As described above, when the all-pixel reading type image pickup device is used, it is possible to output two field data having the same image pickup timing from the camera signal processing circuit 4, and can be used for still image recording. However, at the time of recording a moving image, in order to display or record a smooth moving image, it is necessary to output a signal for creating one frame data from two field data having different image pickup timings, and therefore only one system of field data is sufficient. Therefore, when video processing is performed using one of the two video signal systems output from the camera signal processing circuit 4, the other one system video signal is discarded.
Therefore, it is not necessary to perform signal processing in the video signal processing circuit 5, and performing signal processing on a discarded signal increases power consumption, and in a device using a battery drive system, driving time is reduced. Cause reduction.

It is an object of the present invention to provide an image pickup device which prevents unnecessary signal processing when a moving image is obtained using an image pickup device of the all-pixel readout system.

[0010]

According to the present invention, there is provided the following:
Image signal of the all-pixel readout method, which is configured to alternately output the video signal of the line and the video signal of the second line, and to capture one frame image in one field period; The video processing means for processing the video signal output from the element, and the video processing means in the moving image mode alternates the video signal of the first line and the video signal of the second line from different continuous frame images. There is provided control means for controlling the video processing means so as to select and generate a moving image.

[0011]

According to the present invention, the video processing means is controlled by the control means in the moving image mode to alternately select the video signals of the odd lines and the video signals of the even lines from consecutive different frame images. Since the process of generating the moving image is performed, the one-system video signal output from the image sensor is not wastefully processed, and power consumption can be suppressed.

[0012]

FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, 1 to 9 substantially correspond to the same reference numerals in FIG.

In FIG. 1, 10 is a memory input buffer control circuit for controlling the video signal processing circuit 4 according to the mode instructed by the mode selection switch 11, and 11 is a mode selection switch for selecting a moving image recording mode or a still image recording mode. Is.

Further, as the CCD 2, an image pickup element of a system called progressive scan or all-pixel read-out capable of picking up one frame image in one field period driven by the CCD drive driver 7 is used.

Next, the operation will be described. The subject image that has passed through the lens 1 is photoelectrically converted by the CCD 2 to become an electric signal having image information for each frame.

The all-pixel readout type CCD 2 has two systems of outputs, an even line output and an odd line output. CC
The output of D2 is converted into a digital signal by the A / D converter 3 and then input to the camera signal processing circuit 4.
The camera signal processing circuit 4 performs the above-described various processes, and further separates the image signal of one frame unit into the video signals of two types of field units,
Two systems of interlaced field-based luminance signals and chrominance time-division multiplexed signals are output. The video signals of these two systems are input to the video signal processing circuit 4. The video signal processing circuit 4 is controlled by a memory input buffer control circuit 10 that controls data to be written in a buffer memory, which will be described later, according to the recording mode instructed by the mode selection switch 11.

In the video signal processing circuit 5, a shuffling process, an orthogonal transform process, a quantization process, an encoding process, a modulation process and the like are performed according to the recording mode designated by the mode selection switch 11. The modulated recording data is
It is input to the recording circuit 6 and recorded on the magnetic medium.

FIG. 2 is a block diagram showing a configuration example of the camera signal processing circuit 4. In FIG. 2, 401 and 402 are 1H delay lines, 403 is a color separation / time-division multiplexing circuit that separates the CCD output into a luminance signal and an RGB signal, and time-division-multiplexes two systems of data, and 404 is an aperture correction circuit. , 405 is a gamma correction circuit, 406 is a synchronization addition circuit, 407 is a white balance circuit, 408 is a gamma correction circuit, 409 is a matrix circuit, 410 is a high luminance color suppression circuit, 411 is a time division multiplexing circuit, 412 and 413 are selectors. Is.

Next, the operation will be described. The output of the A / D converter 3 has two series of output terminals that simultaneously output two line data. 1H delay line 401, 40
2. The color separation / time division multiplexing circuit 403 separates the luminance signal Y and the RGB signal, and the two series of data (two line data) is time division multiplexed. The brightness signal Y is corrected in the high frequency range by the aperture correction circuit 404, is gamma-corrected by the gamma correction circuit 408, and is added to the synchronization addition circuit 40.
A synchronization signal is added by 6 and input to the selector 412.

On the other hand, the RGB signals are subjected to white balance adjustment by the white balance circuit 407, gamma corrected by the gamma correction circuit 408, and then converted into color difference signals (RY, BY) by the matrix circuit 409. This color difference signal is input to the white balance circuit 407 and used for white balance adjustment. Further, the color difference signal is subjected to color signal suppression at high brightness by the high brightness color suppression circuit 410 according to the brightness signal Y, and then time-division multiplexed by the color difference signal time division multiplexing circuit 411 to be subjected to the selector 4 operation.
13 is input.

The luminance signal Y and the color difference time division multiplexed signal are time-divided by the selectors 412 and 413, and each output is selected such that even / odd lines are alternated in field data output units. Therefore, two outputs (Y
1, C1) and (Y2, C2), field data with different imaging timings are continuously output.

FIG. 3 is a diagram showing the timing of the output signal of the camera signal processing circuit 4. In FIG. 3, frame images F1, F2, and F captured at consecutive image capturing timings.
3 is shown. The frame image capturing timing is the conventional field image capturing timing (NTSC: about 60).
Hz). At this time, the output (Y1, C1) of the camera signal processing circuit 4 has odd line data o1 (luminance signal Y, color difference time division multiplexed signal) of the frame image F1, and even line data e2 (luminance signal Y of the frame image F2). , Color difference time division multiplex signal) and odd line data o3 (luminance signal Y, color difference time division multiplex signal) of the frame image F3 are output. Further, the frame image F is output (Y2, C2).
Even line data e1 of 1 (luminance signal Y, color difference time division multiplexed signal), odd line data o2 of frame image F2
(Luminance signal Y, color difference time division multiplexed signal), frame image F
3 even-numbered line data e3 (luminance signal Y, color difference time division multiplexed signal) is output.

FIG. 5 is a block diagram showing a configuration example of the video signal processing circuit. In FIG. 5, 5, 8, 9, 10, 1
1 is the same block as in FIG. 501, 502, 50
3, 504 and 509 are input buffers for writing data in the image memory 8, 505 and 510 are output buffers for reading data from the image memory 8, and 506 is DC.
Orthogonal transformation circuit for performing T transformation, 507 is a quantization circuit, 5
Reference numeral 08 is an encoding circuit and 511 is a modulation circuit.

Next, the operation will be described. When the still image recording mode is selected by the mode selection switch 11, the video signal (luminance signal Y, color difference time division multiplex signal) of two fields output from the camera signal processing circuit 4 is sent to the video signal processing circuit 5. Is entered. The still image recording mode signal output from the mode selection switch 11 is input to the memory input buffer control circuit 10. The memory input buffer control circuit 10 controls the input buffers 501 to 504 so that the same image pickup timing data, that is, the two-field data input as Y1, C1, Y2, and C2 at the same timing is written in the image memory 8.

The still image recording mode signal is also input to the memory address control circuit 9 and Y at the same timing.
The write address is controlled so that one frame data is combined from the two field data input as 1, C1, Y2, and C2. The read address is formed by blocking the signal Y and the color difference signal in the frame data, and
Block data is given (shuffled) in an order determined so as to be evenly read from within a frame.

The block data read from the image memory 8 is D-block by block in the orthogonal transformation circuit 506.
Orthogonal transformation such as CT transformation is performed, and orthogonal transformation coefficient data is output. This orthogonal transform coefficient data is used by the quantization circuit 5
In 07, depending on the bias of the orthogonal transform coefficient data, the decoded data is quantized by the quantized coefficient determined so that the decoded data does not change significantly during the inverse transform. This quantized data is input to the encoding circuit 508 and is encoded within the block to reduce the data amount of zigzag scanning and Huffman encoding.

The coded data is again stored in the image memory 8
Is written into the image memory 8 and is shuffled so that the shuffled data is returned to the conventional frame data arrangement. The deshuffled encoded data is modulated so that the recording characteristic of the recording circuit 6 is enhanced and highly accurate recording / reproduction equalization can be performed.

Next, even when the moving image recording mode is selected by the mode selection switch 11, two systems of video signals in the field unit output from the camera signal processing circuit 4 (the above signal Y, color difference time division multiplexed signal). Is input to the video signal processing circuit 5. The moving image recording mode signal output from the mode selection switch 11 is input to the memory input buffer control circuit 10. Memory input buffer control circuit 10
Is field data of two sheets with different imaging timings,
That is, the input buffers 501 to 504 are controlled so that continuous two-field data of either (Y1, C1) or (Y2, C2) is written in the image memory 8.

When the (Y1, C1) side field data is used, the input buffers 503 and 504 receive from the memory input buffer control circuit 10 a signal for turning off the power of the input buffer. The clock signal input to the input buffer serves as a gate output with the output signal of the memory input buffer control circuit 10, and the clock input to the input buffer by the memory input buffer control circuit 10 is turned off. By using at least one of the above methods, the input buffers 501 to 50
The driving of No. 4 is controlled by the memory input buffer control circuit 10.

Further, the moving picture recording mode signal is inputted to the memory address control circuit 9 and one frame data is obtained from continuous two field data inputted from one system of video signals (Y1, C1 in the above example). Control the write address so that The read address is given so that the signal Y in the frame data and the color difference signal are divided into blocks, and the block data is read out in an order (shuffling) determined so as to be read out uniformly from one frame. The orthogonal transformation process, the quantization process, the encoding process, and the modulation process after the shuffling process are the same in the moving image recording mode as in the still image recording mode.

FIG. 5 shows a block diagram of a control circuit for controlling the input buffers 501 to 504. FIG. 5 (A) is a block diagram for performing the above method, and FIG.
FIG. 4 is a block diagram for performing the above method. Reference numerals 512 and 513 in FIG. 5A denote a power supply control circuit, and FIG.
514 and 515 are clock gates. As described above, when the field data on the (Y1, C1) side is used, the input buffers 501 and 502 are supplied with the power supply or the gate passage clock. At this time, the input buffer 5
The power supply circuits 601 and 602 or the clock gates 603 and 604 operate so that the power supply circuits or gate passing clocks are not supplied to the circuits 03 and 504.

[0032]

As described above, according to the present invention, when a moving image is picked up and recorded by using an image pickup device of an all-pixel reading method capable of eliminating the disturbance of edges and the deterioration of vertical resolution when picking up a still image. In addition, it is possible to eliminate wasteful processing of the video signal, which can reduce the power consumption and thus extend the drive time in the device using the battery drive system.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a camera signal processing circuit.

FIG. 3 is a timing chart showing the output of the camera signal processing circuit.

FIG. 4 is a block diagram showing a configuration example of a video signal processing circuit.

FIG. 5 is a block diagram showing a configuration example of a control circuit that controls an input buffer.

FIG. 6 is a block diagram showing a conventional imaging device.

[Explanation of symbols]

 2 CCD 4 camera signal processing circuit 5 video signal processing circuit 7 memory address control circuit 8 image memory 9 memory address control circuit 10 memory input buffer control circuit 11 mode selection switch

Claims (2)

[Claims] 1. An all-pixel reading method configured to alternately output a video signal of a first line and a video signal of a second line, and to capture one frame image in one field period. Image pickup device, a video processing unit for processing a video signal output from the image pickup device, and the video processing unit in the moving image mode, the video signal of the first line and the second line of consecutive different frame images. An image pickup apparatus comprising: a control unit that controls the video processing unit so as to perform processing for alternately selecting the video signal and the video signal. 2. The control means performs a process in which, in the still image mode, the video processing means generates a still image using the video signal of the first line and the video signal of the second line in the same frame image. The image pickup apparatus according to claim 1, wherein the image processing means is controlled to perform the operation.