JPH0983474A - Signal transmission processing unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the loss of s-bit in the process of multiplexing and signal separation by copying the s-bit in a specific frame of each Y interface to a position corresponding to that in all other frames. SOLUTION: Each Y interface input signal is decoded for multiplexing in CMI DECODE 101-10n and synchronized by succeeding synchronization circuits 111-11n. Then s-bit copy sections 121-12n copy an s-bit in a specific frame of each Y interface signal to a bit position in all other frames corresponding to the s-bit position. The output signal is given to a multiplexer circuit 130, in which the signal is multiplexed and the result is given to a demultiplexer circuit 201 of a receiver side through a high speed communication transmission line 30. The signal is demultiplexed to respective interface signals and a synchronizing signal is provided by synchronizing signal provision sections 211-21n, the CMI DECODE 101-10n conduct conversion processing to provide an output of a Y interface signal. Thus, the loss of the s-bit in the process of multiplexing and signal demultiplexing is avoided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal transmission device, and more particularly to a user network interface of 6.3 MbpsY.
The present invention relates to a signal transmission processing device for multiplexing and transmitting interface signals and then separating them.

[0002]

2. Description of the Related Art ISDN (Integrated Services Digital Network)
As a dedicated line for data transmission provided by
The MdpsY interface is known. The Y interface signal has a 4-multiframe structure. That is, it has a periodic structure in which four frames are connected. Then, in the third frame of the four multi-frames, there are S bits indicating the usage status of the line. This S bit is given to a specific bit of the third frame,
For example, the data is “1”.

[0003]

On the other hand, the ISDN high-speed data transmission service makes it possible to multiplex and transmit such Y interface signals. However, when the Y interface signal is multiplexed, the Y interface signal is converted into the CMI structure TTL code forming the Y interface. Then, in the process of multiplexing and the subsequent signal separation, the sync signal is also coded and converted, and the sync signal is newly added on the receiving side. Y output at the receiving side in this process
The interface signal may be processed with the arbitrary frame as the first frame regardless of the order of the transmitting side. Therefore, even if the S bit of the third frame is to be detected, the third frame may be the first frame, and the reception side cannot detect normal reception.

[0004]

The present invention adopts the following constitution in order to solve the above points. <Structure> The signal transmission processing device of the present invention is configured as a multi-frame by receiving a decoding unit that receives a plurality of Y interface signals and performs signal conversion respectively, and an output signal of each decoding unit that is controlled in synchronization with each other. S-bit copy section for copying the S bit contained in a specific frame of the Y interface signal to corresponding positions in all other frames, and the output signal of the S-bit copy section is received and multiplexed for high-speed signal transmission. Circuit for transmitting to the path, a separation circuit for separating the signal received from this high-speed signal transmission path into a signal corresponding to the Y interface signal, and the output of this separation circuit is signal-converted to restore the original Y interface signal. And a coding unit.

<Description> For example, a 6.3 Mbps Y interface signal has a structure in which four multiframes are formed, and S bits are included in the third frame. When transmitting / receiving the Y interface signal, the receiving side detects that the signal is normally received by detecting the S bit in the third frame. However, if the signal is converted by multiplexing or the like, the receiving side processes an arbitrary frame as the first frame, and thus S bit detection from the third frame may not be possible. Therefore, on the transmitting side, a plurality of Y interface signals are multiplexed to obtain 150 Mbp.
When S bits are included in the corresponding positions of all the frames of each Y interface signal in advance when multiplexed to the high-speed signal of s, no matter which frame is selected by the receiving side as the first frame, S bits can be detected in 3 frames.

[0006]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to specific examples. <Specific Example> FIG. 1 is a block diagram showing a specific example of the signal transmission processing device of the present invention. This device multiplexes a plurality of Y interface signals in a multiplexing unit 10 on the transmitting side and transmits the multiplexed signals to a separating unit 20 on the receiving side via a high-speed signal transmission line 30. Then, the Y interface signal is separated and output again here. Each multiplexing unit 10 has a Y
.. 10n as many as the number of input signals are provided to process the interface signals. Further, synchronization circuits 111, 112, ... 11n are provided to establish synchronization of outputs of these decoding units. Further, in the present invention, S bit copy units 121, 122, ... Having an S bit processing function as described later are provided.
12n are provided. These outputs are multiplexed circuit 13
It is configured so that signals are input to 0 and signals are multiplexed. The Y interface signal is a 6.312 Mbps signal, and the multiplexed signal is, for example, 150 Mbps.

A separating circuit 201 is provided in the separating unit 20 on the receiving side, where each signal is separated into respective Y interface signals. Then, in order to add a synchronization signal to these signals, synchronization providing units 211 to 21n are provided. Further, the outputs of the synchronization imparting units 211 to 21n are configured to be converted and output by the encoding units 221 to 22n. The decoding units 101 to 10n of the multiplexing unit 10 are circuits that convert the Y interface signal configured by the CMI code into a TTL signal for multiplexing. The coding units 221 to 22n are circuits that convert the TTL signal output from the separation circuit 201 into a CMI code and output a Y interface signal.

FIG. 2 illustrates the frame structure of the Y interface signal. As shown in the figure, the Y interface signal has a structure in which one frame is composed of 789 bits and four frames are connected. Although one frame is composed of 789 bits as described above, data is stored in the first 784 bits and control data is stored in the remaining 5 bits. The first 784 bits are composed of 98 time slots. This one time slot is composed of 8-bit data. In the present invention, the problem is the 5-bit data provided in the latter half of each frame. Therefore, only the 5-bit data of each frame is enlarged and shown on the bottom side of the figure. Here, in the general Y interface signal, S bits are stored in the third bit of the 5 bits for controlling the third frame. However, even if the transmitting side transmits with such an array, it is unknown on the receiving side which frame is set as the first frame. Therefore, the third frame shown in this figure is set as the first frame, the fourth frame is the second frame, the first frame is the third frame, and the second frame is four. It may be set in the second frame. When this happens, the third
Looking for the S bit in the second frame will not detect this. Therefore, in the present invention, S bits are copied to corresponding locations of all frames of the Y interface signal by the S bit copy units 121 to 12n.

FIG. 3 shows an operation explanatory diagram of the S-bit copy section. As shown in this figure, the S bit copy unit is
When a multi-frame is input, the S bit of the 3rd frame is taken out and the 4th frame and the next 4th frame are extracted.
Copy to the first and second frames in the multi-frame. Also, the S bits in the third frame of the next 4 multiframes are copied to the corresponding bits of each subsequent similar frame. In this way, the multiplexing section shown in FIG. 1 copies S bits to all frames of the Y interface signal. In this way, the receiving-side separation unit 20 separates the Y interface signals from each other, and no matter which frame is used as the reference for the synchronization signal, S is always the third frame.
The bit is stored and can be detected.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a signal transmission processing device of the present invention.

FIG. 2 is an explanatory diagram of a frame configuration of a 6.3 Mbps Y interface signal.

FIG. 3 is an operation explanatory diagram of an S-bit copy unit.

[Explanation of symbols]

 10 Multiplexing unit 20 Separation unit 30 High-speed signal transmission path 101 to 10n Decoding unit 121 to 12n S bit copy unit 130 Multiplexing circuit 201 Separation circuit 221 to 22n Encoding unit

Claims (1)

[Claims] 1. A decoding unit which receives a plurality of Y interface signals and respectively performs signal conversion, and an output signal of each decoding unit which is controlled in synchronization with each other, and receives a specific frame of a multi-framed Y interface signal. An S-bit copy section for copying the S-bits contained therein to corresponding positions in all other frames; and a multiplexing circuit for receiving and multiplexing the output signal of the S-bit copy section and transmitting it to the high-speed signal transmission line. A separation circuit for separating the signal received from the high-speed signal transmission line into a signal corresponding to the Y interface signal, and a coding unit for converting the output of the separation circuit to restore the original Y interface signal. A signal transmission processing device characterized by the above.