JPH098310A - Fabrication of semiconductor device - Google Patents

Abstract

PURPOSE: To prevent punch through without increasing the threshold voltage and to prevent fluctuation of the threshold voltage due to a thermal process by heat treating after doping first impurities in order to make uniform the impurity concentration and then doping second impurities. CONSTITUTION: A buried oxide layer 12 and an SOI layer 14 are formed on an SOI substrate 10 before depositing an isolation film 26. Boron ions are then implanted into a region for forming an N type MOS transistor. Subsequently, the implanted boron ions are diffused by heat treatment and the concentration of boron is made uniform in the SOI Layer 14. Assuming the diffusion coefficient of baron is D, conditions of heat treatment are set such that 2×(Dt)</2> has a value larger than the thickness of SOI layer 14 upon elapse of a long time. Finally, antimony ions are implanted and a gate electrode 22, a source diffusion layer 16, a drain diffusion layer 18, etc., are formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a MIS transistor, and more particularly to a method for manufacturing a semiconductor device capable of suppressing the short channel effect and reducing the fluctuation of the threshold voltage due to a thermal process.

[0002]

2. Description of the Related Art With high integration of LSIs, a short channel effect due to miniaturization of elements has become a problem. In order to suppress the short channel effect, it is desirable to increase the impurity concentration in the channel region to prevent punch through between the source and drain diffusion layers. However, even if the impurity concentration of the channel region is simply increased, the threshold voltage is also increased, so that a high current driving capability cannot be obtained.

Therefore, the impurity concentration is increased inside the substrate in the channel region in order to prevent punch-through, while
In order to suppress an increase in threshold voltage on the surface of the substrate, it is common practice to lower the impurity concentration. For example, such an impurity profile is formed by a so-called counter doping method in which a dopant having a conductivity type opposite to that of the semiconductor substrate is introduced into the substrate surface side. In the counter-doping method, when the impurity concentration of the substrate is increased to prevent punch-through, a dopant of a conductivity type opposite to that of the semiconductor substrate is introduced to the substrate surface side to compensate the carrier, This is a method of reducing the carrier concentration on the side and suppressing an increase in the threshold voltage.

Thus, a semiconductor device having a desired threshold voltage while suppressing the short channel effect has been constructed.

[0005]

However, in the conventional general semiconductor device, the impurities introduced to prevent punch-through are unevenly distributed with peaks inside the substrate. It changes greatly by the heat treatment of the subsequent process. As a result, there is a problem that the thermal diffusion of impurities affects the impurity concentration near the surface and the threshold voltage fluctuates.

Further, if the thermal process in the subsequent step changes, the threshold voltage changes, so that there is a problem that a desired threshold voltage cannot be obtained due to variations in heat treatment conditions. In addition, there is a problem that it is necessary to optimize the impurity introduction amount and the like for each different thermal process. An object of the present invention is to provide a method of manufacturing a semiconductor device which can prevent punch-through without increasing the threshold voltage and has a small variation in the threshold voltage due to a thermal process.

[0007]

A first impurity doping step of doping a semiconductor layer with a first impurity having a first conductivity type, and the semiconductor doped with the first impurity. Heat treating the layer to make the concentration of the first impurity in the semiconductor layer substantially uniform;
A second conductive type second layer on the heat-treated semiconductor layer;
A second impurity doping step of doping the impurities of
And a transistor formation step of forming a MIS transistor using the semiconductor layer doped with the first impurity and the second impurity as a channel region.

In the method of manufacturing a semiconductor device described above, in the first impurity doping step, the short channel effect of the MIS transistor is reduced by increasing the doping amount of the first impurity, and the second impurity doping step is performed. In the impurity doping step, it is desirable to decrease the threshold voltage of the MIS transistor to a desired value by increasing the doping amount of the second impurity.

In the method of manufacturing a semiconductor device described above, it is preferable that the semiconductor layer is an SOI layer in an SOI substrate. In the method for manufacturing a semiconductor device described above, in the heat treatment step, when the diffusion constant of the first impurity is D, the heat treatment time is t, and the film thickness of the SOI layer is t _Si , 2√ (Dt) It is desirable to perform the heat treatment at a temperature and for a time period at which is larger than t _Si .

[0010]

According to the present invention, a semiconductor layer is doped with a first impurity having a first conductivity type, a first impurity doping step, and the semiconductor layer doped with the first impurity is heat-treated to form a semiconductor. A heat treatment step of making the concentration of the first impurity in the layer substantially uniform, a second impurity doping step of doping the heat-treated semiconductor layer with a second impurity having a second conductivity type, and a first impurity If the semiconductor device is manufactured by the transistor forming step of forming the MIS transistor in the semiconductor layer doped with the second impurity, the fluctuation of the threshold voltage due to the heat treatment in the subsequent step can be reduced.

Further, in the first impurity doping step, MI is increased by increasing the doping amount of the first impurity.
If the threshold voltage of the MIS transistor is reduced to a desired value by reducing the short channel effect of the S transistor and increasing the doping amount of the second impurity in the second impurity doping step, increase the threshold voltage. Without short channel effect can be prevented.

In the method of manufacturing a semiconductor device described above, if the SOI layer of the SOI substrate is doped with the first impurity, the first impurity can be easily made uniform in the heat treatment step. Further, in the heat treatment step, the diffusion constant of the first impurity D, and the heat treatment time t, the thickness of the SOI layer is taken as t _Si, 2√ (Dt) is the temperature and time that is larger than t _Si If heat-treated, the first in the SOI layer
The distribution of the impurities can be made substantially uniform.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the principle of the method of manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. FIG. 1 is a diagram showing a structure of a semiconductor device used for numerical analysis, FIG. 2 is a graph showing results obtained by numerical analysis of gate length dependence of threshold voltage in a conventional semiconductor device, and FIG. 3 is an impurity distribution in a channel region. 4 is a graph showing the relationship between the threshold voltage and the depth of the counter-doped layer, FIG. 5 is a graph showing the relationship between the threshold voltage and the distance to the center of the counter-doped layer, and FIG. It is a graph which shows the relationship with the width of a counter dope layer.

The semiconductor device shown in FIG. 1 is an N-type MOSFET formed on an SOI substrate. Silicon substrate 10
A buried oxide film 12 having a thickness of 400 nm is formed on the top. A film thickness of 100 is formed on the buried oxide film 12.
An SOI layer 14 having a thickness of nm is formed. A source diffusion layer 16 and a drain diffusion layer 18 are independently formed in the SOI layer 14. The film thickness is 4 nm on the SOI layer 14.
Gate insulating film 20 is formed. Gate insulating film 2
A gate electrode 22 made of polycrystalline silicon is formed on 0. The donor concentration N _D of the source diffusion layer 16, the drain diffusion layer 18, and the gate electrode 22 is 10 ²⁰ c.
m ^-3 .

In the semiconductor device of FIG. 1, the threshold voltage V when the acceptor concentration N _A of the channel region 24 is changed
FIG. 2 shows the dependence of _{th on} the gate length L _g . In the figure, the solid line shows the dependency when the drain voltage is 0.05 V, and the dotted line shows the dependency when the drain voltage is 1 V. In this embodiment, the threshold voltage V _th is the drain current I _D and the gate width W _g.
It is defined as the gate voltage V _g when the product of and becomes 1 μA · μm.

As shown in the figure, when the acceptor concentration N _A of the channel region 24 is 1 × 10 ¹⁷ cm ^-3 , the threshold voltage V _th is remarkably reduced as the channel length L _g is shortened. , The acceptor concentration N _A is increased and the decrease in the threshold voltage V _th is suppressed. When the acceptor concentration N _A is 2 × 10 ¹⁸ cm ⁻³ , the gate length L _g is 0.07.
Even if it is shortened to 5 μm, the decrease in the threshold voltage V _th when the drain voltage V _d is 1 V can be suppressed to 0.3 V or less. When the gate length L _g is 0.1 μm, the decrease in threshold voltage can be suppressed to 0.1 V or less.

If the acceptor concentration N _A is further increased, the decrease in threshold voltage V _th can be further suppressed.
However, when the concentration of the channel region 24 is too high, the p formed by the drain diffusion layer 18 and the channel region 24 is formed.
Since problems such as a tunnel current flowing in the n-junction and a decrease in reverse breakdown voltage occur, it is necessary to consider this point in device design.

On the other hand, the threshold voltage V _th increases as the acceptor concentration N _A of the channel region 24 increases. When the acceptor concentration N _A of the channel region 24 is 2 × 10 ¹⁸ cm ⁻³ , the threshold voltage V _th is about 0.9 V, and it is preferable that the threshold voltage in the deep submicron device be lower. Therefore, the channel region 24 is counter-doped to adjust the threshold voltage V _th .

As shown in FIG. 3A, the channel region 2
4 of the acceptor concentration N _A as 2 × 10 ^{1 8} cm ^-3 constant, the counter-doped layer having a uniform concentration to a depth d _c from the surface, 7.5 × donor amount [Phi _D per unit area
FIG. 4 shows the relationship between the threshold voltage V _th and the depth d _c when formed as 10 ¹² cm ⁻² . As shown, depth d _c
The shallower is the threshold voltage V _th, the lower.

As shown in FIG. 3B, when the distance R _p from the substrate surface to the center of the counter-doped layer is changed while keeping the width d _w of the counter-doped layer constant, as shown in FIG. As the distance R _p increases, the threshold voltage V _th
Also increases. However, when the width d _w of the counter-doped layer is changed while keeping the distance R _p constant, the threshold voltage V _th hardly depends on the width d _w of the counter-doped layer as shown in FIG. Total layer donor Φ
Depends only on _D.

The concentration distribution of the counter dope layer is shown in FIG.
Even when the approximation is performed by a Gaussian distribution as shown in FIG. 3C instead of the rectangular approximation as shown in FIG. 3B, the width of the counter-doped layer is 2ΔR _p (ΔR _p is Gaussian) as shown by ◯ in the figure. Distribution standard deviation). As described above, when the channel region 24 is counter-doped when the acceptor concentration N _A of the channel region 24 is constant, the absolute value of the threshold voltage V _th is determined only by the distance R _p and the total donor amount Φ _D. It can be seen that the threshold voltage V _th does not change even if the spread of the distribution (the width d _w of the counter-doped layer or the standard deviation ΔR _{p of the} Gaussian distribution) changes.

Next, the above phenomenon will be verified using an analytical model. FIG. 7 is a diagram showing the outline of the analytical model used in this example, FIG. 8 is a graph showing the relationship between the total amount of donors in the counter-doped layer and the distance to the center of the counter-doped layer, and FIG. 9 is according to this example. 6 is a graph showing the results of numerical analysis of gate length dependence of threshold voltage in a semiconductor device.

The background acceptor concentration is N _B
Using the above substrate, a counter-doped layer having a donor concentration of N _D (x ₁ ) is formed in a region having a depth d _n from the substrate surface (FIG. 7). The region where the counter-doped layer is formed is I, the region deeper than it is II, and the threshold voltage V is determined by solving the one-dimensional Poisson equation for each region.
_th can be shown as follows.

[0024]

[Equation 1]

Here, W ₀ is the width of the depletion layer formed when a voltage corresponding to the threshold voltage V _th is applied to the gate electrode without forming the counter-doped layer, and W ₀ = √ (2φ _f Expressed as ε _Si / qN _B ).

As shown in equation (1), the threshold voltage V _th is
It is determined only by the distance R _p and the total donor amount Φ _D , which is in good agreement with the result shown in FIG. From this, it can be seen that the results obtained by the above-described analytical model are correct.
Solving equation (1) for Q _D ,

[0027]

[Equation 2]

[0028] Distance calculated based on equation (2)
Release R_pAnd total amount of donor Φ_DThe relationship with is shown in FIG. To illustrate
So that the threshold voltage V_thGiven a certain relationship
And the distance R_pAnd total amount of donor Φ_DAnd can decide
You. Threshold voltage V_thIs 0.4V, for example,
Distance R_pIs 15 nm and the total amount of donor Φ_D4.5 x 10
¹²cm ^-2Or, for example, the distance R_p25 nm
As the total amount of donor Φ_D7 x 10 ¹²cm^-2As well
Yes.

As shown in FIG. 9, the threshold voltage V _th on the long channel side can be set to approximately 0.4 V under any of the above conditions, but the influence of the counter doping on the short channel effect is different. Example 1 in which the distance R _p is 25 nm and the total donor amount Φ _D is 7 × 10 ¹² cm ⁻² ;
The background acceptor concentration N _B is 5 × 10 ¹⁷ c
As compared with Comparative Example 1 in which counter doping is not performed at m ⁻³ , Example 1 can suppress the decrease in the threshold voltage V _th slightly, but it is difficult to sufficiently suppress the short channel effect.

On the other hand, in Example 2 in which the distance R _p was 15 nm and the total donor amount Φ _D was 4.5 × 10 ¹² cm ⁻² , the background acceptor concentration N _B was 2 × 10 ¹⁸ cm 2.
^-3 , the short channel effect can be suppressed to the same extent as in Comparative Example 2 in which counter doping is not performed. Thus, in order to suppress the short channel effect, it is desirable to make the distance R _p as small as possible.

As described above, when the acceptor concentration N _B of the channel region 24 is constant and the channel region is counter-doped, the absolute value of the threshold voltage V _th is determined only by the distance R _p and the total donor amount Φ _D. It was verified that the threshold voltage V _th does not change even if the spread of the impurity distribution changes. Such a phenomenon has an extremely important meaning in the semiconductor process. That is, if the counter-doped layer is ion-implanted, the distance R _p can be controlled by the implantation energy as the projected range of the implanted ions, and the standard deviation ΔR _p, which is the spread of the impurity distribution, is changed by the subsequent heat treatment. Even in this case, it is possible to suppress the variation of the threshold voltage V _th .

Therefore, if the acceptor concentration N _A of the channel region 24 can be made high and constant, it is possible to manufacture a semiconductor device in which the fluctuation of the threshold voltage due to the influence of the thermal process is small and punch through can be prevented. Become. Next, a method of manufacturing a semiconductor device according to an embodiment of the invention will be described with reference to FIG.
This will be described with reference to FIG.

FIG. 10 shows the manufacture of a semiconductor device according to this embodiment.
11 is a process sectional view showing the method, and FIG. 11 is a semiconductor according to this embodiment.
It is a graph which shows the impurity distribution in an apparatus. embedded
An SOI layer 14 having a thickness of about 100 nm is formed on the oxide film 12.
A device isolation film 26 is formed on the SOI layer 14 of the completed SOI substrate.
It is formed (FIG. 10A). Next, N-type MOS transistor
For example, a total amount of 2 × 10 ¹³c
m^-3Of boron (B) ions at an acceleration energy of 20 keV
(Fig. 10 (b)). The implanted B is an SOI layer
As shown in FIG. 11A, the Gaussian distribution
Distributed in a shape.

Subsequently, the implanted B is diffused by heat treatment so that the boron concentration in the SOI layer 14 becomes uniform (FIG. 11B). The heat treatment condition at this time is that 2√ (Dt) is S when D is the diffusion coefficient of B and t is time.
It is desirable to set the thickness to be larger than the film thickness t _Si of the OI layer 14. This is because if the heat treatment conditions are set in this manner, the impurity concentration in the SOI layer 14 becomes uniform enough to be considered to be substantially constant.

For example, if the temperature is 1000 ° C., heat treatment may be performed for about 60 minutes, and if the temperature is 900 ° C., heat treatment may be performed for about 400 minutes. Since the diffusion constant D varies depending on the heat treatment temperature depending on the introduced impurities, it is desirable to set the heat treatment time appropriately. Further, in order to make the impurity concentration uniform, an impurity having a large diffusion constant D, such as B for a P-type impurity and P for an N-type impurity, is used.
(Phosphorus) is desirable.

When the implanted B is uniformly distributed in the SOI layer 14 by this heat treatment, the background acceptor concentration N _B becomes 2 × 10 ¹⁸ cm ⁻³ . In this way, it becomes possible to uniquely set the background acceptor concentration N _B by the implantation amount and the film thickness of the SOI layer 14. Next, counter doping is performed by the ion implantation method. For example, a total amount of 4 × 10 ¹² cm ⁻³ of antimony (Sb) ions is ion-implanted at an acceleration energy of 26 keV (FIG. 10C). According to the ion implantation method, the projection range, that is, the distance R _p can be arbitrarily changed by changing the implantation energy. Therefore, the implantation amount can be set using the graph shown in FIG.

After that, the gate electrode 22, the source diffusion layer 16, the drain diffusion layer 18, etc. are formed in the same manner as in the normal MOS transistor formation process (FIG. 10D). The impurity concentration distribution of the channel region of the MOS transistor thus formed is as shown in FIG.
By performing counter-doping in a substrate having a uniform concentration in this way, the threshold voltage V _th of the formed MOS transistor is uniquely determined by the distance R _p and the implantation amount Φ _D set during counter-doping. Even when the impurity profile of the counter-doped layer changes due to the subsequent heat treatment, it is possible to suppress the fluctuation of the threshold voltage V _th .

By optimizing the formation conditions of the counter-doped layer as shown in FIG. 9, it is possible to form a transistor having a desired threshold voltage V _th while reducing the short channel effect. In the above embodiment, S
The method of manufacturing the semiconductor device using the OI substrate has been described, but this is for the following reason. That is, when the SOI substrate is used, the buried oxide film 1 is formed just below the SOI layer 14.
The reason for this is that the impurities are hardly diffused in the direction of the buried oxide film 12 and the impurity concentration of the SOI layer 14 can be easily made constant.

However, if the impurity concentration on the surface side of the substrate can be made uniform, the present invention can be applied to a method for manufacturing a semiconductor device using a normal bulk substrate. Next, a method of manufacturing a semiconductor device according to another embodiment of the present invention will be described with reference to FIG.

FIG. 12 is a sectional view for explaining the method of manufacturing a semiconductor device according to this embodiment. Bulk silicon substrate 1
After the element isolation film 26 is formed on the substrate 0, impurities for punch-through prevention are introduced in the same manner as the embodiment shown in FIG. Next, the impurities introduced by the heat treatment are thermally diffused so that the impurity concentration on the surface side of the silicon substrate 10 becomes substantially uniform. At this time, since the introduced impurities can diffuse deep into the silicon substrate, it is difficult to form a uniform layer as in the embodiment shown in FIG.

However, since the present invention can be applied if the impurity concentration on the substrate surface side does not change significantly in the heat treatment of the subsequent step, it is sufficient that at least the impurity concentration on the substrate surface side is uniform. Note that the impurity diffusion layer may be formed by ion implantation with different implantation energies a plurality of times so that the impurity concentration in the depth direction is uniform to a sufficiently deep region. Alternatively, a high-concentration impurity substrate having an impurity concentration sufficient to prevent punch-through between the source and the drain may be used.

After the impurity diffusion layer 28 having a uniform concentration is formed on the front surface side of the silicon substrate 10 in this way, FIG.
Counter-doping is performed in the same manner as in the example shown in (c) to adjust the threshold voltage of the transistor. Then
The gate electrode 22, the source diffusion layer 16, the drain diffusion layer 18, etc. are formed in the same manner as in the normal MOS transistor formation process (FIG. 12).

When the semiconductor device is manufactured in this way,
The present invention can also be applied to the case of using a bulk semiconductor substrate. That is, punch-through can be prevented without increasing the threshold voltage, and a semiconductor device in which the fluctuation of the threshold voltage due to the thermal process is small can be formed on the bulk substrate. Although the above embodiments have been described by limiting to the N-type MOS transistor, they can be applied to the P-type MOS transistor as they are by changing the conductivity type of the dopant. For example, after the P ions are ion-implanted, heat treatment may be performed to make the impurity concentration in the substrate constant, and then counter doping using indium (In) ions may be performed.

[0044]

As described above, according to the present invention, the first impurity doping step of doping the semiconductor layer with the first impurity having the first conductivity type, and the semiconductor doped with the first impurity A heat treatment step of heat-treating the layer to make the concentration of the first impurity in the semiconductor layer substantially uniform; and a second impurity doping step of doping the heat-treated semiconductor layer with a second impurity having a second conductivity type. And the first impurity and the second
If the semiconductor device is manufactured by the transistor forming step of forming the MIS transistor in the semiconductor layer doped with the impurity, the fluctuation of the threshold voltage due to the heat treatment of the subsequent step can be reduced.

In the first impurity doping step, MI is increased by increasing the doping amount of the first impurity.
If the threshold voltage of the MIS transistor is reduced to a desired value by reducing the short channel effect of the S transistor and increasing the doping amount of the second impurity in the second impurity doping step, increase the threshold voltage. Without short channel effect can be prevented.

In the method of manufacturing a semiconductor device described above, if the SOI layer of the SOI substrate is doped with the first impurity, the first impurity can be easily made uniform in the heat treatment step. Further, in the heat treatment step, the diffusion constant of the first impurity D, and the heat treatment time t, the thickness of the SOI layer is taken as t _Si, 2√ (Dt) is the temperature and time that is larger than t _Si If heat-treated, the first in the SOI layer
The distribution of the impurities can be made substantially uniform.

[Brief description of drawings]

FIG. 1 is a diagram showing the structure of a semiconductor device used for numerical analysis in this example.

FIG. 2 is a graph showing a result obtained by numerical analysis of gate length dependence of a threshold voltage in a conventional semiconductor device.

FIG. 3 is a graph showing an impurity distribution in a channel region in a semiconductor device used for numerical analysis.

FIG. 4 is a graph showing the relationship between the threshold voltage and the depth of the counter-doped layer.

FIG. 5 is a graph showing the relationship between the threshold voltage and the distance to the center of the counter-doped layer.

FIG. 6 is a graph showing the relationship between the threshold voltage and the width of the counter-doped layer.

FIG. 7 is a diagram showing an outline of an analytical model used in this example.

FIG. 8 is a graph showing the relationship between the total amount of donors in the counter-doped layer and the distance to the center of the counter-doped layer.

FIG. 9 is a graph showing the results of numerical analysis of the gate length dependence of the threshold voltage in the semiconductor device according to the present example.

FIG. 10 is a process sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 11 is a graph showing an impurity distribution in a semiconductor device according to an example of the present invention.

FIG. 12 is a cross-sectional view illustrating the method of manufacturing a semiconductor device according to another embodiment of the present invention.

[Explanation of symbols]

 10 ... Silicon substrate 12 ... Buried oxide film 14 ... SOI layer 16 ... Source diffusion layer 18 ... Drain diffusion layer 20 ... Gate oxide film 22 ... Gate electrode 24 ... Channel region 26 ... Element isolation film 28 ... Impurity diffusion layer

Claims (4)

[Claims] 1. A first semiconductor layer having a first conductivity type in a semiconductor layer
A first impurity doping step of doping the impurity of, and a heat treatment step of heat-treating the semiconductor layer doped with the first impurity to make the concentration of the first impurity in the semiconductor layer substantially uniform, A second conductive type second layer on the heat-treated semiconductor layer;
A second impurity doping step of doping the impurity of 1. and a transistor forming step of forming a MIS transistor using the semiconductor layer doped with the first impurity and the second impurity as a channel region. And a method for manufacturing a semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein in the first impurity doping step, a short channel effect of the MIS transistor is reduced by increasing a doping amount of the first impurity, In the second impurity doping step, the threshold voltage of the MIS transistor is lowered to a desired value by increasing the doping amount of the second impurity. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor layer is an SOI layer in an SOI substrate. 4. The method of manufacturing a semiconductor device according to claim 3, wherein in the heat treatment step, a diffusion constant of the first impurity is D, a heat treatment time is t, and a film thickness of an SOI layer is t _Si. 2. A method of manufacturing a semiconductor device, characterized in that heat treatment is performed at a temperature and for a time at which 2√ (Dt) becomes larger than t _Si .