JPH0982983A - Semiconductor device and manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a semiconductor device smaller than and make an integration degree higher than conventional devices by forming a cavity section under an insulating layer containing a section, to which a semiconductor element is formed, through etching from a surface, to which the insulating layer is shaped. SOLUTION: An opening section 7 is formed onto an oxide film 2 and a nitride film 3, a cavity section is formed just under a section, to which a single crystal silicon layer 4 is formed, and the cavity section functions as a diaphragm 8. Electronic circuits 9 and 10 are formed to sections, to which the oxide film 2 and the nitride film 3 are not shaped, and connected electrically through the single crystal silicon layer 4 and aluminum electrodes 5. The internal resistance value of the single crystal silicon layer 4 is changed by the physical displacement of the diaphragm 8 by pressure generated from the outside, the change is detected as the fluctuation of voltage and transmitted to the electronic circuits 9, 10, signal processing such as amplification, temperature compensation, dispersion correction, etc., is conducted, and a pressure value is output.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly to a semiconductor pressure sensor and a semiconductor acceleration sensor used in automobiles, home appliances and other industrial fields, and a method for manufacturing them. .

[0002]

2. Description of the Related Art Pressure sensors and acceleration sensors for converting pressure and acceleration into electric signals have been widely used in the field of automobiles, but the demand for them has further increased with the progress of electronics in automobiles. . Since the 1970s, electronic control of automobile engines has been adopted to realize exhaust gas regulations and low fuel consumption, for example, MAP (Manifold
Absolute Pressure), atmospheric pressure, transmission oil pressure, engine oil pressure and many other pressure sensors have come to be used. Further, since the 1990's, these sensors have come to be used for traveling, electronic control of drive systems, equipment for failure diagnosis function, etc. from the viewpoint of improving vehicle safety and environmental protection. For example, acceleration sensors have come to be used in antilock brake systems, active suspension systems, and in recent years airbag systems. In addition to this, pressure sensors are used in home appliances, such as dust control for vacuum cleaners, blood pressure and blood vessel sound detection for electronic blood pressure monitors, compressor control and atmospheric pressure measurement for packaged air conditioners, and water level control for fully automatic washing machines. The range of applications is expanding, such as for water level control in fully automatic baths and water pressure measurement, as well as gas pressure measurement in other industrial plants and water pressure measurement in diver's watches. Also in the acceleration sensor,
Its applications such as vibration sensors for industrial equipment are being further expanded.

A pressure sensor or an acceleration sensor made of a semiconductor uses a thin portion (diaphragm) formed by a silicon fine processing technique on a semiconductor substrate as a movable portion, and stress generated by displacement of the diaphragm is piezoresistive effect. It is common to use a method of converting the strain gauge resistance into a change in resistance value and outputting this as a voltage. As a method of converting the displacement of the diaphragm into an electric signal, there is a method of utilizing electrostatic capacity, but at present, the method of utilizing piezo resistance as described above is the mainstream. Since the output voltage is weak and has a large variation, amplification and variation correction are performed by a hybrid integrated circuit or the like.

The semiconductor integrated circuit has realized high integration, high performance, and low cost due to the development of silicon fine processing technology. This also applies to other semiconductor devices such as a semiconductor pressure sensor and a semiconductor acceleration sensor.

FIG. 23 shows a sectional structure of a general IC atmospheric pressure sensor. Here, 20 is a p-type silicon substrate, 21 is an n + type buried layer, 22 is an n-type epitaxial layer, and 23 is p.
+ Type element isolation region, 24 is a p-type diffusion layer, 25 is a base region, 26 is a collector region, 27 is an emitter region, 28 is an aluminum electrode, 29 is a silicon oxide film (hereinafter referred to as an oxide film), 30 is a silicon nitride film ( Hereinafter, a nitride film) and 31 are thin portions (diaphragms). The IC atmospheric pressure sensor shown in FIG. 23 has a sensor portion p on the diaphragm 31.
A strain gauge resistor using an n-junction is formed, and a signal processing circuit from the strain gauge resistor is formed in the peripheral portion of the sensor portion and the signal processing circuit portion are integrated on the same substrate. . Here, the signal processing circuit unit is simply np.
Only n-bipolar transistors are shown. Such an IC atmospheric pressure sensor is manufactured by the method shown in FIG. Here, 32 is a silicon substrate, 33 is a sensor unit, 34 is a signal processing circuit unit, and 31 is a diaphragm. The steps in FIG. 24 are as follows. (A) Silicon substrate 32
The sensor unit 33 and the signal processing circuit unit 34 are formed on the top. (B) The silicon substrate 32 is thinned by etching from the back surface side, and the diaphragm 31 is formed under the sensor portion 33.
To form The sensor section 33 and the signal processing circuit section 34 are formed by a normal semiconductor integrated circuit manufacturing process.

As a method for forming the diaphragm 31, isotropic etching using an acidic solution such as a hydrofluoric nitric acid solution, TMAH (tetramethylammonium hydroxide), EDP (ethylenediaminepyrocatechol), an aqueous hydrazine solution, Anisotropic etching using an alkaline solution such as a KOH solution (KOH / isopropanol, KOH / hydrazine mixed solution, etc.) is the mainstream.

[0007]

However, in the conventional semiconductor pressure sensor and semiconductor acceleration sensor, as described above, after the sensor portion is formed on one main surface side of the silicon substrate 32, the silicon is applied from the other main surface side. The substrate 31 is thinned by etching to form the diaphragm 31. For this reason, it is necessary to expose the mask patterns on both surfaces of the semiconductor substrate 32, and in order to secure a mask pattern alignment margin on both surfaces of the substrate, the sensor portion 33 where the diaphragm 31 is formed and the signal processing circuit portion 34 are formed.
The distance between and must be large.

Further, since the area of the opening is usually larger than the area of the bottom in the etching of silicon, the area of the opening of the etching mask formed on the back surface of the substrate must be larger than that of the actual sensor 33. This also causes a large distance between the sensor unit 33 and the signal processing circuit unit 34.

In addition, the thickness of the diaphragm 31 is currently 1
Although it is about 0 to 100 μm, it is difficult to achieve a more uniform thin layer by this method because the etching amount and the diaphragm thickness are controlled by the etching time of silicon. These problems are problems in achieving miniaturization and miniaturization of the entire sensor.

Besides, since the mask pattern is exposed on both sides of the semiconductor substrate 1, the surface of the semiconductor substrate 32 is covered with a protective film, but the protective film is scratched when the silicon wafer is transported or handled. There are cases. When these scratches are generated on the device formation surface side of the sensor unit 33, the signal processing circuit unit 34, etc., it is impossible to properly manufacture the device, and therefore, it may cause insulation failure in the formed semiconductor element and electronic circuit. May be.

In addition, when a flaw or the like occurs on the surface where the diaphragm 31 is formed, pin holes are formed in the etching mask portion, the silicon layer other than the diaphragm forming portion 31 is thinned, and cracks occur in the diaphragm portion 31. May locally generate weak areas. These are problems such as a decrease in manufacturing yield in the actual manufacturing process.

[0012]

According to the present invention, a semiconductor element formed on an insulating layer formed on a semiconductor substrate and an electronic circuit formed on the semiconductor substrate or on the insulating layer are electrically connected to each other. Are connected, in the semiconductor substrate, by performing etching from the surface on which the insulating layer is formed,
It is intended to provide a semiconductor device characterized in that a cavity is provided below the insulating layer including a portion where the semiconductor element is formed. Further, a step of forming an insulating layer on the semiconductor substrate, a step of forming a semiconductor element on the insulating layer,
A step of forming an electronic circuit on the semiconductor substrate or the insulating layer, a step of electrically connecting the semiconductor element and the electronic circuit, in the semiconductor substrate, etching from the surface on which the insulating layer is formed A part of the semiconductor substrate under the insulating layer including the portion where the semiconductor element is formed is removed to form a cavity under the insulating layer including the portion where the semiconductor element is formed. The present invention is intended to solve the above-mentioned problems by using a method for manufacturing a semiconductor device characterized by including the step of:

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings together with each embodiment.

(Embodiment 1) FIG. 1 is a sectional view showing a first embodiment of a semiconductor device according to the present invention. Here, there is a region where the oxide film 2 and the nitride film 3 are stacked on the silicon substrate 1. A single crystal silicon layer 4 is formed on the oxide film 2 and the nitride film 3, and an aluminum electrode 5 is connected thereto. The single crystal silicon layer 4 and the aluminum electrode 5 are insulated by the insulating film 6 except for the connection portion. Oxide film 2
And an opening 7 is formed on the nitride film 3, and a cavity is provided in the oxide film 2 and the nitride film 3 immediately below the portion where the single crystal silicon layer 4 is formed.
This portion becomes the diaphragm 8. Electronic circuits 9 and 10 are formed on a portion of the silicon substrate 1 where the oxide film 2 and the nitride film 3 are not formed.
And 10 are single crystal silicon layer 4 and aluminum electrode 5.
Are electrically connected through. Here, only the pMOS transistor 9 and the nMOS transistor 10 are shown as electronic circuits. Diaphragm 8 as a whole
Then, the electronic circuits 9 and 10 are covered with the passivation film 11.

FIG. 2 is a plan view showing a first embodiment of the semiconductor device according to the present invention. Here, reference numerals 1 to 8 are the same as those in FIG. 1, and 13 is a contact portion between the single crystal silicon layer 4 and the aluminum electrode 5. FIG. 1 is a schematic cross-sectional view taken along the broken line AA 'in FIG. In FIG. 2, the electronic circuit parts 9 and 10 are omitted, and the diaphragm 8 part is mainly shown. The semiconductor device shown in FIGS. 1 and 2 is a piezoresistive semiconductor pressure sensor. In the above configuration, due to the physical displacement of the diaphragm 8 due to the pressure generated from the outside,
When stress is generated in the single crystal silicon layer 4, the internal resistance value of the single crystal silicon layer 4 changes, and this change in internal resistance value is detected as a change in voltage and sent to the electronic circuits 9 and 10 for amplification. Signal processing such as temperature compensation and variation correction is performed, and the pressure value is output. This semiconductor device can also be used as a piezoresistive semiconductor acceleration sensor.

FIG. 3 is a process chart showing a method of manufacturing the semiconductor device shown in this embodiment. Here, reference numerals 1 to 11 are the same as those in FIG. 1, and 12 is an amorphous silicon layer. The steps in FIG. 3 are as follows. (A) The oxide film 2 and the nitride film 3 are formed on the silicon substrate 1. (B) The silicon film 1 is formed by patterning the oxide film 2 and the nitride film 3.
After exposing a part of it, an amorphous silicon layer 12 is laminated. (C) The amorphous silicon layer 12 is recrystallized from the exposed portion of the silicon substrate 1 to form the single crystal silicon layer 4 on the nitride film 3. (D) After forming the insulating film 6 and performing patterning, the aluminum electrode 5 is formed.
(E) After forming the passivation film 11, the opening 7 is formed.
Is formed to expose a part of the silicon substrate 1. (F) Isotropic etching is performed from the opening 7 to form the silicon substrate 1.
Is removed to form the diaphragm 8. Although the electronic circuits 9 and 10 are formed on the silicon substrate 1 after the single crystal silicon layer 4 is formed, this portion is omitted in FIG. Through the above steps, the semiconductor device shown in FIG. 1 can be obtained.

An example in which the above semiconductor device is specifically manufactured by using the process shown in FIG. 3 is shown below. Plane orientation <10
0>, diameter 125 mm, thickness 625 μm, specific resistance 0.1
On a silicon substrate of a p-type silicon wafer of Ωcm, an oxide film is formed by thermal oxidation and a nitride film is formed by a low pressure CVD method. Here, the oxide film is formed in an oxygen / hydrogen mixed gas (here, O ₂ : H ₂ = 4: 6) under conditions of a temperature of 1000 ° C. and an oxidation rate of 4.3 nm / min and a thickness of 0.8.
A μm oxide film was formed. The temperature of the nitride film is 80
0 ° C., SiH ₄ flow rate 5 sccm, NH ₃ flow rate 300 sc
cm, SiH ₄ partial pressure 0.3 Torr, deposition rate 70 nm
/ Min condition to deposit a 0.3 μm thick nitride film. Next, the oxide film and the nitride film are patterned by RIE (reactive ion etching).

After exposing a part of the silicon substrate of the p-type silicon wafer, an amorphous silicon layer is laminated by a low pressure CVD method. Here, the temperature is 570 ° C and the pressure is 18 Tor.
r, Si ₂ H ₆ flow rate 10 sccm, H ₂ flow rate 3 slm,
The deposition rate was 30 nm / min, and the thickness was 0.
A 2 μm amorphous silicon layer was laminated. Subsequently, the amorphous silicon layer is irradiated with a pulse beam of an argon laser having a diameter of 50 μm to melt the amorphous silicon layer from the exposed portion of the p-type silicon wafer, and then recrystallized to form a nitride film on the nitride film. A 0.2 μm thick single crystal silicon layer is formed. Further, an oxide film having a thickness of 1.0 μm is laminated by a low pressure CVD method, and after patterning by RIE, an aluminum electrode is formed by a sputtering method. The oxide film was formed at a temperature of 800 ° C., a Si ₂ H ₆ flow rate of 3 sccm, an N ₂ O flow rate of 300 sccm, a Si ₂ H ₆ partial pressure of 0.15 Torr, and a deposition rate of 45 nm / min. Then, as a passivation film, an NSG film (No.
n Silicate Glass) and then R
An opening is formed by IE to expose a part of the p-type silicon wafer. Finally, isotropic etching is performed from the opening with a hydrofluoric nitric acid-based solution to remove a part of the p-type silicon wafer and form a diaphragm having a thickness of 3.3 μm in the portion where the single crystal silicon layer is formed. Here HF:
A mixed solution of HNO ₃ : CH ₃ COOH = 1: 12: 17 was used.

The piezoresistive semiconductor pressure sensor shown in the first embodiment is a semiconductor pressure sensor that is smaller and has a higher degree of integration than ever before. In addition, since the element and the diaphragm are formed from the same main surface side on the semiconductor substrate by manufacturing in the process shown in the first embodiment, the semiconductor pressure sensor described above can be manufactured and the semiconductor pressure sensor can be manufactured. It is possible to improve the manufacturing yield of the sensor.

The planar layout of the semiconductor pressure sensor shown in this embodiment is not limited to that shown in FIG. 2 and can take various forms. 5 to 7 show one example thereof. Here, reference numerals 1 to 13 are the same as those in FIG.
The size can also be set according to the rules of the usage process. Further, in this embodiment, the oxide film-nitride film-single crystal silicon layer is formed in order from the bottom, but it is also possible to form the nitride film-oxide film-single crystal silicon layer in this order.

Method of manufacturing semiconductor pressure sensor shown in this embodiment
The method is not limited to the specific examples described above,
It is possible to apply various methods and conditions. An example
For example, the amorphous silicon layer may be formed by the low pressure CVD method described above,
Glow discharge method, arc discharge method, reactive sputtering method, thermal C
VD method, photo CVD method, plasma CVD method, vapor deposition method, etc.
It is possible to use and laminate. The lamination conditions are
For example, in the glow discharge method, SiH_Four, Si₂H₆, SiC
l_FourEtc. can be used. In this case, SiH
_FourThen pressure 0.5-2.0 Torr, temperature 250-35
Amorphous at 0 ° C and in the range of 50 to 450 Hz
It is possible to stack quality silicon layers. Also, non
After depositing polycrystalline silicon in addition to crystalline silicon, re-crystallize
It is also possible to carry out crystallization. As a lamination method, normal pressure
CVD method, low pressure CVD method, plasma CVD method, etc.
It is possible to In this case, for example, the low pressure CVD method
Indicates a pressure of 0.1 to 5.0 Torr and a temperature of 500 to 900 ° C.
At SiH_Four, Si₂H₆, SiH₂Cl₂Such as hydrogen
Alternatively, it can be diluted with nitrogen. SiH _FourTo
When diluted with nitrogen, SiH_FourThe concentration is in the range of 20-30%
It can be carried out in the enclosure. Also SiH_FourThe thermal decomposition of
If a polycrystalline silicon layer is stacked for_FourTo
No need to dilute.

Although the single crystal silicon layer is formed by irradiating a pulse beam of an argon laser in this embodiment, a CW laser beam, a Q switch pulse laser beam, an electron beam beam, an excimer laser beam or the like is used. Is also possible. This can be similarly applied to the case where the polycrystalline silicon layer is single-crystallized. In addition to the laser annealing solid phase growth method described above, it is also possible to perform single crystallization of an amorphous silicon layer or a polycrystalline silicon layer by a solid phase growth method using heat treatment. In this case, the amorphous silicon layer is heated to a temperature of 500 to 1200 ° C., the polycrystalline silicon layer is heated to a temperature of 800 to 1200 ° C. in an atmosphere of hydrogen or nitrogen by an infrared lamp or a strip heater to obtain a single crystal. Can be converted.

In addition to the above-mentioned thermal oxidation, an atmospheric pressure CVD method, a low pressure CVD method, or a plasma CVD method can be used for forming the oxide film. In the CVD method, TEOS (tatrae) is used.
It is also possible to use a thoxysilane).
Further, in forming the nitride film, thermal nitriding method, atmospheric pressure CVD method, low pressure C
It is possible to use the VD method or the plasma CVD method.
For the solution for isotropic etching of Si, HF / HNO ₃ / H ₂ O and HF / HN are used as the hydrofluoric nitric acid-based solution.
O ₃ / CH ₃ COOH, HF / HNO ₃ , HF / HNO
₃ / H ₂ , HF / NHO ₃ / NaClO ₂ , HF / HN
O ₃ / CH ₃ COOH / NaClO ₂ , HF / HNO ₃
/ HClO ₄ , HF / HNO ₃ / CH ₃ COOH / HC
lO ₄ , HF / HNO ₃ / Na ₂ HPO ₄ , HF / HN
It is possible to use a mixture of O ₃ / CH ₃ COOH / Na ₂ HPO _4, etc. In addition to the hydrofluoric nitric acid-based solution, NH ₄ F / HF, NH ₄ F / H ₂ O ₂ , NH ₄ F /
It is possible to use a mixed liquid such as H ₂ O ₂ / H ₂ O. In addition, isotropic etching of Si can be performed by cylindrical plasma etching.

In addition, as shown in FIG. 4, the exposed p-type silicon substrate portion for single crystallization of the amorphous silicon layer or the polycrystalline silicon layer is commonly used as an opening for isotropic etching. It is also possible.

FIG. 4 is another example of a process chart showing the method of manufacturing the semiconductor device shown in this embodiment. Here, reference numerals 1 to 12
Are the same as in FIG. The steps in FIG. 4 are as follows. (A) The oxide film 2 and the nitride film 3 are formed on the silicon substrate 1. (B) After patterning the oxide film 2 and the nitride film 3 to expose a part of the silicon substrate 1,
The amorphous silicon layer 12 is laminated. (C) The amorphous silicon layer 12 is recrystallized from the exposed portion of the silicon substrate 1 to form the single crystal silicon layer 4 on the nitride film 3.
(D) After forming the insulating film 6 and performing patterning,
The aluminum electrode 5 is formed. (E) After forming the passivation film 11, patterning is performed to form the opening 7. In the steps (d) to (e), a part of the silicon substrate 1 exposed to recrystallize the amorphous silicon layer 12 is continuous with the single crystal silicon layer 4, and this part is opened. It will be Part 7. (F) Isotropic etching is performed through the opening 7 to remove the single crystal silicon layer 4 and a part of the silicon substrate 1 to form the diaphragm 8. Although the electronic circuits 9 and 10 are formed on the silicon substrate 1 after the single crystal silicon layer 4 is formed, this portion is omitted in FIG. Further, in FIG. 4, the diaphragm 8 is mainly shown, and the portion where the electronic circuit 9 is formed is omitted. The semiconductor device shown in FIG. 1 can be obtained by the steps shown in FIG. In this case, the process is the same as that of FIG. 3 except for the position where the opening is formed.
It is possible to use the same conditions and methods applicable to the step shown in FIG.

(Embodiment 2) FIG. 8 is a plan view showing a second embodiment of the semiconductor device according to the present invention. Here, reference numerals 1 to
13 is the same as FIG. In FIG. 2, one opening 7 is provided for one diaphragm, but in FIG. 8, a plurality of openings 7 (four in FIG. 8) are provided for one diaphragm. As a result, the opening 1 is formed when the diaphragm 8 is formed.
Since the etching amount of each silicon substrate can be reduced, the diaphragm 8 having a large area can be formed in a shorter time.
Can be formed. In addition, when the silicon substrate 1 is etched and only one opening 7 is formed, the silicon substrate 1 at the bottom of the cavity is
It is possible to suppress the instability of the mechanical structure of the entire sensor due to the excessively thin thickness by using a plurality of openings 7. According to FIG. 8, the single crystal silicon layer 4 is arranged in the center of the diaphragm 8 and is connected to the aluminum electrodes 5 at a predetermined interval without dividing the center. This embodiment is the first except for the number of openings.
The structure is similar to that of the above embodiment. Therefore, the method for manufacturing the semiconductor device shown in this embodiment is the same as the method for manufacturing the semiconductor device shown in the first embodiment, and the same conditions as those in the first embodiment can be applied. For example, the planar layout is not limited to that shown in FIG. 8 and can take various forms. FIG. 9 shows an example thereof. Here, reference numerals 1 to 13 are the same as those in FIG. According to FIG. 9, the L-shaped single crystal silicon layer 4 is formed on the center side of the plurality of openings 7.
The electrodes are divided and arranged, the aluminum electrodes 5 are connected, and the resistance value of each single crystal silicon layer 4 is detected.

(Third Embodiment) FIG. 10 is a plan view showing a third embodiment of the semiconductor device according to the present invention. Code 1 here
13 are the same as in FIG. According to FIG. 10, the structure is such that the silicon substrate 1 and the single crystal silicon layer 4 arranged on the periphery of the diaphragm 8 are connected by the aluminum electrode 5 via the contact portion 13, and the opening 7 is provided on the periphery thereof. I am trying.

Although the opening 7 and the diaphragm 8 are provided inside the electronic circuits 9 and 10 in FIG. 2, the periphery of the electronic circuit is removed by etching in FIG. 10 to form the diaphragm 8. Thus, for example, when the sensors are arranged in a matrix, the semiconductor device shown in the first and second embodiments and the semiconductor device shown in the third embodiment have the following characteristic differences.

When the semiconductor devices are arranged on a chip having the same area, the semiconductor device shown in the first and second embodiments can improve the integration degree of the sensor portion as compared with the semiconductor device shown in the third embodiment. Becomes On the other hand, when they are arranged on a chip with the same degree of integration, in the semiconductor device shown in Example 3,
The sensor portion can cover a wider area than the semiconductor devices shown in the first and second embodiments. This embodiment has the same structure as that of the first embodiment except the position of the diaphragm 8. Therefore, the method of manufacturing the semiconductor device shown in this embodiment is the same as the method of manufacturing the semiconductor device shown in the first embodiment, and each condition in each step shown in the first embodiment can be similarly applied. .

Further, the planar layout is not limited to that shown in FIG. 10 and can take various forms. FIG. 11 shows an example. Here, reference numerals 1 to 13 are the same as those in FIG. In the case of FIG. 11, the silicon substrate 1 is exposed inside the diaphragm 8, the single crystal silicon layer 4 is divided into four parts around the diaphragm 8, and the silicon substrate 1 and the single crystal silicon layer 4 are connected to the aluminum electrode 5.
And connected to form a pressure sensor.

(Embodiment 4) FIG. 12 is a sectional view showing a fourth embodiment of the semiconductor device according to the present invention. Here, there is a region where the nitride film 3 and the oxide film 2 are laminated on the silicon substrate 1. A single crystal silicon layer 4 and electronic circuits 9 and 10 are formed on the nitride film 3 and the oxide film 2. The single crystal silicon layer 4 and the electronic circuits 9 and 10 are electrically connected through the aluminum electrode 5. Here, as the electronic circuits 9 and 10, the pMOS transistors 9 and n are used.
Only the MOS transistor 10 is shown. The single crystal silicon layer 4 and the electronic circuits 9 and 10 are insulated by the insulating film 6 except for the connection portion with the aluminum electrode 5.
An opening 7 is formed on the oxide film 2 and the nitride film 3, and a cavity is provided in the oxide film 2 and the nitride film 3 immediately below the portion where the single crystal silicon layer 4 is formed. This portion becomes the diaphragm 8. The diaphragm 8 and the electronic circuits 9 and 10 as a whole are covered with a passivation film 11.

The semiconductor device shown in FIG. 12 is a piezoresistive semiconductor acceleration sensor. In the above structure, stress is generated in the single crystal silicon layer 4 due to the physical displacement of the diaphragm 8 due to the acceleration applied from the outside, so that the internal resistance value of the single crystal silicon layer 4 is changed, and the change of the internal resistance value is caused by the voltage change. Is sent to the electronic circuits 9 and 10 as
Signal processing such as amplification, temperature compensation, and variation correction is performed, and the acceleration value is output. This semiconductor device can also be used as a piezoresistive semiconductor pressure sensor.

FIG. 13 is a process chart showing a method of manufacturing the semiconductor device shown in this embodiment. Reference numerals 1 to 11 in FIG.
40 is SOI (Silicon On Insulator)
A substrate, 41 is a semiconductor element, 42 is an electronic circuit, 43 is an opening, and 44 is a diaphragm. The process according to FIG. 13 is as follows. (A) In the SOI substrate 40 having the single crystal silicon layer 4 formed on the nitride film 3 and the oxide film 2, (b) the semiconductor element 41, the electronic circuit 42, and the opening 43 are formed on the single crystal silicon layer 4. . (C) An opening 43 is formed on the nitride film 3 and the oxide film 2. (D) A part of the silicon substrate 1 under the nitride film 3 and the oxide film 2 where the semiconductor element 41 is formed is removed by etching through the opening 43, and the diaphragm 44 is formed. Through the above steps, the semiconductor device shown in FIG. 12 can be obtained.
Although not shown, the semiconductor element 41 and the electronic circuit 4
2 is electrically connected.

An example in which the above semiconductor device is specifically manufactured by using the process shown in FIG. 13 is shown below. An SOI substrate having a nitride film thickness of 0.1 μm, an oxide film thickness of 0.2 μm, and a single crystal silicon layer thickness of 0.2 μm is prepared. This S
The OI substrate 40 is a p-type silicon substrate having a plane orientation of <100>, a diameter of 125 mm, a thickness of 625 μm, and a specific resistance of 10 Ωcm, and nitrogen ions and oxygen ions are implanted into the silicon substrate to form a nitride film and an oxide film. It was created by In this SOI substrate, an oxide film having a thickness of 0.8 μm is stacked on the single crystal silicon layer by a plasma CVD method, patterned by RIE, and then an aluminum electrode is formed by a sputtering method. The oxide film is formed at a temperature of 800 ° C., a Si ₂ H ₆ flow rate of 3 sccm, and N ₂
O flow rate 300 sccm, Si ₂ H ₆ partial pressure 0.15 Tor
r and the deposition rate was 45 nm / min. Then, as a passivation film, BPSG having a thickness of 1.0 μm
Laminate films (Borono-Phospho Silicate Glass).

Next, the oxide film and the nitride film are patterned by RIE to form openings to expose a part of the p-type silicon substrate under the SOI substrate. Finally, perform isotropic etching with a nitric acid-based solution from the opening,
A part of the silicon substrate is removed, and a diaphragm having a thickness of 2.3 μm is formed on the part where the single crystal silicon layer is formed. Here, HF: HNO ₃ : CH ₃ COOH = 1: 1
A 2:17 mixture was used.

The piezoresistive semiconductor acceleration sensor shown in the fourth embodiment is a semiconductor acceleration sensor which is smaller in size and higher in integration than conventional ones. Further, since the element and the diaphragm are formed from the same main surface side on the semiconductor substrate by manufacturing in the process shown in the fourth embodiment, the semiconductor acceleration sensor described above can be manufactured and the semiconductor acceleration sensor can be manufactured. It is possible to improve the manufacturing yield of the sensor. In addition, in this embodiment, the electronic circuit is formed in the single crystal semiconductor layer on the insulating layer. By using the electronic circuit having the SOI structure, it is possible to realize high speed, high integration, small size, and improved reliability of the electronic circuit.

Although the SOI substrate used in this embodiment is manufactured by the ion implantation method, it may be manufactured by the direct bonding method. For example, a nitride film and an oxide film may be laminated in this order on a silicon substrate, and then the oxide film and another silicon substrate may be bonded together.
In this case, it is possible to use the same conditions and methods as shown in the seventh embodiment described later.

Regarding other details of this embodiment,
It is possible to apply the same conditions and methods as those shown in the examples.

(Embodiment 5) FIG. 14 is a sectional view showing a fifth embodiment of a semiconductor device according to the present invention. Here, 14 is an SOI substrate, a first single crystal silicon layer 16 is formed on the first oxide film 15, and a second oxide film 2 and a second oxide film 2 are formed on the first single crystal silicon layer 16. There is a region where the nitride film 3 is laminated. A second single crystal silicon layer 4 is formed on the second oxide film 2 and the nitride film 3, and an aluminum electrode 5 is connected to the second single crystal silicon layer 4. The second single crystal silicon layer 4 and the aluminum electrode 5 are insulated by the insulating film 6 except for the connection portion. An opening 7 is formed on the second oxide film 2 and the nitride film 3, and the opening 7 is formed immediately below the second oxide film 2 and the nitride film 3 in the portion where the second single crystal silicon layer 4 is formed. Is provided with a hollow portion, and this portion becomes the diaphragm 8. In addition, the first single crystal silicon layer 1
6, electronic circuits 9 and 10 are formed, and the electronic circuits 9 and 10 are electrically connected to each other through the second single crystal silicon layer 4 and the aluminum electrode 5. Here, as an electronic circuit, a pMOS transistor 9 and an nM are used.
Only the OS transistor 10 is shown. The diaphragm 8 and the electronic circuits 9 and 10 as a whole are covered with a passivation film 11.

The semiconductor device shown in FIG. 14 is a piezoresistive semiconductor pressure sensor, and its operation is similar to that of the semiconductor pressure sensor shown in the first embodiment. This semiconductor device can also be used as a piezoresistive semiconductor acceleration sensor.

FIG. 15 is a process chart showing a method of manufacturing the semiconductor device shown in this embodiment. Here, 2 is the second oxide film, 3
Is a nitride film, 4 is a second single crystal silicon layer, 12 is an amorphous silicon layer, 14 is an SOI substrate, 15 is a first oxide film,
16 is a first single crystal silicon layer, 41 is a semiconductor element, 4
2 is an electronic circuit, 43 is an opening, and 44 is a diaphragm. The steps in FIG. 15 are as follows. (A) In the SOI substrate 14 in which the first single crystal silicon layer 16 is formed on the first oxide film 15, (b) The nitride film 3 and the second oxide film are formed on the first single crystal silicon layer 16. Form 2. (C) After patterning, the amorphous silicon layer 12 is formed on the first single crystal silicon layer 16 and the second oxide film 2. (D) The amorphous silicon layer 12 is irradiated with an argon laser to recrystallize the amorphous silicon layer 12 from the exposed portion of the first single crystal silicon layer 16,
A second single crystal silicon layer 4 is formed on the second oxide film 2. (E) Semiconductor element 4 on second single crystal silicon layer 4
1, an electronic circuit 42 and an opening 43 are formed on the first single crystal silicon layer 16. (F) A portion of the first single crystal silicon layer 16 under the nitride film 3 and the second oxide film 2 where the semiconductor element 41 is formed is removed by etching through the opening 43 to form the diaphragm 44. . Through the above steps, the semiconductor device shown in FIG. 14 can be obtained.

An example in which the above semiconductor device is specifically manufactured by using the process shown in FIG. 15 is shown below. Plane orientation <1
00>, diameter 125 mm, thickness 625 μm, specific resistance 0.
A nitride film is formed by a plasma CVD method and a second oxide film is formed by a low pressure CVD method on an SOI substrate having 1 Ωcm, an oxide film pressure of 0.4 μm, and a first single crystal silicon layer thickness of 1.0 μm. Here, the nitride film is formed at a temperature of 200 ° C., a pressure of 0.2 Torr, an RF frequency of 13.56 MHz, and SiH.
₄ flow rate 5 sccm, NH ₃ flow rate 300 sccm, deposition rate 30 nm / min, thickness 0.3 μm
A nitride film was deposited. The temperature of the oxide film is 800
° C, SiH ₄ flow rate 5 sccm, N ₂ O flow rate 250 sccc
m, SiH ₄ partial pressure 0.3 Torr, deposition rate 35 nm /
This was carried out under the condition of min to form an oxide film having a thickness of 0.5 μm. Next, the oxide film and the nitride film are patterned by RIE. After exposing a part of the first single crystal silicon layer, an amorphous silicon layer is stacked by a low pressure CVD method. Here, temperature 570 ° C., pressure 18 Torr, Si
_{A 2} H ₆ flow rate of 10 sccm, a H ₂ flow rate of 3 slm, and a deposition rate of 30 nm / min were performed to deposit an amorphous silicon layer having a thickness of 0.2 μm. Subsequently, the amorphous silicon layer is irradiated with a pulse beam of an argon laser having a diameter of 30 μm to melt the amorphous silicon layer from the exposed portion of the first single crystal silicon layer, and then recrystallized to be oxidized. A second single crystal silicon layer having a thickness of 0.2 μm is formed over the film. Further, an oxide film having a thickness of 1.0 μm is laminated by a low pressure CVD method, and after patterning by RIE, an aluminum electrode is formed by a sputtering method. The oxide film is formed at 800 ° C., the Si ₂ H ₆ flow rate is 3 sccm, and the N ₂ O flow rate is 3
The conditions were 00 scmm, Si ₂ H ₆ partial pressure of 0.15 Torr, and deposition rate of 45 nm / min. Then, as a passivation film, an NSG film (Non-Si
After stacking the licate glass), an opening is formed by RIE to expose a part of the first single crystal silicon layer. Finally, isotropic etching with a hydrofluoric nitric acid-based solution is performed from the opening to remove a part of the first single crystal silicon layer, and a thickness of 3.5 μm is formed on a portion where the second single crystal silicon layer is formed.
a diaphragm of m. Here HF: HN
A mixture of O ₃ : CH ₃ COOH = 1: 14: 20 was used.

The piezoresistive semiconductor pressure sensor shown in the fifth embodiment is a semiconductor pressure sensor which is smaller in size and higher in integration than conventional ones. In addition, since the element and the diaphragm are formed from the same main surface side on the semiconductor substrate by manufacturing in the process shown in the fifth embodiment, the semiconductor pressure sensor described above can be manufactured and the semiconductor pressure sensor can be manufactured. It is possible to improve the manufacturing yield of the sensor. Further, in this embodiment, by using the electronic circuit having the SOI structure, it is possible to realize high speed, high integration, downsizing, reliability improvement of the electronic circuit. Further, since the first oxide film is used as the etching stopper, it is possible to prevent the mechanical structure of the entire sensor from becoming unstable due to the thickness of the silicon substrate at the bottom of the cavity becoming too thin during the etching of the silicon substrate. .

In this embodiment, the semiconductor element is formed on the second single crystal silicon layer 4 and the electronic circuit is formed on the first single crystal silicon layer 16. However, as shown in FIG. It is also possible to form a semiconductor element and an electronic circuit on the single crystal silicon layer 4. FIG. 16 is another example of a cross-sectional view of the semiconductor device shown in this embodiment. Here, 1 is a silicon substrate, 2 is a second oxide film, 3 is a nitride film, 15 is a first oxide film, 16 is a first single crystal silicon layer, 41 is a semiconductor element, 42 is an electronic circuit, and 43. Is an opening, and 44 is a diaphragm. In FIG. 16, the first oxide film 15 is formed on the silicon substrate 1, and the first single crystal silicon layer 16 is formed on the first oxide film 15. A second oxide film 2 and a nitride film 3 are formed on the first single crystal silicon layer 16, and a semiconductor element 41 and an electronic circuit 42 are formed on the second oxide film 2. The first single crystal silicon layer 16 is etched through the opening 43 provided on the second oxide film 2 and the nitride film 3 to form a diaphragm 44.
However, the cavity is not provided immediately below the electronic circuit 42, but is provided only below the semiconductor element 41. In addition, the electronic circuit 4 is formed on the first single crystal silicon layer 16 in FIG.
It is also possible to provide 2. The process shown in FIG. 16 is the same as the process shown in FIG. 15 except for the position where the electronic circuit is formed. Therefore, it is possible to use the same conditions and methods applicable to the process shown in FIG.

For the other details of this embodiment, it is possible to apply the same conditions and methods as those shown in the first and fourth embodiments.

(Embodiment 6) FIG. 17 is a sectional view showing a sixth embodiment of a semiconductor device according to the present invention. Here, 14 is an SOI substrate, a first single crystal silicon layer 16 is formed on the first oxide film 15, and a second oxide film 2 and a second oxide film 2 are formed on the first single crystal silicon layer 16. There is a region where the nitride film 3 is laminated. A second single crystal silicon layer 4 is formed on the second oxide film 2 and the nitride film 3, and an aluminum electrode 5 is connected to the second single crystal silicon layer 4. The second single crystal silicon layer 4 and the aluminum electrode 5 are insulated by the insulating film 6 except for the connection portion. An opening 7 is formed on the second oxide film 2 and the nitride film 3, and the second oxide film 2 and the nitride film 3 are directly under the portion where the second single crystal silicon layer 4 is formed. A cavity is provided in the diaphragm, and this portion becomes the diaphragm 8. Electronic circuits 9 and 10 are formed in the first single crystal silicon layer 16, and the electronic circuits 9 and 10 are electrically connected to the second single crystal silicon layer 4 through the aluminum electrode 5. The electronic circuits 9 and 10 are separated from each other by the diaphragm 8 and the third oxide film 17. Here, only the pMOS transistor 9 and the nMOS transistor 10 are shown as electronic circuits. Diaphragm 8 as a whole
Then, the electronic circuits 9 and 10 are covered with the passivation film 11.

The semiconductor device shown in FIG. 17 is a piezoresistive semiconductor acceleration sensor, and its operation is the same as that of the semiconductor acceleration sensor shown in the fourth embodiment. The semiconductor device can also be used as a piezoresistive semiconductor pressure sensor.

FIG. 18 is a process chart showing the method for manufacturing the semiconductor device shown in this embodiment. Reference numerals 2 to 16 in FIG.
17 is a thick oxide film, 18 is a polycrystalline silicon layer, and 19 is a third oxide film. The process according to FIG. 18 is as follows. (A) A first layer is formed on the first oxide film 15.
In the SOI substrate 14 on which the single crystal silicon layer 16 is formed, (b) a thick oxide film 17 is formed on the first single crystal silicon layer 16 to separate the region of the first single crystal silicon layer 16. (C) Planarization is performed to form a third oxide film 19 leaving only the lower part of the thick oxide film 17. (D) A second oxide film 2 and a nitride film 3 are formed on the first single crystal silicon layer 16. (E) After patterning, a polycrystalline silicon layer 18 is formed on the first single crystal silicon layer 16 and the nitride film 3. (F) Polycrystalline silicon layer 18
The polycrystalline silicon layer 18 is recrystallized from the exposed portion of the first single crystal silicon layer 16 by irradiating it with an argon laser to form the second single crystal silicon layer 4 on the nitride film 3. (G) The semiconductor element 4 is formed on the second single crystal silicon layer 4.
1, an electronic circuit 42 and an opening 43 are formed on the first single crystal silicon layer 16. (H) The second oxide film 2 having the semiconductor element 41 formed by etching through the opening 43
Then, a part of the first single crystal silicon layer 16 under the nitride film 3 is removed to form the diaphragm 44. Through the above steps, the semiconductor device shown in FIG. 17 can be obtained.

An example in which the above semiconductor device is specifically manufactured by using the process shown in FIG. 18 is shown below. Plane orientation <1
00>, diameter 125 mm, thickness 625 μm, specific resistance 10
A thick oxide film with a thickness of 2.0 μm is formed by the LOCOS thermal oxidation method on an SOI substrate with an Ωcm, an oxide film thickness of 0.8 μm, and a first single crystal silicon layer thickness of 1.0 μm. 1 single crystal silicon layer is separated. Subsequently, SOG (Spin On Glass) is applied to the surface, and then reflow is performed to flatten the surface. Further, the oxide film is etched by RIE, and the etching is finished when the silicon / oxide film interface is exposed. This forms a third oxide film having a thickness of 1.0 μm, leaving only the lower part of the thick oxide film. After that, an oxide film and a nitride film are formed by the low pressure CVD method. Here, the oxide film is formed at a temperature of 800 ° C. and Si
H ₄ flow rate 5 sccm, N ₂ O flow rate 250 sccm, Si
An H ₄ partial pressure of 0.3 Torr and a deposition rate of 35 nm / min were performed to deposit an oxide film having a thickness of 0.5 μm.
The temperature of the nitride film is 800 ° C. and the SiH ₄ flow rate is 5 sc.
cm, NH ₃ flow rate 300 sccm, SiH ₄ partial pressure 0.3
A nitride film having a thickness of 0.3 μm was deposited under conditions of Torr and a deposition rate of 70 nm / min.

Next, patterning of the oxide film and the nitride film is performed by RIE. After exposing a part of the first single crystal silicon layer, a single crystal silicon layer is stacked by a low pressure CVD method. Here, the temperature is 656 ° C and the pressure is 0.25To.
In a mixed gas of rr, SiH ₄ and H ₂ , a single-crystal silicon layer having a thickness of 0.2 μm was laminated under the conditions of SiH ₄ partial pressure of 0.15 Torr and deposition rate of 300 nm / min. Then, the polycrystal silicon layer is irradiated with a pulse beam of an excimer laser having a diameter of 50 μm to recrystallize the polycrystal silicon layer from the exposed portion of the first single crystal silicon layer, so that the thickness of the oxide film on the oxide film becomes 0. A second single crystal silicon layer having a thickness of 0.2 μm is formed. Further, an oxide film having a thickness of 1.0 μm is stacked by the plasma CVD method, patterned by RIE, and then an aluminum electrode is formed by the sputtering method. The oxide film is formed at a temperature of 800 ° C., a Si ₂ H ₆ flow rate of 3 sccm, a N ₂ O flow rate of 300 sccm, and Si ₂ H ₆
The partial pressure was 0.15 Torr and the deposition rate was 45 nm / min. Then, as a passivation film, a 1.0 μm-thick BPSG film (Borono-Phospho SilicateGla) is formed.
After ss) is stacked, an opening is formed by RIE to expose a part of the first single crystal silicon layer. Finally, isotropic etching is performed with a nitric acid-based solution from the opening 43 to remove a part of the first single crystal silicon layer, and a thickness of 3. is formed on a portion where the second single crystal silicon layer is formed. A 0 μm diaphragm is formed. Here HF: HNO ₃ : CH
A mixed solution of ₃ COOH = 1: 12: 17 was used.

The piezo-resistive semiconductor acceleration sensor shown in the sixth embodiment is a semiconductor acceleration sensor which is smaller in size and higher in integration than ever before. In addition, since the element and the diaphragm are formed from the same main surface side on the semiconductor substrate by manufacturing in the process shown in the sixth embodiment, the semiconductor acceleration sensor described above can be manufactured and the semiconductor acceleration sensor can be manufactured. It is possible to improve the manufacturing yield of the sensor. Further, in this embodiment, by using the electronic circuit having the SOI structure, it is possible to realize high speed, high integration, downsizing, reliability improvement of the electronic circuit. Further, since the first oxide film and the third oxide film are used as the etching stopper, it is possible to prevent the thickness of the silicon substrate at the bottom of the cavity from becoming too thin during the etching of the silicon substrate, and to prevent the sidewall of the first single crystal silicon layer from becoming too thin. It is possible to protect the part (side wall part of the electronic circuit) and stabilize the mechanical structure of the entire sensor.

As the flattening method, SOG is used in this embodiment.
Although the method of reflowing and flattening is used, other than this, CMP (Chemical Mechanical Polishing) or the like can be used.

In this embodiment, the semiconductor element is formed on the second single crystal silicon layer and the electronic circuit is formed on the first single crystal silicon layer. However, as shown in FIG. 19, a nitride film and an oxide film are formed. It is also possible to form a semiconductor element and an electronic circuit on the upper second single crystal silicon layer. FIG. 19 is another example of a cross-sectional view of the semiconductor device shown in this embodiment. here,
1 is a silicon substrate, 2 is a second oxide film, 3 is a nitride film, 1
5 is a first oxide film, 16 is a first single crystal silicon layer, 1
7 is a third oxide film, 41 is a semiconductor element, 42 is an electronic circuit, 43 is an opening, and 44 is a diaphragm. FIG.
In, the first oxide film 15 is formed on the silicon substrate 1, and the first single crystal silicon layer 16 and the third oxide film 17 are formed on the first oxide film 15. A second oxide film 2 and a nitride film 3 are formed on the first single crystal silicon layer 16 and the third oxide film 17, and a semiconductor element 41 and an electronic circuit 42 are formed on the second oxide film 2. Has been formed. The diaphragm 44 is formed by etching the first single-crystal silicon layer 16 through the opening 43 provided on the second oxide film 2 and the nitride film 3. However, the diaphragm 44 is formed immediately below the electronic circuit 42. Since the oxide film 17 is formed, the cavity is provided only directly below the semiconductor element 41. In addition, the first single crystal silicon layer 16 in FIG.
It is also possible to provide the electronic circuit 42 in. Since the process shown in FIG. 19 is the same process as that of FIG. 18 except for the position where the electronic circuit is formed, it is possible to use the same conditions and methods applicable to the process shown in FIG.

For other details of this embodiment, the same conditions and methods as those shown in the first, fourth and fifth embodiments can be applied.

(Embodiment 7) FIG. 20 is a process drawing showing a seventh embodiment of the method for manufacturing a semiconductor device according to the present invention. Here, 35 is a first silicon substrate, 36 is a high concentration impurity layer, 37 is a second silicon substrate, 38 is an insulating layer, 39 is a single crystal silicon layer, 40 is an SOI substrate, 41 is a semiconductor element, and 42 is an electron. A circuit, 43 is an opening, and 44 is a diaphragm. The process according to FIG. 20 is as follows.
(A) High concentration impurity layer 36 on the first silicon substrate 35
To form (B) The first silicon substrate 35 and the insulating layer 38 formed on the second silicon substrate 37 are bonded together. (C) After heat treatment is performed to completely bond the first silicon substrate 35 and the insulating layer 38 to each other, the second silicon substrate 37 is thinned to form the single crystal silicon layer 39 on the insulating layer 38.
The SOI substrate 40 having the above is formed. (D) The single crystal silicon layer 39 is patterned to form the semiconductor element 41 and the electronic circuit 42, and the opening 43 is formed on the insulating layer 38.
To form (E) The high-concentration impurity layer 36 is removed by etching through the opening 43 to form the diaphragm 44.

A specific example in which the above semiconductor device is specifically manufactured by using the process shown in FIG. 20 is shown below. A p + -type high-concentration impurity layer is formed by ion implantation on a first p-type silicon wafer having a plane orientation of <100>, a diameter of 125 mm, a thickness of 625 μm, and a specific resistance of 0.5 Ωcm. Here, boron ions are implanted under the conditions of a dose amount of 6 × 10 ¹² cm ⁻² and an accelerating voltage of 40 keV, and a p of 0.5 μm thickness is obtained.
^{A +} type high concentration impurity was formed. Next, the surface of the silicon wafer on which the p ⁺ -type high-concentration impurity layer was formed and the plane orientation <10
0>, diameter 125 mm, thickness 625 μm, specific resistance 20 Ω
A 400-nm-thick oxide film formed by thermal oxidation on the second silicon wafer having a thickness of 400 cm is bonded in nitrogen. Then, the bonded silicon wafers are heat-treated in a nitrogen / oxygen mixed gas at a temperature of 1150 ° C. for 5 minutes to completely bond the two. Subsequently, the second silicon wafer is ground to a thickness of 5 μm, and then plasma etching is performed to stack the second silicon wafer to a thickness of 1.0 μm. As a result, the SOI in which the single crystal silicon layer with a thickness of 1.0 μm is formed on the oxide film with a thickness of 400 nm is formed.
A substrate is obtained. After that, a semiconductor element and an electronic circuit are formed on the single crystal silicon layer by using a normal LSI manufacturing process. At this time, the semiconductor element is located on the p ⁺ -type high-concentration impurity layer with the oxide film interposed therebetween. Further, an opening is formed on the oxide film to expose a part of the p ⁺ -type high concentration impurity layer. Finally, isotropic etching is performed from the opening with a hydrofluoric nitric acid-based solution to remove the p ⁺ -type high-concentration impurity layer and form a diaphragm in the portion where the semiconductor element is formed. Here, HF: HNO ₃ : CH ₃ CO
A mixed solution of OH = 1: 3: 8 was used.

By using the process shown in the seventh embodiment,
The silicon substrate can be accurately etched. Further, since the electronic circuit can have the SOI structure, it is possible to realize high speed, high integration, downsizing, reliability improvement of the electronic circuit.

The above-described SOI substrate is manufactured by the direct bonding method, and the thinning of the second silicon substrate is performed here by grinding and polishing, but this step can also be performed by etching. For example, after a single crystal silicon layer is epitaxially grown on a p-type silicon wafer, an insulating layer is formed on the single crystal silicon layer, the insulating layer and the first silicon wafer are bonded together, and the p-type silicon wafer is etched. And a single crystal silicon layer can be formed over the insulating layer. in this case,
It is possible to use a KOH aqueous solution or the like as the etching solution. In addition, after a single crystal silicon layer is epitaxially grown on the etch stop layer formed on the silicon wafer, an insulating layer is formed on the single crystal silicon layer and the insulating layer and the first silicon wafer are attached to each other. In addition, the silicon wafer and the etch stop layer can be removed by etching to form a single crystal silicon layer over the insulating layer. In this case, as the etch stop layer, a high-concentration p-type silicon layer formed by boron ion implantation or epitaxial growth, a silicon germanium epitaxial layer, a porous silicon layer, or the like can be used. For this method, the same method and conditions shown in the sixth embodiment can be applied.

For the other details of this embodiment, the same conditions and methods as those shown in the first and fourth to sixth embodiments can be applied.

(Embodiment 8) FIG. 21 is a process drawing showing an eighth embodiment of the method for manufacturing a semiconductor device according to the present invention. Here, reference numerals 35 to 44 are the same as those in FIG. 20, and 45 is a porous silicon layer. The process according to FIG. 21 is as follows. (A) A porous silicon layer 45 is formed on the first p-type silicon substrate 35. (B) Insulating layer 3 formed on the first p-type silicon substrate 35 and the second silicon substrate 37
Attach 8 and. (C) After heat treatment is performed to completely bond the first silicon substrate 35 and the insulating layer 38,
The second silicon substrate 37 is thinned to form an SOI substrate 40 in which the single crystal silicon layer 39 is formed over the insulating layer 38. (D) Semiconductor element 41 on single crystal silicon layer 39
And the electronic circuit 42 and the opening 43 are formed. (E)
The porous silicon layer 4 is etched through the opening 43.
5 is removed and the diaphragm 44 is formed.

An example in which the above semiconductor device is specifically manufactured by using the process shown in FIG. 21 is shown below. Plane orientation <1
00>, diameter 125 mm, thickness 625 μm, specific resistance 0.
A porous silicon layer is formed on the first p-type silicon wafer of 01 Ωcm by the anodization method. Here HF:
1.0 in a conversion solution of C ₂ H ₅ OH: H ₂ O = 1: 1: 1
Apply a direct current of A / cm ² for 14 minutes to obtain a thickness of 15 μm.
The porous silicon layer of was formed. Next, the surface of the silicon wafer 35 on which the porous silicon layer is formed and the plane orientation <1
00>, diameter 125 mm, thickness 625 μm, specific resistance 20
An oxide film having a thickness of 800 nm formed by thermal oxidation on the second silicon wafer of Ωcm is attached in argon. After that, the bonded silicon wafers are heat-treated in oxygen at a temperature of 1100 ° C. for 2 hours to completely bond the two. Then, after grinding the second silicon wafer to a thickness of 5 μm, plasma etching is performed to thin the second p-type silicon wafer to a thickness of 1.0 μm. As a result, a thickness of 1.
An SOI substrate 0 having a 0 μm single crystal silicon layer is obtained. After that, a semiconductor element and an electronic circuit are formed on the single crystal silicon layer by using a normal LSI manufacturing process. At this time, the semiconductor element is located on the porous silicon layer, sandwiching the oxide film. Further, an opening is formed on the oxide film to expose a part of the porous silicon layer. Finally, etching is performed from the opening to remove the porous silicon layer, and a diaphragm having a thickness of 3.0 μm is formed in the portion where the single crystal silicon layer is formed. Here, hydrofluoric acid / hydrogen peroxide mixture of HF: H ₂ O ₂ = 1: 5 was used.

By using the process shown in the eighth embodiment,
The silicon substrate can be accurately etched. Further, since the electronic circuit can have the SOI structure, it is possible to realize high speed, high integration, downsizing, reliability improvement of the electronic circuit.

The SOI substrate is manufactured by bonding and grinding and polishing, but it can also be manufactured by bonding and etching. For this method, the same method and conditions as those shown in the seventh embodiment can be applied. As the insulating layer, a nitride film, an oxide film covered with a nitride film, or the like can be used.
For selective etching of the porous silicon layer, in addition to hydrofluoric acid / hydrogen peroxide, a hydrofluoric / nitric acid-based solution (for example, HF: HNO ₃ : CH) is used.
₃ COOH = 1: 12: 17) can be used. In addition, the porous silicon layer can be selectively oxidized and removed with hydrofluoric acid or buffered hydrofluoric acid.

For the other details of this embodiment, it is possible to apply the same conditions and methods as those shown in the first and fourth to seventh embodiments.

(Embodiment 9) FIG. 22 is a process drawing showing a ninth embodiment of the method of manufacturing a semiconductor device according to the present invention. Here, reference numerals 35 to 44 are the same as those in FIG. 20, and 46 is a trench that becomes a cavity. The process according to FIG. 22 is as follows. (A) The semiconductor element 41 and the electronic circuit 42 are formed on the second silicon substrate 37.
(B) After the insulating layer 38 is formed on the semiconductor element 41 and the electronic circuit 42, the surface is flattened. (C) A trench 46 is formed on the first silicon substrate 35. (D) The insulating layer 38 and the first silicon substrate 35 are bonded together.
At this time, the trench 46 is arranged under the insulating layer in the portion where the semiconductor element 41 is formed. (E) Heat treatment is performed to completely bond the insulating layer 38 and the first silicon substrate 35, and then the second silicon substrate 37 is thinned to form the insulating layer 3
The semiconductor element 41 and the electronic circuit 42 are formed on the semiconductor chip 8, and the diaphragm 44 is formed on the trench 46.

An example in which the above semiconductor device is specifically manufactured by using the process shown in FIG. 22 is shown below. Plane orientation <1
00>, diameter 125 mm, thickness 625 μm, specific resistance 30
A semiconductor device and an electronic circuit are formed on the second silicon wafer of Ωcm by using a normal LSI manufacturing process.

Next, after forming an insulating layer on the semiconductor element and the electronic circuit, the surface is flattened. Here, after forming an oxide film by the atmospheric pressure CVD method, reflow is performed to flatten the surface, and further by the plasma CVD method,
A nitride film and an oxide film were formed.

The formation of an oxide film by the atmospheric pressure CVD method is performed at a temperature of 2
90 ° C, TEOS flow rate 3 slm, O ₂/ O_ThreeFlow rate 7.5
slm, O_ThreeConcentration 4.6%, N₂Flow rate 18 slm, deposition
It was performed under the condition of a speed of 350 nm / min.

The nitride film is formed at a temperature of 200 ° C., a pressure of 0.2 Torr, an RF frequency of 13.56 MHz, and SiH.
₄ flow rate 5 sccm, NH ₃ flow rate 300 sccm, deposition rate 30 nm / min, thickness 0.3 μm
A nitride film was deposited.

The oxide film is formed by the plasma CVD method at a temperature of 290 ° C., a pressure of 0.2 Torr, and a plasma discharge of RF frequency 13.56 MHz is performed in a SiH ₄ / N ₂ O mixed gas to form an oxide film having a thickness of 0.3 μm. The film was deposited.

As a result, an insulating layer having a thickness of 0.8 μm was formed on the semiconductor element and the electronic circuit.

After this, the plane orientation <100> and the diameter 125 m.
A trench 46 having a depth of 1.0 μm is formed by RIE on a first silicon wafer having a thickness of m, a thickness of 625 μm, and a specific resistance of 20 Ωcm.

Subsequently, the insulating layer formed on the second silicon wafer and the first silicon wafer are bonded together in a nitrogen / argon mixed gas. At this time, the semiconductor element is located on the trench with the insulating layer in between.

After that, the bonded silicon wafers are heat-treated in oxygen at a temperature of 1180 ° C. for 5 minutes to completely bond them. Further, the second silicon wafer is ground and polished. At this time, the semiconductor element and the electronic circuit are left using the portion of the insulating layer that separates the semiconductor element and the electronic circuit as a polishing stopper. As a result, an SOI substrate in which a single crystal silicon layer having a thickness of 1.0 μm is formed on an oxide film having a thickness of 800 nm is obtained.

Thereafter, a semiconductor element and an electronic circuit are formed on the single crystal silicon layer by using a normal LSI manufacturing process. At this time, the semiconductor element is located on the porous silicon layer, sandwiching the oxide film. Further, an opening is formed on the oxide film to expose a part of the porous silicon layer. Finally, isotropic etching is performed from the opening with a hydrofluoric nitric acid-based solution to remove the porous silicon layer and form a diaphragm having a thickness of 3.0 μm in the portion where the single crystal silicon layer is formed. Here, hydrofluoric acid / hydrogen peroxide mixture of HF: H ₂ O ₂ = 1: 5 was used.

By using the steps shown in the ninth embodiment,
Since it is not necessary to provide an opening on the insulating layer, the sensor unit and the entire sensor can be downsized, and the layout of the sensor unit and the entire sensor can be designed more freely. Further, since the electronic circuit can have the SOI structure, it is possible to realize high speed, high integration, downsizing, reliability improvement of the electronic circuit.

As a flattening method, as shown in the sixth embodiment, SOG reflow, CMP, or the like can be used.

For the other details of this embodiment, the same conditions and methods as those shown in the first and fourth to eighth embodiments can be applied.

[0079]

As described above, the semiconductor element formed on the insulating layer formed on the semiconductor substrate and the electronic circuit formed on the semiconductor substrate or the insulating layer are electrically connected to each other. In the semiconductor substrate, etching is performed from the surface on which the insulating layer is formed, and a cavity is provided below the insulating layer including the portion where the semiconductor element is formed, so that the semiconductor is smaller than the conventional one and has a higher degree of integration. It becomes possible to provide a device. With this semiconductor device, a sensor with improved sensitivity can be obtained as a pressure sensor or an acceleration sensor.

Further, since the element and the diaphragm can be formed from the same main surface side on the semiconductor substrate, the processing step on the back surface side can be eliminated in the manufacturing process, and the semiconductor device having the above effects can be eliminated. Can be manufactured, and the manufacturing yield of semiconductor devices can be improved. These are the further miniaturization and higher performance of semiconductor devices,
There is an effect that the price can be reduced.

[Brief description of drawings]

FIG. 1 is a sectional view showing a first embodiment of a semiconductor device according to the present invention.

FIG. 2 is a plan view showing a first embodiment of the semiconductor device according to the present invention.

FIG. 3 is a process chart showing the manufacturing method of the semiconductor device according to the first embodiment of the invention.

FIG. 4 is another example of process chart showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 5 is another example of a plan view showing the first embodiment of the semiconductor device according to the present invention.

FIG. 6 is another example of a plan view showing the first embodiment of the semiconductor device according to the present invention.

FIG. 7 is another example of a plan view showing the first embodiment of the semiconductor device according to the present invention.

FIG. 8 is a plan view showing a second embodiment of the semiconductor device according to the present invention.

FIG. 9 is another example of a plan view showing a second embodiment of the semiconductor device according to the present invention.

FIG. 10 is a plan view showing a third embodiment of the semiconductor device according to the present invention.

FIG. 11 is another example of a plan view showing a third embodiment of the semiconductor device according to the present invention.

FIG. 12 is a sectional view showing a fourth embodiment of the semiconductor device according to the present invention.

FIG. 13 is a process drawing showing the manufacturing method of the semiconductor device shown in the fourth embodiment of the present invention.

FIG. 14 is a sectional view showing a fifth embodiment of the semiconductor device according to the present invention.

FIG. 15 is a process drawing showing the manufacturing method of the semiconductor device shown in the fifth embodiment of the present invention.

FIG. 16 is another example of a sectional view showing a fifth embodiment of the semiconductor device according to the present invention.

FIG. 17 is a sectional view showing a sixth embodiment of the semiconductor device according to the present invention.

FIG. 18 is a process drawing showing the manufacturing method of the semiconductor device shown in the sixth embodiment of the present invention.

FIG. 19 is another example of a sectional view showing a sixth embodiment of the semiconductor device according to the present invention.

FIG. 20 is a process drawing showing a seventh embodiment of the method of manufacturing a semiconductor device according to the present invention.

FIG. 21 is a process drawing showing the eighth embodiment of the method of manufacturing a semiconductor device according to the present invention.

FIG. 22 is a process drawing showing the ninth embodiment of the method of manufacturing a semiconductor device according to the present invention.

FIG. 23 is a cross-sectional view showing the structure of a general IC atmospheric pressure sensor.

FIG. 24 is a cross-sectional view showing the structure of a general IC atmospheric pressure sensor.

[Explanation of symbols]

 1 Silicon Substrate 2 (Second) Silicon Oxide Film 3 Silicon Nitride Film 4 (Second) Single Crystal Silicon Layer 5 Aluminum Electrode 6 Insulating Film 7 Opening 8 Diaphragm 9 Electronic Circuit (pMOS Transistor) 10 Electronic Circuit (nMOS Transistor) ) 11 passivation film 12 amorphous silicon layer 13 contact part 14 SOI substrate 15 first silicon oxide film 16 first single crystal silicon layer 17 third silicon oxide film 18 polycrystalline silicon layer 20 p-type silicon substrate 21 n + Type buried layer 22 n type epitaxial layer 23 p + type element isolation region 24 p type diffusion layer 25 base region 26 collector region 27 emitter region 28 aluminum electrode 29 silicon oxide film 30 silicon nitride film 31 diaphragm 32 silicon substrate 33 sensor part 34 signal processing 35 first (p-type) silicon substrate 36 high concentration impurity layer 37 and the second silicon substrate 38 an insulating layer 39 single crystal silicon layer 40 SOI substrate 41 semiconductor device 42 electronic circuit 43 opening 44 a diaphragm 45 porous silicon layer 46 a trench

Claims (12)

[Claims] 1. A semiconductor device in which a semiconductor element formed on an insulating layer formed on a semiconductor substrate and an electronic circuit formed on the semiconductor substrate or on the insulating layer are electrically connected to each other, A semiconductor device characterized in that the semiconductor substrate is etched from a surface on which the insulating layer is formed to provide a cavity below the insulating layer including a portion where the semiconductor element is formed. 2. A step of forming an insulating layer on a semiconductor substrate, a step of forming a semiconductor element on the insulating layer, a step of forming an electronic circuit on the semiconductor substrate or on the insulating layer, and the semiconductor. The step of electrically connecting the element and the electronic circuit, and the semiconductor under the insulating layer including a portion where the semiconductor element is formed by performing etching from the surface of the semiconductor substrate on which the insulating layer is formed Removing a part of the substrate to form a cavity under the insulating layer including a portion where the semiconductor element is formed. 3. A step of forming a high-concentration impurity layer on a semiconductor substrate, a step of forming an insulating layer on the semiconductor substrate and the high-concentration impurity layer, and the step of forming an insulating layer on the high-concentration impurity layer. A step of forming a semiconductor element on an insulating layer; a step of forming an electronic circuit on the semiconductor substrate or the insulating layer; a step of electrically connecting the electronic circuit and the semiconductor element; Etching is performed from above and on the surface of the high-concentration impurity layer on which the insulating layer is formed to remove the high-concentration impurity layer, and a cavity portion is formed below the insulating layer including a portion where the semiconductor element is formed. And a step of forming a semiconductor device. 4. A step of forming a porous semiconductor layer on a semiconductor substrate, a step of forming an insulating layer on the semiconductor substrate and on the porous semiconductor layer, and the step of forming the insulating layer on the porous semiconductor layer. A step of forming a semiconductor element on an insulating layer; a step of forming an electronic circuit on the semiconductor substrate or the insulating layer; a step of electrically connecting the electronic circuit and the semiconductor element; Etching is performed from above and on the surface of the porous semiconductor layer on which the insulating layer is formed to remove the porous semiconductor layer, and a cavity is formed below the insulating layer including a portion where the semiconductor element is formed. And a step of forming a semiconductor device. 5. The method of manufacturing a semiconductor device according to claim 2, wherein the etching is performed through an opening formed on the insulating layer. 6. A step of forming a semiconductor element and an electronic circuit on a first substrate, a step of forming an insulating layer on the semiconductor element and the electronic circuit, and forming a cavity on a second semiconductor substrate. And a step of bonding the insulating layer and the second semiconductor substrate to each other to form a cavity below the insulating layer including a portion where the semiconductor element is formed. Device manufacturing method. 7. The method of manufacturing a semiconductor device according to claim 2, wherein regions having different thicknesses are formed on the semiconductor substrate by providing the hollow portion. . 8. An insulating layer is formed on a semiconductor substrate, a semiconductor element is formed on the insulating layer, an electronic circuit is formed on the semiconductor substrate or on the insulating layer, and the semiconductor element and the electronic circuit are formed. In a semiconductor device electrically connected to, by performing etching from the surface of the semiconductor substrate on which the insulating layer is formed, a part of the semiconductor substrate under the insulating layer including a portion where the semiconductor element is formed A semiconductor device, characterized in that a cavity is formed below the insulating layer including the portion where the semiconductor element is formed. 9. A high-concentration impurity layer is formed on a semiconductor substrate, an insulating layer is formed on the semiconductor substrate and the high-concentration impurity layer, and the insulating layer is formed on the high-concentration impurity layer. In a semiconductor device in which a semiconductor element is formed, an electronic circuit is formed on the semiconductor substrate or on the insulating layer, and the electronic circuit and the semiconductor element are electrically connected, the semiconductor substrate and the high-concentration impurity layer Etching is performed from the upper surface on which the insulating layer is formed to remove the high-concentration impurity layer, and a cavity portion formed below the insulating layer including a portion where the semiconductor element is formed is provided. Characteristic semiconductor device. 10. A porous semiconductor layer formed on a semiconductor substrate, an insulating layer formed on the semiconductor substrate and the porous semiconductor layer, and an insulating layer formed on the porous semiconductor layer. A semiconductor device comprising the formed semiconductor element and an electronic circuit formed on the semiconductor substrate or on the insulating layer, wherein the electronic circuit and the semiconductor element are electrically connected to each other, on the semiconductor substrate and the porous material. The surface of the semiconductor layer on which the insulating layer is formed is etched to remove the porous semiconductor layer, and a cavity portion is formed below the insulating layer including a portion where the semiconductor element is formed. A semiconductor device characterized by the above. 11. A first substrate having a semiconductor element and an electronic circuit formed on a substrate, and an insulating layer formed on the semiconductor element and the electronic circuit, and a cavity formed on the semiconductor substrate. A second semiconductor substrate, wherein the insulating layer and the second semiconductor substrate are bonded together, and the cavity is formed under the insulating layer including a portion where the semiconductor element is formed. A semiconductor device characterized by being provided. 12. The etching according to claim 1, wherein the etching is performed through an opening formed on the insulating layer.
11. The semiconductor device according to claim 1.