JPH0982691A - Plasma etching method and system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make the etched substrates uniform in dimensional conversion difference by a method wherein silicon-containing conductive material layer patterns are controlled in dimensional conversion difference by a retention time of etching gas in an etching chamber. SOLUTION: A computer 19 is equipped with a memory means, and correlational data such as an opening area rate of an etched layer, a tapering angle and a dimensional conversion difference of a resist pattern, and a retention time and an exhaust rate of etching gas are stored in the memory means. A control means provided in the computer 19 is made to control a conductance valve 17 in opening from the correlational data and the inputted values of the opening area rate of an etched substrate 11 and the tapering angle data of a resist pattern so as to set a retention time of etching gas or an exhaust speed optimal. Therefore, when a dimensional conversion difference of a silicon- containing conductive material layer pattern is positive, a retention time of etching gas is set shorter than a case where a dimensional conversion difference of a silicon-containing conductive material layer pattern is negative.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma etching method and a plasma etching apparatus used for patterning a gate electrode, an internal wiring, etc. of a semiconductor device.
The present invention relates to a plasma etching method and a plasma etching apparatus for patterning a gate electrode, an internal wiring and the like having a fine width and excellent in a processed shape.

[0002]

2. Description of the Related Art Polycrystalline silicon has been widely used as a gate electrode / wiring material for semiconductor devices such as LSIs. In recent years, the design rule of semiconductor devices has been reduced from half micron to sub-quarter micron level, and as the demand for high-speed devices such as highly integrated memory devices has increased, it is about an order of magnitude lower than that of polycrystalline silicon. Refractory metal silicides, which have a resistance value, are being used. When the gate electrode / wiring is formed by using the refractory metal silicide, the refractory metal silicide layer may be used alone, but the interface characteristics with the gate insulating film, which easily affects the device characteristics and reliability, may be used. Considering this, it is often the case that an impurity-containing polycrystalline silicon layer, which has a proven track record in the past, is first formed on a gate insulating film, and a refractory metal silicide layer is stacked on the polycrystalline silicon layer. Such a laminated structure is collectively called polycide. Tungsten silicide as a refractory metal silicide (WSi _x) is common, referred to in particular tungsten polycide polycide having the WSi _x (W polycide).

In the process of plasma etching a refractory metal silicide layer or polycide layer to form a gate electrode / wiring, halogen-based gas other than F-based gas, such as Cl-based gas or Br-based gas, is adopted to achieve high selection. It is becoming more common to perform anisotropic processing of the ratio. When an F-based gas is used, it is necessary to form a thick side wall protective film of CF-based polymer or the like in order to prevent side etching due to highly reactive F ^* (F radicals), although it has an excellent etching rate. This is because the problems of dimensional conversion difference and particle contamination cannot be avoided, and the etching selectivity to the underlying gate oxide film is unfavorable. In particular, in the gate electrode / wiring processing of the design rule of sub-quarter μm, a plasma etching method and apparatus capable of achieving an ultrahigh selection ratio while maintaining anisotropy are required. On the other hand, in recent years, high-density plasma etching using a Cl-based gas has become mainstream, and in the case of polycrystalline silicon, a selection ratio exceeding 30 with respect to the underlying SiO ₂ can be achieved.

For plasma etching of the W polycide layer using a Cl-based gas, a Cl ₂ / O ₂ mixed gas is usually used. In this case, chlorides (WCl _x and SiCl _x ) of W and Si, which are constituent elements of W polycide, or oxychlorides (WOCl _x and SiOCl) are used as reaction products of etching by Cl ^* radicals and O ^* radicals. _x ) etc. are formed.

Of these reaction products, WOCl _x and SiCl _x, which have a relatively high vapor pressure, are vaporized and removed in a form assisted by ion injection, and etching proceeds, while WCl _{x, which} has a relatively low vapor pressure. _x and SiOCl _x are deposited on the side surface of the pattern where the number of incident ions is small during etching and serve as a side wall protective film to contribute to anisotropic processing. WOCl ₄ which is a typical reaction product of W
And the boiling points of WCl ₆ are CRC Handbook
f Chemistry and Physics 7
5th. Edition (1994, CRC Pres
According to s), the following values are reported. WOCl ₄ 227.5 ° C. WCl ₆ 346.7 ° C. Thus, WCl ₆ has a boiling point of 1 as compared with WOCl _4.
Since it is higher than 00 ℃, the temperature of the substrate to be etched is low,
Alternatively, when the amount of oxygen-based chemical species on the substrate to be etched is insufficient, a very thick sidewall protective film is formed. This tendency is the same when a halogen-based gas other than Cl-based gas is used. Therefore, in a wiring forming method of plasma etching a wiring layer containing a refractory metal with a mixed gas of a gas capable of generating a halogen-based chemical species other than a fluorine-based chemical species and a gas capable of generating an oxygen-based chemical species, It is an important etching parameter to control the production ratio of oxyhalide in the etching reaction product.

By the way, according to the semiconductor technology roadmap up to 2010 compiled by the American Semiconductor Industry Association (SIA), the dimensional conversion difference (CD Loss; Critical D) allowed for processing the gate electrode of the 0.13 μm generation
The image loss is 13 nm or less, that is, 10% or less. In the actual process, it is necessary that the sum of the variation of the resist pattern size and the size conversion difference at the time of etching satisfies this value. Therefore, controllability of 10 nm or less is required in each process. If the dimensional conversion difference is too large, the reliability and uniformity of the semiconductor device deteriorate, such as fluctuations in wiring resistance and deterioration in migration resistance. On the other hand, the thickness of the side wall protective film formed by depositing the refractory metal halide such as WCl _x is 5
nm to 50 nm, which is a level that cannot be ignored. Therefore, a dimensional conversion difference occurs due to the thickness of the sidewall protective film, which becomes a major obstacle in the manufacturing process of the highly integrated semiconductor device.

As described above, in the gate electrode etching using Cl-based gas, mainly SiCl _x , W
Since the deposition of the reaction product of Cl _x or these oxides is used as the side wall protection film, the gate electrode width is basically thickened by the thickness of these deposits.
That is, the dimension conversion difference takes a positive value and becomes the CD gain.

Therefore, for each different substrate to be etched,
Alternatively, how to evenly control the thickness of the sidewall protection film in one substrate to be etched is an important technical issue. However, according to the study by the present inventors, the amount of the reaction product attached to the side surface of the pattern is (1) the opening area ratio at which the layer to be etched is exposed from the etching mask, that is, (1) 1-Coverage of resist pattern) (2) It has been clarified that the side surface of the resist pattern greatly varies depending on the angle formed by the layer to be etched, that is, the taper angle of the etching mask.

First, the problem (1) will be described with reference to FIGS. 6 (a) and 6 (b). This figure shows a refractory metal polycide layer 5 composed of a polycrystalline silicon layer 3 and a refractory metal silicide layer 4 formed on a gate insulating film 2 on a semiconductor substrate 1.
Shows the state where plasma etching is performed using the etching mask 6 as a mask. Of these, FIG. 6A shows the vicinity of the line and space pattern, in which the area coverage of the etching mask 6 is high, and the opening area ratio at which the surface of the refractory metal polycide layer 5 which is the layer to be etched is exposed from the etching mask 6 is, for example, It is 20% or less. Further, FIG. 6B shows the vicinity of the isolated pattern, and the opening area ratio at which the layer to be etched is exposed is, for example, 70% or more.

6A and 6B, the black arrow indicates the reaction product 8 being removed from the substrate to be etched, and the broken arrow indicates that the reaction product 8 has been re-dissociated in the plasma. It shows that the re-dissociation product 9 is deposited on the substrate to be etched. Reference numeral 7 is a side wall protective film, which is formed by adhering a part of the reaction product 8 and the re-dissociation product 9 on the side surface of the pattern where the ion incidence is small. Particularly in a high-density plasma etching apparatus, since the amount of re-dissociation products 9 in plasma is large, the proportion of deposition of the re-dissociation products 9 is large.

As is apparent from FIG. 6 (a), when the opening area ratio at which the layer to be etched is exposed is small, the amount of reaction product 8 generated is small, and therefore the amount of re-dissociation product 9 deposited is small. The side wall protection film 7 is thin. Therefore, the pattern width of the layer to be etched is less likely to be widened due to the difference in dimension conversion, and in some cases, the side wall protective film 7 may be insufficiently deposited to cause side etching or notching. Further, when the exposed area ratio of the layer to be etched is large as shown in FIG. 6B, the reaction product 8 is generated in a large amount and the re-dissociation product 9 is deposited in a large amount, so that the sidewall protective film 7 is thick. It is formed. Therefore, the pattern width of the layer to be etched tends to be widened due to the dimensional conversion difference. Here, the dimensional conversion difference in gate electrode etching is an amount defined by the maximum width of the etching mask and the dimensional difference between the gate electrode and the gate insulating film interface after patterning, that is, the gate electrode width at the bottom surface of the gate electrode. is there.

Next, the problem of the taper angle of the etching mask of (2) will be described with reference to FIGS. 7 (a) and 7 (b).
The taper angle of the etching mask is defined as an angle θ formed by the inner surface of the etching mask and the layer to be etched. This figure shows only one resist pattern 7 portion of the same substrate to be etched as in FIG. In particular, FIG. 7A shows an inverse taper shape in which the angle θ formed by the side surface of the etching mask 6 and the surface of the high melting point metal polycide layer 5 as the layer to be etched is 90 ° or more. In this case, the side wall protective film 7 attached to the side surface of the etching mask 6 tends not to be removed by sputtering because the amount of ions incident on this portion is small, and tends to be deposited excessively thickly. Therefore, a positive dimensional conversion difference occurs in the gate electrode made of the refractory metal polycide layer 5, as shown in FIG. 7B. Etching mask 6
In the case of a forward taper shape in which the angle θ formed between the side surface of the metal polycide layer 5 and the surface of the refractory metal polycide layer 5 to be etched is less than 90 °, the reverse is true. In No. 7, since many ions are incident on this portion, it is immediately removed by sputtering and tends to be deposited extremely thinly or not at all. Therefore,
Side etching enters the gate electrode made of the refractory metal polycide layer 5, and a negative dimensional conversion difference occurs.

As described above, even if the plasma etching conditions are kept constant, there is a problem that the dimensional conversion difference varies depending on the exposed area ratio of the layer to be etched and the taper angle of the etching mask. This is a problem that cannot be avoided by the current plasma etching apparatus or plasma etching method, and is particularly inconvenient when serially processing different types of substrates to be etched.

[0014]

SUMMARY OF THE INVENTION An object of the present invention is to solve the problems associated with the conventional plasma etching method and plasma etching apparatus described above. That is, an object of the present invention is to perform dimension conversion regardless of the etching mask coverage, that is, the exposed area ratio of the layer to be etched or the taper angle of the etching mask, in the processing of a minute gate electrode to which the minimum design rule in the semiconductor manufacturing process is applied. It is an object of the present invention to provide a plasma etching method and a plasma etching apparatus capable of suppressing the difference within a permissible value of 10% or less and suppressing the variation in the dimensional conversion difference for each substrate to be etched.

[0015]

The wiring forming method of the present invention is proposed to solve the above problems.
That is, the invention of claim 1 etches a substrate to be etched having an etching mask formed on a conductive material layer containing silicon in an etching chamber with an etching gas containing a halogen-based gas, and
While depositing at least one of a reaction product of the conductive material containing silicon and a halogen-based gas and a re-dissociation product of the reaction product on a substrate to be etched, a conductive material layer containing silicon is formed. In the plasma etching method of patterning, the dimensional conversion difference of the conductive material layer pattern containing silicon is controlled by the residence time of the etching gas in the etching chamber. That is, when the dimension conversion difference of the conductive material layer pattern containing silicon is positive, the residence time of the etching gas should be controlled to be shorter than that when the dimension conversion difference of the conductive material layer pattern containing silicon is negative. Is characterized by.

According to a third aspect of the present invention, a substrate to be etched having an etching mask formed on a conductive material layer containing silicon is etched in an etching chamber with an etching gas containing a halogen-based gas and contains the silicon. Plasma etching for patterning a conductive material layer containing silicon while depositing at least one of a reaction product of a conductive material and a halogen-based gas and a re-dissociation product of the reaction product on a substrate to be etched. In the method, the residence time of the etching gas in the etching chamber is controlled by the area ratio of the conductive material layer containing silicon exposed from the etching mask. That is, when the area ratio of the silicon-containing conductive material layer exposed from the resist pattern is high, the etching in the etching chamber is smaller than when the silicon-containing conductive material layer is exposed from the etching mask. It is characterized in that the residence time of the gas is controlled to be short.

Further, according to a fifth aspect of the present invention, a substrate to be etched having an etching mask formed on a conductive material layer containing silicon is etched in an etching chamber with an etching gas containing a halogen-based gas, and the silicon is removed. Plasma for patterning a conductive material layer containing silicon while depositing at least one of a reaction product of a conductive material containing the halogen-based gas and a re-dissociation product of the reaction product on a substrate to be etched. In the etching method, the residence time of the etching gas in the etching chamber is controlled by the angle between the side surface of the etching mask and the conductive material layer containing silicon.
That is, when the side surface of the etching mask forms an angle of 90 ° or more (inverse taper shape) with the conductive material layer containing silicon (the inverse taper shape), the angle formed by the side surface of the etching mask with the conductive material layer containing silicon is less than 90 ° ( The retention time of the etching gas in the etching chamber is controlled to be shorter than that in the case of the forward taper shape.

Next, in the plasma etching apparatus of the present invention, that is, in the invention of claim 11, the substrate to be etched having the etching mask formed on the conductive material layer containing silicon is placed in the etching chamber with the etching gas containing the halogen-based gas. While etching at
The conductive material layer containing silicon is patterned while depositing a reaction product of the conductive material containing silicon and a halogen-based gas, and at least one of re-dissociation products of the reaction product on the substrate to be etched. In the plasma etching apparatus, the correlation between the area ratio of the conductive material layer containing silicon exposed from the etching mask and the dimensional conversion difference, and the angle between the side surface of the etching mask and the conductive material layer containing the silicon and the dimensional conversion difference,
Storage means for storing the correlation of at least one of the above, area ratio data in which a conductive material layer containing silicon is exposed from the etching mask, and angle data formed by side surfaces of the etching mask with the conductive material layer containing silicon. An input unit for inputting at least one of the above, area ratio data in which the conductive material layer containing silicon is exposed from the etching mask, and angle data of the side surface of the resist pattern with the conductive material layer containing silicon. Control means for controlling the residence time of the etching gas in the etching chamber based on at least one of the input values.

In a preferred embodiment of the plasma etching method and the plasma etching apparatus of the present invention,
The conductive material containing silicon is preferably any one of non-single crystal silicon, refractory metal silicide, and refractory metal polycide. In patterning a gate electrode material layer made of such a material, the plasma etching method and the plasma etching apparatus of the present invention can be preferably applied. Note that non-single-crystal silicon means both amorphous silicon and polycrystalline silicon.

In a preferred embodiment of the plasma etching method and the plasma etching apparatus of the present invention, it is desirable that the residence time of the etching gas be controlled by the exhaust speed of a vacuum pump that exhausts the inside of the etching chamber. In a more specific embodiment, the residence time of the etching gas is interposed between the etching chamber and a vacuum pump that exhausts the inside of the etching chamber,
It is desirable to control the degree of opening and closing of the conductance valve.

Further, in a preferred embodiment of the plasma etching method and the plasma etching apparatus of the present invention, the plasma density in the etching chamber is
It can be preferably applied when it is 1 × 10 ¹⁰ / cm ³ or more and less than 1 × 10 ¹⁴ / cm ³ . In such a high-density plasma atmosphere, the re-dissociation of the reaction product is predominant as compared with ordinary parallel plate etching using a plasma density of less than 1 × 10 ¹⁰ / cm ^3, so that the re-dissociation product This is because there is a large amount of deposition on the substrate to be etched. In the main operating vacuum range of the high-density plasma etching apparatus for ECR plasma, inductively coupled plasma, helicon wave plasma, etc., in the range of 10 ⁻¹ Pa, 1 × 1
The upper limit of substantial plasma density is 0 ¹³ / cm ³ .

The essence of the plasma etching method of the present invention is that the condition of the substrate to be etched is such that a positive dimension conversion difference is likely to occur, that is, the exposed area of the layer to be etched is 70%.
If the etching mask has the above-described shape or the etching mask has an inverse tapered shape, the retention time of the etching gas in the etching chamber is set to be short, that is, the exhaust speed is set to be large. By setting such conditions, the amount of the reaction product or the re-dissociation product of the reaction product dissociated in the plasma to be deposited on the substrate to be etched is reduced, that is, the thickness of the side wall protective film is reduced, and the positive dimension conversion difference is reduced. Can be reduced. On the contrary, when the etching target substrate condition in which a negative dimensional conversion difference is likely to occur, that is, when the exposed area of the etching target layer is 20% or less or the etching mask has a forward tapered shape, the etching gas in the etching chamber is The retention time is set to be long, that is, the exhaust speed is set to be small. By setting such conditions, the deposition amount of the reaction product or the re-dissociation product of the reaction product dissociated in plasma on the substrate to be etched is increased, that is, the thickness of the side wall protective film is increased, and the negative dimension conversion difference is increased. Can be reduced.

In practice, the correlation between the dimensional conversion difference and the residence time or exhaust speed of the etching gas is obtained for various substrates to be etched having different opening area ratios of the layers to be etched and taper angles of the etching mask, and this data is used as the data. Based on this, the residence time of the etching gas or the exhaust speed at which the dimensional conversion difference is 10% or less may be set.

The relationship between the opening area ratio of the layer to be etched, the residence time of the etching gas or the exhaust rate, and the dimensional conversion difference is shown in the graph of FIG. The shaded area in the figure is
This is a region where the dimensional conversion difference is within 10%. An area where a positive dimensional conversion difference occurs is indicated by +, and an area where a negative dimensional conversion difference occurs is indicated by a − symbol. If a positive dimensional conversion difference occurs beyond the shaded area, the residence time of the etching gas may be set shorter, and if a negative dimensional conversion difference occurs beyond this area, the etching gas may be reduced. It can be seen that it is sufficient to set a long residence time.

The graph of FIG. 5 shows the relationship between the taper angle of the etching mask, the residence time of the etching gas or the exhaust speed, and the dimensional conversion difference. The shaded portion in the figure is a region where the dimensional conversion difference is within 10%. If a positive dimensional conversion difference occurs beyond this region, the retention time of the etching gas may be set short, and if a negative dimensional conversion difference occurs beyond this region, the etching gas retention time It turns out that it is sufficient to set a long value. In FIGS. 4 and 5, the abscissa indicating the residence time of the etching gas or the exhaust speed is in arbitrary units.
Since these are tooling factors that vary depending on the etching apparatus, it is necessary to obtain such correlation data in advance for each etching apparatus.

In the plasma etching apparatus of the present invention, the correlation between the opening area ratio of the layer to be etched and the dimensional conversion difference and the correlation between the taper angle of the etching mask and the dimensional conversion difference are input in advance to a storage means such as a microcomputer. Keep it. Since the opening area ratio of the layer to be etched and the taper angle of the resist pattern of the substrate to be etched are constant for each lot, these known data are input for each lot.
Based on the stored data and the known data for each lot, the residence time of the etching gas can be controlled to an optimum value by the control means such as a microcomputer, and the dimensional conversion difference can be kept within 10%. .

The etching mask in this specification means a resist mask, a multilayer resist mask, SiO ₂
Etc. including an inorganic mask. A conductive material layer containing silicon which is being patterned is also included in the etching mask in a broad sense.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific embodiments of the present invention will be described below with reference to the accompanying drawings. In the drawings referred to in the description of the embodiments, constituent elements similar to those in the drawings referred to in the above description are designated by the same reference numerals.
First, a configuration example of a substrate bias application type ECR plasma etching apparatus which is a plasma etching apparatus adopted in the following embodiments will be described with reference to the schematic sectional view shown in FIG. The substrate 11 to be etched is placed and R
A microwave of 2.45 GHz generated by a magnetron (not shown) is passed through the microwave waveguide 13 and the microwave introduction window 14 to the etching chamber 15 in which the substrate stage 12 connected to the F power source is arranged. Introduce. A solenoid coil 16 is arranged on the side surface of the etching chamber 16 and is excited by this.
A high density ECR plasma is generated in the etching chamber 15 by the interaction between the 75 T magnetic field and the microwave. The exhaust system of the plasma etching apparatus is, for example, 50
It has a large capacity vacuum pump 18 of 001 / min and a conductance valve 17. Reference numeral 19 is a computer as a storage means and a control means. The storage means is input with the correlation data such as the opening area ratio of the layer to be etched, the taper angle of the resist pattern and the dimension conversion difference, the residence time of the etching gas, and the exhaust speed shown in FIGS. 4 and 5 described above. There is. Further, the control means controls the opening degree of the conductance valve 17 based on this correlation and the input value of the opening area ratio of the substrate 11 to be etched and the taper angle information of the resist pattern to control the retention time of the etching gas, that is, the exhaust speed. It can be set to the optimum value. In the figure, details of the etching gas introduction nozzle, the mass flow controller, etc. are omitted.

Example 1 This example is an example in which a substrate to be etched having an etching mask formed on a gate electrode and a W polycide layer as a wiring material extending from the gate electrode was patterned by plasma etching. A description will be given with reference to FIGS. As shown in FIG. 1A, the substrate to be etched is a gate insulating film 2 on a semiconductor substrate 1 made of silicon or the like.
A refractory metal polycide layer 5 having an n ⁺ polycrystalline silicon layer 3 and a refractory metal silicide layer 4 made of WSi _x laminated thereon is formed, and a negative chemically amplified resist (SAL-601 manufactured by Shipley Co., Ltd.) and the like are further formed. The etching mask 6 made of a resist material corresponding to the excimer laser is formed. The exposed opening area ratio of the etching target layer of the present etching target substrate is 90%, the taper angle of the etching mask 6 is 91 °, and the maximum width of the resist pattern is 0.13 μm.

This substrate to be etched is subjected to normal plasma etching conditions, that is, the conductance valve 17 has an opening of 50% and an etching gas residence time of 0.035 s.
When etching is performed with setting to ec, reaction products and their re-dissociation products are excessively deposited on the substrate to be etched. As a result, the refractory metal polycide layer pattern is thickened by 0.1 μm, and a positive dimensional conversion difference occurs. .

Therefore, in the present embodiment, the opening of the conductance valve 17 is set to 95%, the evacuation rate is increased, and the residence time of the etching gas is set to 0.03 sec or less. As an example, the refractory metal polycide layer 5 is formed under the following plasma etching conditions. Plasma etched. Cl ₂ 300 sccm O ₂ 20 sccm Gas pressure 0.4 Pa Microwave power 1000 W (2.45 MHz) Substrate bias power 50 W (800 kHz) Substrate temperature 20 ° C. State of substrate to be etched after plasma etching is shown in FIG. Shown in b). By adopting this etching condition, the size conversion difference in the isolated line pattern part is ± 0.01μ.
m, that in the line and space pattern part is ±
Within 0.005 μm, both could be achieved within 10%. This is because the reaction products WCl _x and SiOCl _x are increased as the exhaust speed is increased, that is, the residence time of the etching gas is decreased.
Etc. and the deposition of these re-dissociation products is reduced to less than half and the thickness of the side wall protective film 7 is reduced, which makes it possible to suppress the absolute value of the dimension conversion difference and its deviation. is there. The etching conditions are
For example, it contributes to the reduction of the dimension conversion difference even in the patterning in which the substrate has a resist pattern having a forward taper angle of 88 ° and the opening area ratio of the layer to be etched is almost 100%, that is, patterning in a state close to the overall etchback. be able to.

Example 2 This example is an example in which a substrate to be etched having a resist pattern formed on a gate electrode and a W polycide layer as a wiring material extending from the same is patterned by plasma etching. Yes, this is Figure 2
This will be described with reference to (a) and (b). As shown in FIG. 2A, the substrate to be etched is a semiconductor substrate 1 made of silicon or the like.
A refractory metal polycide layer 5 in which an n ⁺ polycrystalline silicon layer 3 and a refractory metal silicide layer 4 made of WSi _x are laminated is formed on the upper gate oxide film 2, and a negative type chemically amplified resist (Shipley Company) The etching mask 6 is formed of a resist corresponding to an excimer laser such as SAL-601 manufactured by SAL-601. The exposed opening area ratio of the layer to be etched of the substrate to be etched is 5%, the taper angle of the etching mask 6 is 86 °, and the maximum width of the etching mask 6 is 0.13 μm.

Since the substrate to be etched has a small amount of etching reaction products and is in a state where the sputter removal of the deposit on the side surface of the etching mask 6 is likely to proceed, the thickness of the side wall protective film becomes extremely small. . For this reason,
When etching is performed under normal plasma etching conditions, that is, the conductance valve 17 has an opening of 50% and an etching gas residence time of 0.035 sec, the refractory metal polycide layer pattern has a negative dimension conversion difference or side etching. Notching occurs.

Therefore, in this embodiment, the opening of the conductance valve 17 is set to 20%, the exhaust speed is reduced, and the residence time of the etching gas is set to 0.05 sec or more. As an example, the high melting point metal polycide layer is formed under the following plasma etching conditions. 5 was plasma etched. Cl ₂ 75 sccm O ₂ 5 sccm Gas pressure 0.4 Pa Microwave power 850 W (2.45 MHz) Substrate bias power 50 W (800 kHz) Substrate temperature 20 ° C. The state of the substrate to be etched after the plasma etching is shown in FIG. Shown in b). By adopting this etching condition, the size conversion difference in the isolated line pattern part is ± 0.01μ.
m, that in the line and space pattern part is ±
Within 0.005 μm, both could be achieved within 10%. This is because the reaction products WCl _x and SiOCl are reduced as the exhaust rate decreases, that is, the residence time of the etching gas increases.
_{This is because x,} etc., and the deposition of these re-dissociation products increased, and the thickness of the sidewall protective film 7 increased, which made it possible to suppress the absolute value of the dimension conversion difference and its deviation. is there.

Although the present invention has been described above with reference to two embodiments, the present invention is not limited to these embodiments.

For example, as a wiring layer containing a refractory metal, W
Although the patterning of the polycide layer is exemplified, it may be patterning of a refractory metal silicide layer such as WSi _x , a polycrystalline silicon layer, or an amorphous silicon layer. As the refractory metal silicide, other than WSi _x , Mo, Ta, T
It can be widely applied to silicides such as i. Polycrystalline silicon is usually used as the lower layer of the refractory metal polycide layer, but amorphous silicon is used as disclosed in Japanese Patent Application Laid-Open No. 63-163 filed by the present applicant. Good. The etching characteristics of amorphous silicon are almost the same as those of polycrystalline silicon. This amorphous silicon also has a polycide structure because it is converted into polycrystalline silicon by a heat treatment process for activation of implanted impurities when it finally functions as a gate electrode / wiring of a MOSFET.

Although Cl ₂ is exemplified as the halogen-based gas other than the fluorine-based chemical species, other Cl-based gas may be used. In addition, Br-based gas such as HBr and Br ₂ or HI
An I-based gas such as the above may be used. O ₂ gas was used together with these halogen-based gases, but halogen-based gas may be used alone, or NO _x -based gas, CO _x -based gas, a mixed gas with H ₂ O or the like, or a rare gas such as He or the like may be appropriately added. Good.

Others, such as the etching apparatus and the structure of the substrate to be etched, can be changed as appropriate within the scope of the technical idea of the present invention.

[0039]

As is apparent from the above description, according to the plasma etching method and the plasma etching apparatus of the present invention, the dimensional conversion difference does not depend on the opening area ratio at which the layer to be etched is exposed or the taper angle of the etching mask. 1
It is possible to reduce the dimensional conversion difference for each substrate to be etched by keeping it within the allowable value within 0%.

Further, according to the plasma etching method and the plasma etching apparatus of the present invention, in the processing of the fine gate electrode to which the minimum design rule is applied, the size conversion difference of the gate electrode width is controlled, and the uniformity and the reliability are excellent. It is possible to provide a semiconductor device.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view for explaining a first embodiment to which the present invention is applied in the order of steps, in which (a) is a refractory metal composed of a polycrystalline silicon layer and a refractory metal silicide layer on a base gate insulating film. A polycide layer is formed, and an etching mask having an inverse taper shape is further formed, and (b) is a state in which patterning of the wiring made of the refractory metal polycide layer is completed.

2A and 2B are schematic cross-sectional views illustrating Example 2 to which the present invention is applied in the order of steps, in which FIG. 2A is a refractory metal including a polycrystalline silicon layer and a refractory metal silicide layer on a base gate insulating film. A state in which a polycide layer is formed and an etching mask having a forward taper shape is further formed is shown, and (b) is a state in which patterning of the wiring made of the refractory metal polycide layer is completed.

FIG. 3 is a schematic sectional view showing a configuration example of a plasma etching apparatus to which the present invention is applied.

FIG. 4 is a graph showing the correlation between the residence time of the etching gas, the opening area ratio of the etching mask, and the dimension conversion difference.

FIG. 5 is a graph showing the correlation between the residence time of the etching gas, the taper angle of the etching mask, and the dimension conversion difference.

6A and 6B are schematic cross-sectional views showing states of reaction products and re-dissociation products when plasma-etching a refractory metal polycide layer. FIG. 6A is a line and space pattern, and FIG. 6B is an isolated line pattern. Show.

7A and 7B are schematic cross-sectional views when plasma-etching a refractory metal polycide layer with an inverse taper-shaped etching mask, FIG. 7A is a state in which an inverse taper-shaped etching mask is formed, and FIG. 7B is a positive dimension. This is a state where a conversion difference has occurred.

[Explanation of symbols]

 1 semiconductor substrate 2 gate insulating film 3 polycrystalline silicon layer 4 refractory metal silicide layer 5 refractory metal polycide layer 6 etching mask θ taper angle 7 sidewall protective film 8 reaction product 9 re-dissociation product 11 etched substrate 12 substrate stage 13 microwave waveguide 14 microwave introduction window 15 etching chamber 16 solenoid coil 17 conductance valve 18 vacuum pump

Claims (15)

[Claims] 1. A substrate to be etched having an etching mask formed on a conductive material layer containing silicon is etched in an etching chamber with an etching gas containing a halogen-based gas, and the conductive material containing silicon and the halogen are also included. In a plasma etching method for patterning the conductive material layer containing silicon, while depositing at least one of a reaction product with a system gas and a re-dissociation product of the reaction product on a substrate to be etched, A plasma etching method, wherein a dimensional conversion difference of the conductive material layer pattern containing silicon is controlled by a residence time of the etching gas in the etching chamber. 2. When the dimensional conversion difference of the conductive material layer pattern containing silicon is positive, the residence time of the etching gas is reduced as compared with the case where the dimensional conversion difference of the conductive material layer pattern containing silicon is negative. The plasma etching method according to claim 1, wherein the plasma etching method is controlled to be short. 3. A substrate to be etched having an etching mask formed on a conductive material layer containing silicon is etched in an etching chamber with an etching gas containing a halogen-based gas, and the conductive material containing the silicon and the halogen. In a plasma etching method for patterning the conductive material layer containing silicon, while depositing at least one of a reaction product with a system gas and a re-dissociation product of the reaction product on a substrate to be etched, A plasma etching method, wherein a residence time of the etching gas in the etching chamber is controlled by an opening area ratio at which the conductive material layer containing silicon is exposed from the etching mask. 4. When the opening area ratio of the conductive material layer containing silicon exposed from the etching mask is large, compared with the case where the opening area ratio of the conductive material layer containing silicon exposed from the etching mask is small. 4. The plasma etching method according to claim 3, wherein the residence time of the etching gas in the etching chamber is controlled to be short. 5. A substrate to be etched having an etching mask formed on a conductive material layer containing silicon is etched in an etching chamber with an etching gas containing a halogen-based gas, and the conductive material containing the silicon and the halogen. In a plasma etching method for patterning the conductive material layer containing silicon, while depositing at least one of a reaction product with a system gas and a re-dissociation product of the reaction product on a substrate to be etched, A plasma etching method, wherein a residence time of the etching gas in the etching chamber is controlled by an angle formed between a side surface of the etching mask and the conductive material layer containing silicon. 6. When the side surface of the etching mask makes an angle of 90 ° or more with the conductive material layer containing silicon, the side surface of the etching mask makes an angle of less than 90 ° with the conductive material layer containing silicon. The plasma etching method according to claim 5, wherein the residence time of the etching gas in the etching chamber is controlled to be shorter than that in the case. 7. The conductive material containing silicon is any one of non-single crystal silicon, refractory metal silicide and refractory metal polycide, according to claim 1, 3, or 5. The plasma etching method according to item 1. 8. The plasma etching method according to claim 1, wherein the residence time of the etching gas is controlled by the exhaust speed of a vacuum pump that exhausts the inside of the etching chamber. 9. The retention time of the etching gas is controlled by a vacuum pump for exhausting the inside of the etching chamber and an opening / closing degree of a conductance valve interposed between the etching chamber and the etching chamber. And the plasma etching method according to any one of 5 above. 10. The plasma density in the etching chamber is 1 × 10 ¹⁰ / cm ³ or more and 1 × 10 ¹⁴ / cm ³ or more.
The plasma etching method according to claim 1, wherein the plasma etching method is less than 1. 11. A substrate to be etched having an etching mask formed on a conductive material layer containing silicon is etched in an etching chamber with an etching gas containing a halogen-based gas, and the conductive material containing silicon and the halogen are used. A plasma etching apparatus for patterning a conductive material layer containing silicon while depositing at least one of a reaction product with a system gas and a re-dissociation product of the reaction product on a substrate to be etched, At least one of the correlation between the dimensional conversion difference and the opening area ratio at which the conductive material layer containing is exposed from the resist pattern, and the correlation between the angle formed by the side surface of the resist pattern with the silicon-containing conductive material layer and the dimensional conversion difference. Storage means for storing any one of the correlations Input for inputting at least one of opening area ratio data in which the conductive material layer containing silicon is exposed from the resist pattern, and angle data with which side surfaces of the resist pattern form the conductive material layer containing silicon. Input value of at least one of: area ratio data in which the conductive material layer containing silicon is exposed from the resist pattern, and angle data formed by a side surface of the resist pattern and the conductive material layer containing silicon. And a control means for controlling a residence time of the etching gas in the etching chamber based on the above. 12. The conductive material containing silicon is any one of non-single crystal silicon, refractory metal silicide and refractory metal polycide.
The plasma etching apparatus according to claim 11. 13. The plasma etching apparatus according to claim 11, wherein the residence time of the etching gas is controlled by the exhaust speed of a vacuum pump that exhausts the inside of the etching chamber. 14. The method according to claim 11, wherein the residence time of the etching gas is controlled by the degree of opening and closing of a conductance valve interposed between the vacuum pump for exhausting the inside of the etching chamber and the etching chamber. Plasma etching equipment. 15. The plasma density in the etching chamber is 1 × 10 ¹⁰ / cm ³ or more and 1 × 10 ¹⁴ / cm ³ or more.
The plasma etching apparatus according to claim 11, wherein the plasma etching apparatus is less than.