JPH0982593A - Semiconductor processing equipment - Google Patents

Semiconductor processing equipment

Info

Publication number
JPH0982593A
JPH0982593A JP25715795A JP25715795A JPH0982593A JP H0982593 A JPH0982593 A JP H0982593A JP 25715795 A JP25715795 A JP 25715795A JP 25715795 A JP25715795 A JP 25715795A JP H0982593 A JPH0982593 A JP H0982593A
Authority
JP
Japan
Prior art keywords
wafer
substrates
chambers
chamber
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25715795A
Other languages
Japanese (ja)
Inventor
Toshihide Miyazaki
敏英 宮崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Steel Corp
Original Assignee
Nippon Steel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Steel Corp filed Critical Nippon Steel Corp
Priority to JP25715795A priority Critical patent/JPH0982593A/en
Publication of JPH0982593A publication Critical patent/JPH0982593A/en
Pending legal-status Critical Current

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  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Physical Vapour Deposition (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PROBLEM TO BE SOLVED: To miniaturize semiconductor processing equipment and improve processing efficiency by so designing the equipment that a plurality of semiconductor substrates will be processed in a plurality of chambers. SOLUTION: A pair of wafer holders 3 that can hold a wafer 1, respectively, are positioned on both the sides of a support base 2. A pair of chambers 5 that can enclose the respective wafer holders 3 and wafers 1 are formed. The wafer holders 3 can be freely moved so that the wafers 1 can be positioned vertically and horizontally. The chambers 5 can be freely shifted between the closed position where both the wafers 1 in the vertical position are enclosed and the open position where both the wafers in the horizontal position are exposed. This makes it possible to miniaturize the equipment further than batch- type equipment can be, and achieves higher throughput than with single wafer processing-type equipment.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、例えば半導体ウエ
ハのリソグラフィ工程にて形成されたレジストパターン
の除去に用いられるレジスト除去装置等のように、半導
体基板に対する処理をチャンバー内の密閉空間で行う半
導体製造装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor for processing a semiconductor substrate in a sealed space in a chamber, such as a resist removing apparatus used for removing a resist pattern formed in a lithography process of a semiconductor wafer. Manufacturing equipment

【0002】[0002]

【従来の技術】従来、半導体デバイスの製造工程におい
て半導体ウエハに対する処理をチャンバー内の密閉空間
で行う装置、例えばレジスト除去装置には、複数枚のウ
エハを同時に処理するバッチ式と、ウエハを1枚ずつ処
理する枚葉式とがある。バッチ式装置は、処理の際に複
数枚のウエハを収容し得る大きさのチャンバーや、この
チャンバー内で複数枚のウエハを保持するウエハボート
等を有している。また、枚葉式装置では、チャンバーは
比較的小さいが、このチャンバー内に1枚のウエハを順
次収容して処理を行う。
2. Description of the Related Art Conventionally, in a semiconductor device manufacturing process, an apparatus for performing processing on a semiconductor wafer in a closed space in a chamber, for example, a resist removing apparatus, is a batch type apparatus for simultaneously processing a plurality of wafers and a single wafer type processing apparatus. There is a single-wafer type in which each is processed. The batch type apparatus has a chamber having a size capable of accommodating a plurality of wafers during processing, a wafer boat for holding a plurality of wafers in the chamber, and the like. Further, in the single wafer processing apparatus, although the chamber is relatively small, one wafer is sequentially accommodated in the chamber for processing.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、バッチ
式レジスト除去装置は、大きなチャンバーやウエハボー
ト等が必要なため、最近のウエハの大口径化に伴いチャ
ンバーやウエハボート等がさらに拡大し、装置が大型化
してきている。このため、装置のフットプリントが増大
するといった欠点があった。また、バッチ式の場合は、
複数枚のウエハを一括して処理するので、各々のウエハ
で処理結果に差が出てしまうという問題もあった。
However, since the batch type resist removing apparatus requires a large chamber, a wafer boat, etc., the chamber, wafer boat, etc. are further expanded with the recent increase in the diameter of the wafer, and the apparatus is It is getting larger. Therefore, there is a drawback that the footprint of the device increases. Also, in the case of batch type,
Since a plurality of wafers are collectively processed, there is also a problem that processing results differ between the wafers.

【0004】一方、枚葉式レジスト除去装置は、バッチ
式と比較してチャンバーが小型でウエハボートも必要な
いので、上述したようなフットプリントの増大の問題は
それ程ないが、ウエハを1枚ずつ処理するので、1バッ
チ当たりの処理時間が長くなるといった欠点があった。
On the other hand, the single-wafer type resist removing apparatus has a smaller chamber and does not require a wafer boat as compared with the batch type, so that the problem of increasing the footprint as described above does not occur so much, but one wafer at a time is used. Since processing is performed, there is a drawback that the processing time per batch becomes long.

【0005】そこで本発明は、上記課題を解決するため
になされたものであり、複数の半導体基板をそれぞれ複
数のチャンバー内で処理する構成で、装置のコンパクト
化と処理能率の向上とを共に図ることができる半導体製
造装置を提供することを目的とする。
Therefore, the present invention has been made in order to solve the above-mentioned problems, and has a structure in which a plurality of semiconductor substrates are processed in a plurality of chambers, respectively, so that the apparatus can be made compact and the processing efficiency can be improved. An object of the present invention is to provide a semiconductor manufacturing apparatus capable of performing the above.

【0006】[0006]

【課題を解決するための手段】上記目的を達成するため
に、本発明は、半導体基板に対する処理をチャンバー内
の密閉空間で行う半導体製造装置において、複数の半導
体基板をそれぞれ保持可能な複数の基板保持手段と、こ
れら各基板保持手段に保持された前記各基板を密閉可能
な複数のチャンバーとを備え、前記各基板保持手段が前
記各基板を略垂直状態に配置するように構成されている
と共に、前記各チャンバーが略垂直状態の前記各基板を
覆囲する閉塞位置と前記各基板を露出する開放位置との
間で移動自在に構成されていることを特徴とする。
In order to achieve the above object, the present invention is a semiconductor manufacturing apparatus for performing processing on a semiconductor substrate in a sealed space in a chamber. A holding means and a plurality of chambers capable of sealing the respective substrates held by the respective substrate holding means are provided, and each of the substrate holding means is configured to arrange the respective substrates in a substantially vertical state. The chambers are configured to be movable between a closed position that covers the substrates in a substantially vertical state and an open position that exposes the substrates.

【0007】また、本発明は、半導体基板に対する処理
をチャンバー内の密閉空間で行う半導体製造装置におい
て、複数の半導体基板をそれぞれ保持可能な複数の基板
保持手段と、これら各基板保持手段に保持された前記各
基板を密閉可能な複数のチャンバーとを備え、前記各基
板保持手段が前記各基板を略垂直状態と略水平状態とに
転換配置するように移動自在に構成されていると共に、
前記各チャンバーが略垂直状態の前記各基板を覆囲する
閉塞位置と略水平状態の前記各基板を露出する開放位置
との間で移動自在に構成されていることを特徴とする。
Further, according to the present invention, in a semiconductor manufacturing apparatus for processing a semiconductor substrate in a closed space in a chamber, a plurality of substrate holding means capable of respectively holding a plurality of semiconductor substrates and the substrate holding means are held. And a plurality of chambers capable of sealing each substrate, and each substrate holding means is configured to be movable so as to convert each substrate into a substantially vertical state and a substantially horizontal state.
The chambers are configured to be movable between a closed position that covers the substrates in a substantially vertical state and an open position that exposes the substrates in a substantially horizontal state.

【0008】さらに、前記各々の半導体製造装置におい
て、前記各基板保持手段が柱状をなす支持基台の側面に
配設されていることを特徴とする。
Further, in each of the semiconductor manufacturing apparatuses, each of the substrate holding means is arranged on a side surface of a columnar supporting base.

【0009】[0009]

【作用】上記のように構成された本発明においては、複
数の基板保持手段により複数の半導体基板がそれぞれ略
垂直状態に配置され、これら各基板に対してそれぞれ複
数のチャンバーが閉塞位置と開放位置との間で移動され
るので、各基板の略垂直状態の配置によって、大きなチ
ャンバーや基板ボート等が必要なく、従来のバッチ式装
置よりも装置のコンパクト化が可能となり、しかも、各
基板の同時処理によって、従来の枚葉式装置と比較して
装置のスループットの増大が可能となる。さらに、各基
板が各チャンバー内で処理される形態となるので、各基
板の処理結果が実質的に均等になる。
According to the present invention constructed as described above, a plurality of semiconductor substrates are arranged in a substantially vertical state by a plurality of substrate holding means, and a plurality of chambers are respectively closed and opened for these substrates. Since it is moved between and, the arrangement of each substrate in a substantially vertical state does not require a large chamber, substrate boat, etc., and the device can be made more compact than the conventional batch type device. The processing allows for increased throughput of the device as compared to conventional single wafer devices. Furthermore, since each substrate is processed in each chamber, the processing results of each substrate are substantially equal.

【0010】また、各基板保持手段の移動により各基板
が略垂直状態と略水平状態とに転換配置されるようにし
た場合には、各チャンバーの開放位置において各基板が
略水平状態に配置されることによって、各基板の容易な
着脱が可能となる。
Further, when the substrates are arranged to be switched between the substantially vertical state and the substantially horizontal state by the movement of the respective substrate holding means, the respective substrates are arranged in the substantially horizontal state at the open position of each chamber. By doing so, each substrate can be easily attached and detached.

【0011】さらに、各基板保持手段を柱状をなす支持
基台の側面に配設することによって、各基板保持手段の
駆動系や各基板に対する処理機能手段(例えば反応ガス
の排気系)等の共通化が可能となる。
Further, by disposing each substrate holding means on the side surface of the support base having a columnar shape, a common drive system for each substrate holding means, processing function means for each substrate (for example, reaction gas exhaust system), and the like. Can be realized.

【0012】[0012]

【発明の実施の形態】以下、本発明をレジスト除去装置
に適用した実施の形態について図面を参照して説明す
る。
BEST MODE FOR CARRYING OUT THE INVENTION Embodiments in which the present invention is applied to a resist removing apparatus will be described below with reference to the drawings.

【0013】図1〜図3は装置の概略正面図、図4はそ
の装置の図1に対応する概略平面図である。この装置
は、基本構成として、支持基台2と、一対のウエハ台3
と、一対のチャンバー5と、一対の電極8と、高周波電
源9とを備えている。
1 to 3 are schematic front views of the apparatus, and FIG. 4 is a schematic plan view of the apparatus corresponding to FIG. This apparatus has a basic structure including a support base 2 and a pair of wafer bases 3.
And a pair of chambers 5, a pair of electrodes 8 and a high frequency power source 9.

【0014】支持基台2は、例えばステンレススチール
等により偏平な四角柱状に形成され、その両側面にそれ
ぞれウエハ台3が配設されている。また、支持基台2内
には圧力調整バルブ7が付設されて排気手段(図示せ
ず)に接続されており、内部を真空状態にすることが可
能である。
The support base 2 is made of, for example, stainless steel in the shape of a flat rectangular prism, and the wafer bases 3 are provided on both side surfaces thereof. A pressure adjusting valve 7 is attached to the inside of the support base 2 and is connected to an exhaust means (not shown), so that the inside can be brought into a vacuum state.

【0015】一対のウエハ台3は、例えばステンレスス
チール等によりテーブル状に形成され、それぞれ支持基
台2に対して水平状の支点Pを中心として、図1に示す
水平状態と図2に示す垂直状態との間で矢印A及びA′
方向へ回動自在に構成されている。そして、ウエハ台3
の上面には、それぞれウエハ1を保持する例えば石英よ
りなるスリット状のウエハ保持部4が複数設けられてい
る。また、ウエハ台3には、例えば熱ヒーター等からな
る温度制御手段(図示せず)が内蔵され、ウエハ1付近
の雰囲気温度を所定温度に制御可能である。
The pair of wafer pedestals 3 are made of, for example, stainless steel in a table shape, and each has a horizontal fulcrum P with respect to the support base 2 as a center, and the horizontal state shown in FIG. 1 and the vertical state shown in FIG. Arrows A and A'to and from state
It is configured to be rotatable in any direction. And the wafer table 3
A plurality of slit-shaped wafer holding portions 4 made of, for example, quartz, each holding the wafer 1, are provided on the upper surface of the. Further, the wafer stage 3 has a temperature control means (not shown), which is composed of, for example, a heater, and is built in, and the ambient temperature near the wafer 1 can be controlled to a predetermined temperature.

【0016】一対のチャンバー5は、例えば石英により
ほぼ円筒状に形成され、支持基台2の上部から延設され
たガイド部10に沿って、それぞれ図1に示す開放位置
と図3に示す閉塞位置との間で矢印B及びB′方向へ平
行移動自在に構成されている。そして、閉塞位置におい
てチャンバー5の開口周縁が、支持基台2の側面に取付
けられた例えばバイトンゴムよりなるOリング6に密着
される。
The pair of chambers 5 are formed of, for example, quartz in a substantially cylindrical shape, and along the guide portion 10 extending from the upper portion of the support base 2, the open position shown in FIG. 1 and the blockage shown in FIG. It is configured to be movable in parallel with the position in the directions of arrows B and B '. Then, at the closed position, the opening peripheral edge of the chamber 5 is brought into close contact with the O-ring 6 made of, for example, Viton rubber, which is attached to the side surface of the support base 2.

【0017】一対の電極8は、それぞれチャンバー5と
一体に矢印B及びB′方向への移動が可能であり、高周
波電源9に接続されている。
The pair of electrodes 8 are movable in the directions of arrows B and B'integrally with the chamber 5, respectively, and are connected to a high frequency power source 9.

【0018】上記のように構成された装置において、最
初、図1及び図4に示すように、チャンバー5は矢印B
方向へ移動されて開放位置にあり、ウエハ台3は矢印A
方向へ回動されて水平状態に配置されている。この状態
でウエハ搬送系(図示せず)によりウエハ1が搬送さ
れ、ウエハ1がそれぞれウエハ台3上のウエハ保持部4
にて保持される。
In the apparatus constructed as described above, first, as shown in FIG. 1 and FIG.
Is moved to the open position, and the wafer table 3 is moved to the arrow A
It is rotated in the direction and arranged horizontally. In this state, the wafer 1 is transferred by the wafer transfer system (not shown), and the wafers 1 are held by the wafer holder 4 on the wafer table 3, respectively.
Is held at.

【0019】ウエハ保持後、ウエハ台3は矢印A′方向
へ移動され、図2に示すように、ウエハ台3即ちウエハ
1は垂直状態に配置され保持される。
After holding the wafer, the wafer stage 3 is moved in the direction of arrow A ', and as shown in FIG. 2, the wafer stage 3, that is, the wafer 1 is arranged and held vertically.

【0020】そして、チャンバー5と電極8とが一体に
矢印B′方向へ移動され、図3に示すように、チャンバ
ー5はOリング6を介して支持基台2と密着され、ウエ
ハ1及びウエハ台3は外雰囲気と完全に隔離される。
Then, the chamber 5 and the electrode 8 are integrally moved in the direction of the arrow B ', and the chamber 5 is brought into close contact with the support base 2 via the O-ring 6 as shown in FIG. The table 3 is completely isolated from the outside atmosphere.

【0021】この後、通常は閉じた状態になっている圧
力調整バルブ7が開くことにより、チャンバー5内の雰
囲気が支持基台2の開孔(図示せず)を介して吸引され
て真空状態となり、所定の圧力、例えば0.1Torr以下
に設定され、またウエハ台3に内蔵された温度制御手段
によって所定の温度、例えば100〜200℃に達す
る。
After that, the pressure control valve 7, which is normally closed, is opened, so that the atmosphere in the chamber 5 is sucked through the opening (not shown) of the support base 2 to be in a vacuum state. Then, a predetermined pressure, for example, 0.1 Torr or less is set, and a predetermined temperature, for example, 100 to 200 ° C. is reached by the temperature control means built in the wafer stage 3.

【0022】その後、チャンバー5の処理ガス導入口5
aからチャンバー5内に処理ガスO2 を例えば1000
sccmの流量で導入し、圧力調整バルブ7の調整により処
理期間中は圧力を例えば0.1〜1.0Torrの範囲、好
ましくは0.8Torr程度に維持し、高周波電源9によっ
て例えば13.56MHz、1000Wを発生させ電極
8を介してRF放電を行う。このとき、供給された処理
ガスO2 はプラズマとなりその中の酸素ラジカルO*
よって、主として炭素、水素、酸素からなるレジストを
以下の化学式のように反応させ除去する。 Cx y +O* → CO2 ↑+H2 O↑ 以上の処理を行うことにより、ウエハ1からレジストを
確実に除去することができる。
After that, the processing gas inlet 5 of the chamber 5
processing gas O 2 into the chamber 5 from, for example, 1000
It is introduced at a flow rate of sccm, and the pressure is maintained in the range of, for example, 0.1 to 1.0 Torr, preferably about 0.8 Torr during the processing period by adjusting the pressure adjusting valve 7, and the high frequency power supply 9 operates at 13.56 MHz, for example. RF power is generated through the electrode 8 by generating 1000 W. At this time, the supplied processing gas O 2 becomes plasma, and the oxygen radicals O * in the plasma react and remove the resist mainly consisting of carbon, hydrogen, and oxygen as shown in the following chemical formula. C x H y + O * → CO 2 ↑ + H 2 O ↑ By performing the above processing, the resist can be reliably removed from the wafer 1.

【0023】このように、本装置においては、両ウエハ
台3により両ウエハ1がそれぞれ垂直状態に配置され、
これら両ウエハ1に対してそれぞれ両チャンバー5が開
放位置と閉塞位置との間で移動されるので、大きなチャ
ンバーや基板ボート等が必要なく、従来のバッチ式装置
よりも装置をコンパクト化することができる。しかも、
両ウエハ1の同時処理によって、従来の枚葉式装置と比
較して装置のスループットを増大することができる。さ
らに、両ウエハ1が両チャンバー5内で処理される形態
となるので、両ウエハ1のレジスト除去結果を実質的に
均等にすることができる。
As described above, in the present apparatus, both wafers 3 are vertically arranged by both wafer stands 3.
Since both chambers 5 are moved between the open position and the closed position with respect to both of these wafers 1, a large chamber, a substrate boat, etc. are not required, and the device can be made more compact than the conventional batch type device. it can. Moreover,
Simultaneous processing of both wafers 1 can increase the throughput of the apparatus as compared with the conventional single wafer processing apparatus. Furthermore, since both wafers 1 are processed in both chambers 5, the resist removal results of both wafers 1 can be substantially equalized.

【0024】そして、処理終了後は、上述の逆動作によ
って、チャンバー5が図2の開放位置へ移動された後、
ウエハ台3即ちウエハ1が図1の水平状態に転換配置さ
れ、ウエハ台3からウエハ1が取り出される。即ち、本
装置においては、両チャンバー5の開放位置において両
ウエハ1が水平状態に配置されることによって、両ウエ
ハ1を容易に着脱することができる。なお、図2に示す
ウエハ台3の垂直状態で、ウエハ1の着脱を行うことも
可能である。
After the processing is completed, the chamber 5 is moved to the open position shown in FIG.
The wafer stage 3, that is, the wafer 1 is converted and arranged in the horizontal state of FIG. 1, and the wafer 1 is taken out from the wafer stage 3. That is, in this apparatus, both wafers 1 can be easily attached and detached by arranging both wafers 1 in a horizontal state at the open position of both chambers 5. The wafer 1 can be attached / detached while the wafer stage 3 shown in FIG.

【0025】さらに、本装置においては、両ウエハ台3
を柱状をなす支持基台2の両側面に配設することによっ
て、両ウエハ台3の駆動系や反応ガスの排気系等を支持
基台2の内部において共通化することができるので、各
機構の簡略化を図ることができる。
Further, in this apparatus, both wafer stands 3
By arranging the columns on both side surfaces of the support base 2 having a columnar shape, the drive system of both wafer bases 3, the exhaust system of the reaction gas, and the like can be shared within the support base 2, so that each mechanism can be used. Can be simplified.

【0026】以上、本発明の実施の形態について説明し
たが、本発明は上記実施形態に限定されることなく、本
発明の技術的思想に基づいて各種の有効な変更並びに応
用が可能である。例えば、この実施形態では2枚のウエ
ハを処理する例について説明したが、支持基台を三角形
柱状や正方形柱状にして側面で3枚以上の基板を処理す
るような構成も可能であり、さらに基板保持手段及びチ
ャンバーを上下に複数設けることも可能である。また、
この実施形態ではチャンバーを平行移動式としたが、回
動式のチャンバーとしてもよい。なお、この実施形態で
はウエハのレジスト除去装置について説明したが、本発
明は各種の半導体基板に対する様々な処理をチャンバー
内で行う各種の半導体製造装置に適用可能である。
Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various effective modifications and applications are possible based on the technical idea of the present invention. For example, although an example in which two wafers are processed has been described in this embodiment, a configuration in which the support base is formed in a triangular column shape or a square column shape and three or more substrates are processed on the side surface is also possible. It is also possible to provide a plurality of holding means and chambers above and below. Also,
In this embodiment, the chamber is of a parallel movement type, but it may be of a rotation type. Although the wafer resist removing apparatus has been described in this embodiment, the present invention can be applied to various semiconductor manufacturing apparatuses that perform various processes on various semiconductor substrates in a chamber.

【0027】[0027]

【発明の効果】以上説明したように、本発明によれば、
複数の半導体基板をそれぞれ略垂直状態に配置して、各
基板をそれぞれ複数のチャンバー内で処理することによ
って、大きなチャンバーや基板ボート等が不要であるた
め、従来のバッチ式装置よりも装置のコンパクト化及び
処理結果の均等化を図ることができ、しかも、従来の枚
葉式装置と比較して複数の基板を同時に処理することが
可能であるため、装置のスループットを増大させること
ができる。
As described above, according to the present invention,
By placing a plurality of semiconductor substrates in a substantially vertical state and processing each substrate in a plurality of chambers, a large chamber, substrate boat, etc. are not required, so the device is more compact than the conventional batch type device. It is possible to achieve uniformization and equalization of processing results, and since it is possible to process a plurality of substrates at the same time as compared with the conventional single wafer processing apparatus, it is possible to increase the throughput of the apparatus.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施の形態のレジスト除去装置におけ
るチャンバー開放位置でウエハ水平状態を示す概略正面
図である。
FIG. 1 is a schematic front view showing a wafer horizontal state at a chamber open position in a resist removing apparatus according to an embodiment of the present invention.

【図2】上記実施形態の装置におけるチャンバー開放位
置でウエハ垂直状態を示す概略正面図である。
FIG. 2 is a schematic front view showing a wafer vertical state in a chamber open position in the apparatus of the above embodiment.

【図3】上記実施形態の装置におけるチャンバー閉塞位
置でウエハ垂直状態を示す概略正面図である。
FIG. 3 is a schematic front view showing a wafer vertical state at a chamber closed position in the apparatus of the above embodiment.

【図4】上記実施形態の装置における図1に対応する概
略平面図である。
FIG. 4 is a schematic plan view corresponding to FIG. 1 in the apparatus of the above embodiment.

【符号の説明】[Explanation of symbols]

1 ウエハ(半導体基板) 2 支持基台 3 ウエハ台 4 ウエハ保持部 5 チャンバー 5a 処理ガス導入口 6 Oリング 7 圧力調整バルブ 8 電極 9 高周波電源 10 チャンバーの支持部 P ウエハ台の回動支点 1 Wafer (semiconductor substrate) 2 Support base 3 Wafer base 4 Wafer holding part 5 Chamber 5a Processing gas inlet 6 O-ring 7 Pressure adjusting valve 8 Electrode 9 High frequency power supply 10 Chamber support P Pivoting fulcrum of wafer base

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板に対する処理をチャンバー内
の密閉空間で行う半導体製造装置において、 複数の半導体基板をそれぞれ保持可能な複数の基板保持
手段と、これら各基板保持手段に保持された前記各基板
を密閉可能な複数のチャンバーとを備え、 前記各基板保持手段が前記各基板を略垂直状態に配置す
るように構成されていると共に、前記各チャンバーが略
垂直状態の前記各基板を覆囲する閉塞位置と前記各基板
を露出する開放位置との間で移動自在に構成されている
ことを特徴とする半導体製造装置。
1. In a semiconductor manufacturing apparatus for processing a semiconductor substrate in a closed space in a chamber, a plurality of substrate holding means capable of respectively holding a plurality of semiconductor substrates, and each of the substrates held by the respective substrate holding means. And a plurality of chambers capable of sealing, each of the substrate holding means is configured to arrange each of the substrates in a substantially vertical state, and each of the chambers surrounds each of the substrates in a substantially vertical state. A semiconductor manufacturing apparatus, which is configured to be movable between a closed position and an open position where each substrate is exposed.
【請求項2】 半導体基板に対する処理をチャンバー内
の密閉空間で行う半導体製造装置において、 複数の半導体基板をそれぞれ保持可能な複数の基板保持
手段と、これら各基板保持手段に保持された前記各基板
を密閉可能な複数のチャンバーとを備え、 前記各基板保持手段が前記各基板を略垂直状態と略水平
状態とに転換配置するように移動自在に構成されている
と共に、前記各チャンバーが略垂直状態の前記各基板を
覆囲する閉塞位置と略水平状態の前記各基板を露出する
開放位置との間で移動自在に構成されていることを特徴
とする半導体製造装置。
2. A semiconductor manufacturing apparatus for performing processing on a semiconductor substrate in a closed space within a chamber, and a plurality of substrate holding means capable of respectively holding a plurality of semiconductor substrates, and each of the substrates held by each of the substrate holding means. And a plurality of chambers capable of sealing the respective substrates, the substrate holding means being configured to be movable so as to convert the substrates into a substantially vertical state and a substantially horizontal state, and the respective chambers being substantially vertical. The semiconductor manufacturing apparatus is configured so as to be movable between a closed position that surrounds each of the substrates in a state and an open position that exposes each of the substrates in a substantially horizontal state.
【請求項3】 前記各基板保持手段が柱状をなす支持基
台の側面に配設されていることを特徴とする請求項1ま
たは2記載の半導体製造装置。
3. The semiconductor manufacturing apparatus according to claim 1, wherein each of the substrate holding means is arranged on a side surface of a support base having a columnar shape.
JP25715795A 1995-09-08 1995-09-08 Semiconductor processing equipment Pending JPH0982593A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25715795A JPH0982593A (en) 1995-09-08 1995-09-08 Semiconductor processing equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25715795A JPH0982593A (en) 1995-09-08 1995-09-08 Semiconductor processing equipment

Publications (1)

Publication Number Publication Date
JPH0982593A true JPH0982593A (en) 1997-03-28

Family

ID=17302502

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25715795A Pending JPH0982593A (en) 1995-09-08 1995-09-08 Semiconductor processing equipment

Country Status (1)

Country Link
JP (1) JPH0982593A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1069599A3 (en) * 1999-07-15 2002-12-04 MooHan Co., Ltd Apparatus for deposition of thin films on wafers
WO2003048430A1 (en) * 2001-11-27 2003-06-12 Osram Opto Semiconductors Gmbh Device and method for producing, removing or treating layers on a substrate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1069599A3 (en) * 1999-07-15 2002-12-04 MooHan Co., Ltd Apparatus for deposition of thin films on wafers
WO2003048430A1 (en) * 2001-11-27 2003-06-12 Osram Opto Semiconductors Gmbh Device and method for producing, removing or treating layers on a substrate

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