JPH098157A - Nonvolatile semiconductor memory device and its manufacture - Google Patents

Abstract

PURPOSE: To provide a nonvolatile semiconductor memory device which holds electrons stored in a floating gate surely and increases a storage characteristic. CONSTITUTION: A silicon oxide film 11 in, e.g. 100nm is formed on the surface of a silicon wafer 10. Then, bron ions (B<+> ) only in a prescribed amount are implanted through the silicon oxide film 11. After theroxide film 11 has been removed, a tunnel oxide film 12 in a film thickness of about 5nm is formed. Then, the wafer 10 is installed inside a reaction furnace, and a floating gate by a polysilicon film 13 is formed on the surface of the tunnel oxide film 12. In the polysilicon film 13, the impurity concentration of an intermediate part 132 is formed to be higher than that in a shallow part 133 and a deep part 131. Instead of this, the impurity concentration may be changed continuously.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an EEPROM and an EP.
The present invention relates to a nonvolatile semiconductor memory device having a floating gate such as a ROM and a manufacturing method thereof.

[0002]

2. Description of the Related Art FIG. 2 is a schematic sectional view showing a nonvolatile semiconductor memory device having a channel injection structure which is a kind of electrically erasable and writable EEPROM. This is called a flash memory and has a stack structure in which a tunnel oxide film 2, a polysilicon floating gate 3, an interlayer insulating film 4 and a control gate 5 are sequentially stacked on a silicon wafer 1. The drain 6 and the source 7 are formed as an n ⁺ diffusion layer in a P channel type silicon wafer. The role of the floating gate 3 in such a non-volatile semiconductor memory device is to reliably hold the electrons accumulated therein in a normal state except when erasing data so as not to be discharged.

That is, in the flash memory, when writing data, a high voltage is applied between the control gate 5 and the drain 6, and a saturated channel current flows between the source and the drain. At this time, electrons are accumulated in the floating gate 3 through the tunnel oxide film 2. In such an n-channel transistor, the potential barrier between the floating gate 3 and the oxide film 4 is 3.
Since it is 2 eV, a higher voltage is applied to the source when erasing data.

FIG. 3 is a diagram showing an impurity concentration distribution in the polysilicon which becomes the floating gate 3. Generally, first, low pressure CVD (chemical vapor deposition) is performed on the upper surface of the tunnel oxide film 2.
By the method, polysilicon (polycrystalline Si) is formed to a thickness of 100 nm, for example. After that, the stacked polysilicon was doped with impurities such as phosphorus (P) by a method such as ion implantation or diffusion. At this time,
The maximum concentration of doped P is at a depth of about 20 nm from the surface, and the concentration distribution becomes slightly lower as it approaches the tunnel oxide film 2.

[0005]

FIG. 4 shows a polysilicon floating gate 3, a tunnel oxide film 2, and a silicon wafer 1.
It is a figure which shows the energy band in. As shown in the figure, the energy band of the floating gate 3 is substantially flat, and thus the electrons accumulated therein are likely to be emitted through the tunnel oxide film or the like. Whether or not electrons are stored in the floating gate is determined by measuring the threshold voltage. FIG. 5 is a diagram showing the data retention characteristics of the EEPROM. About 20 nonvolatile semiconductor memory devices are provided here.
V _t (t) −V _t (0) is maintained at 0 ° C. and the threshold voltage V _t (t) decreases from the initial threshold voltage V _t (0) as time t passes. Is shown as a change with time. By the dashed _{line, Vt (t) -V t (} 0) in the floating gate having a conventional concentration distribution shown in FIG. 3 is shown.

In FIG. 3, as can be seen from the fact that V _t (t) -V _t (0) decreases with time, in the conventional nonvolatile semiconductor memory device, the energy band of the floating gate becomes almost flat. Therefore, there has been a problem that the electrons once accumulated in the floating gate are largely emitted over time.

The present invention has been made to solve the above-mentioned problems, and a first object thereof is to ensure that electrons accumulated in a floating gate are held and a nonvolatile semiconductor having improved storage characteristics. A storage device is provided.

A second object of the present invention is to provide a method for manufacturing a nonvolatile semiconductor memory device having good storage characteristics as described above.

[0009]

A nonvolatile semiconductor memory device according to a first aspect of the present invention is a nonvolatile semiconductor memory device having a floating gate, wherein the polysilicon film forming the floating gate has a shallower portion and a deeper portion. The feature is that the donor impurity concentration of the intermediate portion is formed higher.

The device of claim 2 is characterized in that the ratio of the impurity concentration of the intermediate portion of the polysilicon film to the impurity concentration of the shallow portion and the deep portion is formed to be 2.7 or more.

The device of claim 3 is characterized in that the impurity concentration of the intermediate portion of the polysilicon film is formed to be 1 × 10 ¹⁹ (/ cm ³ ) or more.

A method of manufacturing a nonvolatile semiconductor memory device according to a fourth aspect is the method of manufacturing a nonvolatile semiconductor memory device, wherein a polysilicon film containing a donor impurity is stacked on a tunnel oxide film to form a floating gate. The partial pressure ratio in the reactor is changed so that the partial pressure ratio of the impurity gas in the middle period is higher than the partial pressure ratio of the impurity gas to the source gas in the initial and final stages of the process of forming the floating gate. To do.

The method of claim 5 is characterized in that the partial pressure ratio in the reaction furnace is changed by changing the flow rate of the impurity gas flowing into the reaction furnace.

The method of claim 6 is characterized in that the flow rate of the impurity gas flowing into the reaction furnace is continuously changed.

[0015]

In the device according to the first aspect, the electrons injected into the floating gate are once accumulated, and are difficult to escape,
Data retention characteristics are improved.

In the device according to the second aspect of the present invention, the impurity concentration of the intermediate portion is 2.7 times or more higher than that of the shallow portion and the deep portion of the polysilicon film, thereby ensuring reliability when used at room temperature. it can.

In the device according to the third aspect, it is possible to realize the floating gate of the nonvolatile semiconductor memory device having an energy band of a depth at which electrons do not escape thermally.

In the manufacturing method according to the fourth aspect, the partial pressure ratio of the impurity gas to the source gas in the reaction furnace is changed so that the impurity concentration in the shallow and deep portions of the polysilicon film forming the floating gate is higher than the impurity concentration. The impurity concentration of the intermediate portion can be increased.

In the manufacturing method according to the fifth aspect, the flow rate of the impurity gas is changed to control the partial pressure ratio to form the polysilicon film forming the floating gate.

In the manufacturing method according to the sixth aspect, the polysilicon film forming the floating gate is formed by continuously changing the flow rate of the impurity gas and controlling the partial pressure ratio.

[0021]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

Example 1. FIG. 1 is a diagram showing a procedure for forming a polysilicon film forming a floating gate in the nonvolatile semiconductor memory device according to the first embodiment of the present invention. First,
A silicon wafer 10 to be a p-type substrate is prepared, and an organic cleaning material, a natural oxide film and the like on its surface are removed by an arbitrary cleaning solution. After that, a silicon oxide film 11 having a predetermined thickness, for example 100 nm, is formed on the surface of the silicon wafer 10. Further, a predetermined amount of boron ions (B ⁺ ) are implanted through the silicon oxide film 11 (FIG. 9A). After removing the oxide film 11, a tunnel oxide film 12 having a thickness of about 5 mm is formed.
Are formed ((b) in the figure).

Next, the wafer 10 is set in the reaction furnace,
A floating gate made of the polysilicon film 13 is formed on the surface of the tunnel oxide film 12 by the low pressure CVD method. The polysilicon film 13 has a thickness of about 25 nm as shown in FIG.
And a second region 132 having a thickness of about 50 nm,
Consists of a third region 133 with a thickness of about 25 nm and a total of about 100
It has a film thickness of nm. Then, the impurity concentration of the intermediate second region 132 is formed higher than the impurity concentration of the third region 133 forming the shallow portion and the deep first region 131 on the substrate. Here, the impurities are donor impurities, and, for example, phosphorus (P) is used.

FIG. 6 is a flow chart showing the manufacturing process of the nonvolatile semiconductor memory device of the first embodiment. Process P1 to P3
Are processes corresponding to FIGS. 1A to 1C until the above-described three-layer polysilicon film 13 is formed. Step P4 is a step of forming the interlayer insulating film 14 and the control gate electrode 15. As shown in FIG. 7, the interlayer insulating film 14 is formed on the polysilicon film 13 to a thickness of about 15 nm, and the control gate electrode 15 is formed on the interlayer insulating film 14 to a predetermined thickness by an arbitrary method. Is formed as a polysilicon film. Step P5 is a step of forming a source region and a drain region of the nonvolatile semiconductor memory device. Here, a resist film is applied to the surface of the control gate electrode 15, exposed by a predetermined mask pattern, and developed, and then an unnecessary portion of the control gate electrode 1 is etched.
5, the interlayer insulating film 14, the polysilicon film 13 and the tunnel oxide film 12 are removed. Further, phosphorus (P) ions are implanted using the resist film as a mask to remove the silicon wafer 1
A source region 16 and a drain region 17 are formed in 0. Process P6 is a process of resist removal and annealing. The resist film is removed, and annealing is performed at 900 ° C. for 30 minutes, for example, to complete the nonvolatile semiconductor memory device as shown in FIG. Note that the electrode layers and the like are omitted in FIG.

At the time of injecting and releasing electrons into the floating gate of the nonvolatile semiconductor memory device, the control gate electrode 15 is used.
A voltage of 3.3 V is applied between the silicon substrate 10 and the silicon substrate 10. At the time of injection, the control gate electrode 15 is positively biased, and at the time of discharge, the control gate electrode 15 is negatively biased.

FIG. 9 is a diagram for explaining state changes in the reaction furnace when the above-mentioned three-layer polysilicon film 13 is formed. Silicon hydride gas (monosilane: SiH
₄ ) and hydrogen phosphide gas (phosphine diluted to 1% with H ₂ : PH ₃ / H ₂ ) as a source gas and an impurity gas, and hydrogen gas (H ₂ ) as a reducing gas for cleaning. It can be supplied by adjusting the flow rate.

First, only hydrogen gas is supplied at 230 sccm (standard
The temperature in the furnace is raised while supplying the liquid, and when the wafer temperature rises to 570 ° C. at time t ₁ , the temperature is maintained. After that, while maintaining the pressure at 0.3 Torr in the reaction furnace, 700 sccm of the raw material gas, monosilane, 35 sccm of the phosphine, and 230 s of the hydrogen gas were used.
Adjust to ccm and send. This reduces the phosphorus concentration
The first region 131 of 0.9 × 10 ¹⁹ (/ cm ³ ) is formed. For example, after about 10 minutes, at time t ₂ , only the flow rate of phosphine is increased to 135 sccm without changing other conditions.
In that state, the formation of the polysilicon film is continued until time t ₃ . As a result, the second phosphorus concentration of about 8 × 10 ¹⁹ (/ cm ³ )
A region is formed. This time (time between t ₂ and t ₃ ) is, for example, about twice the time for forming the first region, that is, about 20 minutes. Finally, the flow rate of phosphine is returned to 35 sccm without changing other conditions, and the polysilicon film formation is continued in that state until time t ₄ . As a result, a third region having a phosphorus concentration of about 0.9 × 10 ¹⁹ (/ cm ³ ) is formed. After that, the supply of the raw material gases monosilane and phosphine is stopped, the temperature inside the furnace is lowered, and when the wafer temperature drops to 100 ° C, the wafer is taken out from the reaction furnace.

FIG. 10 is a diagram showing a phosphorus concentration distribution in the polysilicon film according to the present invention. The horizontal axis represents the depth (nm) from the surface of the polysilicon film 13 forming the floating gate, and the vertical axis represents the phosphorus concentration (/ cm ³ ). This polysilicon film 13 changes the flow rate of phosphine flowing into the reaction furnace discontinuously between time t2 and time t3,
By changing the partial pressure ratio of impurities in the reactor,
The impurity concentration of the intermediate portion is higher than that of the shallow portion and the deep portion.

FIG. 11 is a diagram showing the energy band of the polysilicon film according to the present invention. Here, the bottom of the conduction band is lower in the central portion of the polysilicon film 13 than in other regions. In the conventional example, as shown in FIG. 12, since the energy band of the polysilicon film forming the floating gate is substantially horizontal, the electrons injected therein are likely to escape even if they are once accumulated. On the other hand, in the case of the present invention, as shown in FIG. 13, electrons injected into the polysilicon film forming the floating gate enter the depression of the conduction band,
You can't get out of it easily. Therefore, the floating gate thus formed can improve the data retention characteristic of the nonvolatile semiconductor memory device. Practically, the impurity concentration in the middle portion of the polysilicon film 13 is set to 1 × 10 ¹⁹
If it is formed to (/ cm ³ ) or more, it functions as a floating gate of a nonvolatile semiconductor memory device having an energy band of a depth at which electrons do not thermally escape. Then, the polysilicon film 1
By forming the ratio of the impurity concentration of the shallow portion and the deep portion of No. 3 to the impurity concentration of the intermediate portion to 2.7 or more, the data retention characteristic of the nonvolatile semiconductor memory device is improved as compared with the conventional device. Is recognized.

V _t (t) -V indicated by the solid line in FIG.
As can be seen from the small decrease in _t (0), the conventional E
The data retention characteristic is significantly improved as compared with the data retention characteristic of the EPROM.

Embodiment 2 FIG. In the second embodiment, as in the first embodiment, in the reactor, the partial pressure ratio in the middle period is relatively higher than the partial pressure ratio of the impurities in the initial and final stages of the floating gate formation process. The non-volatile semiconductor memory device is manufactured by switching the partial pressure ratio of impurities.
At that time, the flow rate of the impurity gas flowing into the reaction furnace is continuously changed.

FIG. 14 is a diagram for explaining the state change in the reaction furnace when forming the polysilicon film in the second embodiment. As in the first embodiment, the reaction in the furnace silicon hydride gas (monosilane: SiH ₄₎ and phosphine gas (phosphine diluted to 1% H _2: PH ₃ / H ₂
) Is used as a source gas and an impurity gas, and hydrogen gas (H ₂ ) is supplied as a reducing gas for cleaning after being adjusted to predetermined flow rates.

First, the temperature in the furnace is raised while supplying only 230 sccm of hydrogen gas, and the wafer temperature is increased to 570 at time t _5.
When the temperature rises to ° C, hold that temperature. Then, while maintaining the pressure at 0.3Toor, monosilane is fixed at 700sccm and hydrogen gas is fixed at 230sccm, and phosphine is fed while increasing from 35sccm to 5sccm per minute. In that state, the formation of the polysilicon film is continued until time t ₆ . As a result, the phosphorus concentration of the polysilicon film is first about 1 × 10 ¹⁹ (/ cm ³ ), and then gradually increases, and the flow rate of phosphine is 135 sccm at time t ₆ after about 20 minutes, for example. And the phosphorus concentration is about 1 × 10 ²⁰ (/ cm ³ ).
Becomes Next, 700 sccm of monosilane and 230 sc
Keeping the sccm fixed, reduce the phosphine flow rate from 135 sccm to 5 sccm per minute. In that state, time t ₇
The formation of the polysilicon film is continued until. As a result, the flow rate of phosphine is 35 s at the time t ₇ about 20 minutes later.
Return to ccm. Thus, the polysilicon film 13 having a film thickness of about 100 nm is formed. After that, the supply of the raw material gases monosilane and phosphine is stopped, the temperature inside the furnace is lowered, and when the wafer temperature drops to 100 ° C, the wafer is taken out from the reaction furnace.

The subsequent steps of forming the interlayer insulating film 14 and the control gate electrode 15, etc. are the same as those in the first embodiment.

FIG. 15 is a diagram showing the distribution of phosphorus concentration in the polysilicon film according to the second embodiment. The impurity concentration distribution inside the polysilicon film 13 has an inverse V
It becomes a letter shape, and has a peak in the central portion in the thickness direction. Therefore, as will be described later, there are the same operational effects as those of the first embodiment. Compared with the manufacturing method of the first embodiment, the change in the phosphorus concentration is gentle, so that the gas flow rate control in the reaction furnace is easy.

FIG. 16 is a diagram showing the energy band of the polysilicon film according to the second embodiment. Here, the bottom of the conduction band in the central portion of the polysilicon film 13 is lower than the other regions of the floating gate. Practically, the impurity concentration in the middle portion of the polysilicon film 13 is set to 1 × 10 ¹⁹ (/ cm ³ )
If formed as described above, a floating gate having an energy band of a depth that prevents electrons from escaping thermally can be obtained. And
By forming the ratio of the impurity concentration of the middle portion of the polysilicon film 13 to the impurity concentration of the shallow portion and the deep portion of 2.7 or more, the data retention characteristic is improved as compared with the conventional device.

In addition, in order to change the partial pressure ratio between the source gas and the impurity gas, the flow rate of the phosphine which is the impurity gas is changed in the above embodiments, but the flow rate of the source gas may be changed.

Although the flash erasable flash EEPROM is explained as the nonvolatile semiconductor memory device in the above-mentioned embodiment, the floating gate can be constructed in the same way for the UV erasable EPROM.

[0039]

Since the present invention is configured as described above, it is possible to provide a nonvolatile semiconductor memory device with improved data retention characteristics of the semiconductor memory device.

Further, when the polysilicon film is laminated on the tunnel oxide film, the floating gate having a high impurity concentration in the intermediate portion is formed while changing the partial pressure ratio of the impurity gas. It is possible to obtain a non-volatile semiconductor memory device having good retention characteristics.

[Brief description of drawings]

FIG. 1 is a sectional view showing a configuration of a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view showing a nonvolatile semiconductor memory device having a channel injection structure.

FIG. 3 is a diagram showing an impurity concentration distribution in conventional polysilicon.

FIG. 4 is a diagram showing a conventional energy band.

FIG. 5 is a diagram showing data holding characteristics of the EEPROM of the related art and the EEPROM of the present invention.

FIG. 6 is a flowchart showing a manufacturing process of the nonvolatile semiconductor memory device of the present invention.

FIG. 7 is a cross-sectional view showing a step of forming an interlayer insulating film and a control gate electrode in step P4.

FIG. 8 is a cross-sectional view showing a completed nonvolatile semiconductor memory device.

FIG. 9 is used when forming the polysilicon film of Example 1;
It is a figure explaining the state change in a reaction furnace.

FIG. 10 is a diagram showing a phosphorus concentration distribution state in a polysilicon film according to Example 1.

11 is a diagram showing an energy band of Example 1. FIG.

FIG. 12 is an energy band diagram of a polysilicon film forming a conventional floating gate.

13 is an energy band diagram of a polysilicon film forming the floating gate of Example 1. FIG.

FIG. 14 is a diagram for explaining state changes in the reaction furnace when forming the polysilicon film of Example 2;

FIG. 15 is a diagram showing a phosphorus concentration distribution state in a polysilicon film according to Example 2.

16 is a diagram showing energy bands of Example 2. FIG.

[Explanation of symbols]

10 Silicon wafer, 12 Tunnel oxide film, 13
Polysilicon film, 131 first region, 132 second region, 133 third region.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 27/115

Claims (6)

[Claims] 1. A nonvolatile semiconductor memory device having a floating gate, characterized in that a donor impurity concentration of a middle portion of the polysilicon film forming the floating gate is higher than that of a shallow portion and a deep portion of the polysilicon film. Nonvolatile semiconductor memory device. 2. The non-volatile according to claim 1, wherein the ratio of the impurity concentration of the middle portion of the polysilicon film to the impurity concentration of the shallow portion and the deep portion is formed to be 2.7 or more. Semiconductor memory device. 3. The nonvolatile according to claim 1, wherein the impurity concentration of the middle portion of the polysilicon film is formed to be 1 × 10 ¹⁹ (/ cm ³ ) or more. Semiconductor memory device. 4. A method of manufacturing a non-volatile semiconductor memory device, comprising: forming a floating gate by laminating a polysilicon film containing a donor impurity on a tunnel oxide film; and a source gas at an initial stage and a final stage of the floating gate forming step. A method for manufacturing a nonvolatile semiconductor memory device, characterized in that the partial pressure ratio in the reaction furnace is changed so that the partial pressure ratio of the impurity gas in the middle period is higher than the partial pressure ratio of the impurity gas to. 5. The method of manufacturing a nonvolatile semiconductor memory device according to claim 4, wherein the partial pressure ratio in the reaction furnace is changed by changing the flow rate of the impurity gas flowing into the reaction furnace. 6. The method of manufacturing a nonvolatile semiconductor memory device according to claim 5, wherein the flow rate of the impurity gas flowing into the reaction furnace is continuously changed.