JP3157092B2 - Manufacturing method of nonvolatile semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an EEPROM or an EP
The method of manufacturing a nonvolatile semiconductor memory device having a floating gate, such as ROM.

[0002]

2. Description of the Related Art FIG. 2 is a schematic sectional view showing a non-volatile semiconductor memory device having a channel injection structure, which is a kind of electrically erasable and writable EEPROM. This is called a flash memory, and has a stack structure in which a tunnel oxide film 2, a polysilicon floating gate 3, an interlayer insulating film 4, and a control gate 5 are sequentially stacked on a silicon wafer 1. The drain 6 and the source 7 are formed as n ⁺ diffusion layers in a P-channel type silicon wafer. The role of the floating gate 3 in such a nonvolatile semiconductor memory device is to reliably hold the electrons stored therein so as not to be released in a normal state except when erasing data.

That is, in writing data in a flash memory, a high voltage is applied between the control gate 5 and the drain 6 and a saturated channel current flows between the source and the drain. At this time, electrons are accumulated in the floating gate 3 through the tunnel oxide film 2. In such an n-channel transistor, the potential barrier between the floating gate 3 and the oxide film 4 is 3.
Since it is 2 eV, when erasing data, a higher voltage is applied to the source.

FIG. 3 is a diagram showing an impurity concentration distribution in polysilicon to be the floating gate 3. As shown in FIG. Generally, first, a low pressure CVD (chemical vapor deposition) is formed on the upper surface of the tunnel oxide film 2.
By the method, polysilicon (polycrystalline Si) is formed to a thickness of, for example, 100 nm. Thereafter, impurities such as phosphorus (P) are doped into the laminated polysilicon by a method such as ion implantation or diffusion. At this time,
The maximum concentration of P to be doped is at a depth of about 20 nm from the surface, and the concentration distribution becomes slightly lower as approaching the tunnel oxide film 2.

[0005]

FIG. 4 shows a floating gate 3, a tunnel oxide film 2, and a silicon wafer 1 of polysilicon.
FIG. 4 is a diagram showing an energy band in FIG. As shown in the figure, since the energy band of the floating gate 3 is substantially flat, the electrons stored therein are easily emitted through a tunnel oxide film or the like. Whether or not electrons are accumulated in the floating gate is determined by measuring a threshold voltage. FIG. 5 is a diagram showing data retention characteristics of the EEPROM. Here, about 20 nonvolatile semiconductor memory devices are used.
At 0 ° C., the state in which the threshold voltage V _t (t) decreases from the initial threshold voltage V _t (0) as time t elapses is represented by V _t (t) −V _t (0). Are shown as changes over time. By the dashed _{line, Vt (t) -V t (} 0) in the floating gate having a conventional concentration distribution shown in FIG. 3 is shown.

[0006] In FIG. 3, as can be seen from the _{V t (t) -V t (} 0) is decreased with time, the energy band of the floating gate is substantially flat in the conventional nonvolatile semiconductor memory device Therefore, there is a problem that the emission of the electrons once accumulated in the floating gate over time is large.

[0007] The present invention has been made to solve the above problems, an object of the electrons stored in the floating gate can be reliably held, the non-volatile semiconductor memory device with improved storage properties Is to provide a method of manufacturing the same.

[0008]

[0009]

[0010]

[0011]

[0012]

According to a first aspect of the present invention, there is provided a method of manufacturing a nonvolatile semiconductor memory device, comprising forming a floating gate by stacking a polysilicon film containing a donor impurity on a tunnel oxide film. In the device manufacturing method, the partial pressure ratio in the reaction furnace is set so that the partial pressure ratio of the impurity gas in the middle period is higher than the partial pressure ratio of the impurity gas to the source gas in the initial and final stages of the floating gate forming step. It is characterized by changing.

The method according to claim 2 is characterized in that the partial pressure ratio in the reactor is changed by changing the flow rate of the impurity gas flowing into the reactor.

A method according to a third aspect is characterized in that the flow rate of the impurity gas flowing into the reaction furnace is continuously changed.

[0015]

[0016]

[0017]

[0018]

In the manufacturing method according to the first aspect , the partial pressure ratio of the impurity gas to the source gas in the reaction furnace is changed so that the impurity concentration of the polysilicon film constituting the floating gate is lower than that of the shallow portion and the deep portion. , The impurity concentration in the intermediate portion can be made higher.

According to a second aspect of the present invention, the polysilicon film forming the floating gate is formed by changing the flow rate of the impurity gas and controlling the partial pressure ratio.

According to a third aspect of the present invention, the polysilicon film forming the floating gate is formed by continuously changing the flow rate of the impurity gas and controlling the partial pressure ratio.

[0021]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

Embodiment 1 FIG. FIG. 1 is a diagram showing a procedure for forming a polysilicon film forming a floating gate in the nonvolatile semiconductor memory device according to the first embodiment of the present invention. First,
A silicon wafer 10 serving as a p-type substrate is prepared, and organic contaminants, natural oxide films, and the like on the surface are removed by an arbitrary cleaning solution. Thereafter, a silicon oxide film 11 having a predetermined thickness, for example, 100 nm is formed on the surface of the silicon wafer 10. Further, a predetermined amount of boron ions (B ⁺ ) is implanted through the silicon oxide film 11 (FIG. 2A). After removing the oxide film 11, the tunnel oxide film 12 having a thickness of about 5 mm is formed.
Is formed (FIG. 2B).

Next, the wafer 10 is set in a reaction furnace,
A floating gate of a polysilicon film 13 is formed on the surface of the tunnel oxide film 12 by a low pressure CVD method. This polysilicon film 13 has a thickness of about 25 nm as shown in FIG.
A first region 131, a second region 132 having a thickness of about 50 nm,
It comprises a third region 133 having a thickness of about 25 nm, and a total of about 100
It has a thickness of nm. Then, the impurity concentration of the intermediate second region 132 is formed higher than the impurity concentration of the third region 133 and the deep first region 131 which form a shallow portion on the substrate. Here, the impurity is a donor impurity, for example, phosphorus (P) is used.

FIG. 6 is a flowchart showing a manufacturing process of the nonvolatile semiconductor memory device of the first embodiment. Steps P1 to P3
Are processes corresponding to FIGS. 1A to 1C, respectively, until the above-described three-layer polysilicon film 13 is formed. Step P4 is a step of forming the interlayer insulating film 14 and forming the control gate electrode 15. As shown in FIG. 7, the interlayer insulating film 14 is formed on the polysilicon film 13 with a thickness of about 15 nm, and the control gate electrode 15 is formed on the interlayer insulating film 14 by a predetermined thickness by an arbitrary method. Is formed as a polysilicon film. Step P5 is a step of forming a source region and a drain region of the nonvolatile semiconductor memory device. Here, a resist film is applied to the surface of the control gate electrode 15, exposed by a predetermined mask pattern, developed, and then processed by etching to remove unnecessary portions of the control gate electrode 1.
5. The interlayer insulating film 14, the polysilicon film 13, and the tunnel oxide film 12 are removed. Further, phosphorus (P) ions are implanted using the resist film as a mask, and the silicon wafer 1 is implanted.
A source region 16 and a drain region 17 are formed in 0. Step P6 is a step of removing the resist and annealing. After removing the resist film, annealing is performed at 900 ° C. for 30 minutes, for example, to complete a nonvolatile semiconductor memory device as shown in FIG. In FIG. 8, an electrode layer and the like are omitted.

When injecting and emitting electrons into the floating gate of the nonvolatile semiconductor memory device, the control gate electrode 15
A voltage of 3.3 V is applied between the semiconductor substrate 10 and the silicon substrate 10. At the time of implantation, the control gate electrode 15 is positively biased, and at the time of emission, the control gate electrode 15 is negatively biased.

FIG. 9 is a view for explaining a state change in the reaction furnace when the above-mentioned three-layer polysilicon film 13 is formed. A silicon hydride gas (monosilane: SiH
₄ ) and hydrogen phosphide gas (phosphine diluted to 1% with H ₂ : PH ₃ / H ₂ ) as source gas and impurity gas, and hydrogen gas (H ₂ ) as reducing gas for cleaning, respectively. The flow can be adjusted and supplied.

First, only hydrogen gas is supplied at 230 sccm (standard
The temperature inside the furnace is increased while supplying the wafer (cubic centimeter per minute). When the wafer temperature rises to 570 ° C. at time t ₁ , the temperature is maintained. Then, while maintaining the pressure in the reactor at 0.3 Torr, the source gas monosilane was 700 sccm, phosphine was 35 sccm, and hydrogen gas was 230 s.
Adjust to ccm and send. This results in a phosphorus concentration of about
0.9 × 10 ¹⁹ (/ cm ³ ) of the first region 131 is formed. For example, at time t ₂ , about 10 minutes later, the phosphine flow rate alone is increased to 135 sccm without changing other conditions.
In this state, it continued formation of the polysilicon film to the time t _3. As a result, the second phosphorous concentration of about 8 × 10 ¹⁹ (/ cm ³ )
An area is formed. This time (time between t ₂ and t ₃ ) is, for example, about twice the time for forming the first region, that is, about 20 minutes. Finally, control is returned only to 35sccm flow of phosphine without changing, continuing the formation of the polysilicon film to the time t ₄ in this state again other conditions. Thus, a third region having a phosphorus concentration of about 0.9 × 10 ¹⁹ (/ cm ³ ) is formed. Thereafter, the supply of the source gas monosilane and phosphine is stopped, the temperature in the furnace is lowered, and when the wafer temperature falls to 100 ° C., the wafer is taken out of the reaction furnace.

FIG. 10 is a diagram showing the distribution of the phosphorus concentration in the polysilicon film according to the present invention. The horizontal axis indicates the depth (nm) from the surface of the polysilicon film 13 constituting the floating gate, and the vertical axis indicates the phosphorus concentration (/ cm ³ ). This polysilicon film 13 changes the flow rate of phosphine flowing into the reaction furnace discontinuously between time t2 and time t3,
By changing the partial pressure ratio of impurities in the reactor,
The impurity concentration in the middle portion is formed higher than the impurity concentration in the shallow portion and the deep portion.

FIG. 11 is a diagram showing an energy band of a polysilicon film according to the present invention. Here, the bottom of the conduction band is lower in the central portion of the polysilicon film 13 than in other regions. In the conventional example, as shown in FIG. 12, since the energy band of the polysilicon film forming the floating gate is substantially horizontal, electrons injected there are likely to escape even if they are once accumulated. On the other hand, in the case of the present invention, as shown in FIG. 13, the electrons injected into the polysilicon film forming the floating gate enter the dent of the conduction band,
You can't get out of it easily. Therefore, the data retention characteristic of the nonvolatile semiconductor memory device can be improved by the floating gate thus formed. Practically, the impurity concentration in the middle portion of the polysilicon film 13 is set to 1 × 10 ¹⁹
If it is formed to a thickness of (/ cm ³ ) or more, it functions as a floating gate of a nonvolatile semiconductor memory device having an energy band with a depth at which electrons do not escape thermally. Then, the polysilicon film 1
3. The data retention characteristic of the nonvolatile semiconductor memory device is improved as compared with the conventional device by forming the ratio of the impurity concentration of the shallow portion to the deep portion to the impurity concentration of the intermediate portion to 2.7 or more. Is recognized.

V _t (t) -V shown by the solid line in FIG.
As can be seen from the small decrease in _t (0), the conventional E
The data retention characteristic is greatly improved as compared with the data retention characteristic of the EPROM.

Embodiment 2 FIG. In the second embodiment, as in the first embodiment, the inside of the reaction furnace is set so that the partial pressure ratio in the middle stage is relatively higher than the partial pressure ratio of impurities in the initial stage and the final stage of the floating gate forming process. The non-volatile semiconductor memory device is manufactured by switching the partial pressure ratio of the impurity of
At that time, the flow rate of the impurity gas flowing into the reaction furnace is continuously changed.

FIG. 14 is a view for explaining a state change in the reactor when a polysilicon film is formed in the second embodiment. As in the first embodiment, the reaction in the furnace silicon hydride gas (monosilane: SiH ₄₎ and phosphine gas (phosphine diluted to 1% H _2: PH ₃ / H ₂
) Is supplied as a source gas and an impurity gas, and a hydrogen gas (H ₂ ) is supplied as a reducing gas for cleaning at a predetermined flow rate.

[0033] First, with 230sccm supplying only hydrogen gas to increase the temperature in the furnace, the wafer temperature at time t ₅ is 570
When the temperature rises to ° C, the temperature is maintained. Thereafter, while keeping the pressure at 0.3 Toor, monosilane is fixed at 700 sccm and hydrogen gas is fixed at 230 sccm, and phosphine is fed at a rate of 5 sccm / min from 35 sccm into the reactor. In this state, it continued formation of the polysilicon film to the time t _6. Thereby, a polysilicon film phosphorus concentration is initially about 1 × 10 ¹⁹ of (/ cm ^3), then gradually the concentration becomes high, the time t ₆ for example after about 20 minutes the flow rate of phosphine 135sccm And the phosphorus concentration is about 1 × 10 ²⁰ (/ cm ³ )
Becomes Next, monosilane 700 sccm and hydrogen gas 230
With the sccm fixed, the phosphine flow rate is reduced from 135 sccm at 5 sccm per minute. In that state, at time t ₇
The formation of the polysilicon film is continued until this. As a result, the flow rate of the phosphine is reduced to 35 s at time t ₇ after about 20 minutes.
Return to ccm. Thus, a polysilicon film 13 having a thickness of about 100 nm is formed. Thereafter, the supply of the source gas monosilane and phosphine is stopped, the temperature in the furnace is lowered, and when the wafer temperature has dropped to 100 ° C., the wafer is taken out of the reaction furnace.

The subsequent steps of forming the interlayer insulating film 14 and forming the control gate electrode 15 are the same as in the first embodiment.

FIG. 15 is a diagram showing the distribution of the phosphorus concentration in the polysilicon film according to the second embodiment. The impurity concentration distribution inside the polysilicon film 13 is inverse V
It is shaped like a letter and peaks at the center in the thickness direction. For this reason, the same operation and effect as in the first embodiment are obtained as described later. Compared with the manufacturing method of the first embodiment, since the change in the phosphorus concentration is gentle, it is easy to control the gas flow rate in the reaction furnace.

FIG. 16 is a diagram showing an energy band of the polysilicon film according to the second embodiment. Here, the bottom of the conduction band at the central portion of the polysilicon film 13 is lower than other regions of the floating gate. Practically, the impurity concentration in the middle portion of the polysilicon film 13 is set to 1 × 10 ¹⁹ (/ cm ³ )
With the above structure, a floating gate having an energy band with a depth at which electrons do not escape thermally can be obtained. And
By forming the ratio between the impurity concentration of the intermediate portion of the polysilicon film 13 and the impurity concentration of the shallow portion and the deep portion to be 2.7 or more, data retention characteristics are improved as compared with the conventional device.

In each of the above embodiments, the flow rate of the phosphine as the impurity gas is changed in order to change the partial pressure ratio between the source gas and the impurity gas. However, the flow rate of the source gas may be changed.

In the above embodiment, a flash erase EEPROM of a batch erasing type has been described as a nonvolatile semiconductor memory device. However, a floating gate of an EPROM of an ultraviolet erasing type can be similarly formed.

[0039]

[0040]

According to the production method of the present invention, when stacking a polysilicon film on the tunnel oxide film, formed of an impurity concentration higher floating gates in the intermediate section while changing the partial pressure ratio of impurity gas By performing the film , data retention characteristics
It can be obtained sexual good nonvolatile semiconductor memory device.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a configuration of a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a schematic sectional view showing a nonvolatile semiconductor memory device having a channel injection structure.

FIG. 3 is a diagram showing an impurity concentration distribution in conventional polysilicon.

FIG. 4 is a diagram showing a conventional energy band.

FIG. 5 is a diagram showing data retention characteristics of the conventional EEPROM and the EEPROM of the present invention.

FIG. 6 is a flowchart showing a manufacturing process of the nonvolatile semiconductor memory device of the present invention.

FIG. 7 is a cross-sectional view showing a step of forming an interlayer insulating film and a step of forming a control gate electrode in a step P4.

FIG. 8 is a sectional view showing a completed nonvolatile semiconductor memory device.

FIG. 9 is a cross-sectional view illustrating a step of forming a polysilicon film of the first embodiment.
It is a figure explaining a state change in a reactor.

FIG. 10 is a diagram showing a distribution state of a phosphorus concentration in a polysilicon film according to the first embodiment.

FIG. 11 is a diagram illustrating an energy band according to the first embodiment.

FIG. 12 is an energy band diagram of a polysilicon film forming a conventional floating gate.

FIG. 13 is an energy band diagram of a polysilicon film forming the floating gate of the first embodiment.

FIG. 14 is a diagram illustrating a state change in a reaction furnace when forming a polysilicon film according to the second embodiment.

FIG. 15 is a diagram showing a distribution state of a phosphorus concentration in a polysilicon film according to a second embodiment.

FIG. 16 is a diagram illustrating an energy band according to the second embodiment.

[Description of Signs] 10 silicon wafer, 12 tunnel oxide film, 13
Polysilicon film, 131 first region, 132 second region, 133 third region.

Claims (3)

(57) [Claims] 1. A method for manufacturing a nonvolatile semiconductor memory device in which a polysilicon film containing a donor impurity is laminated on a tunnel oxide film to form a floating gate, wherein a source gas is formed at an initial stage and a final stage of the floating gate forming step. A method for manufacturing a non-volatile semiconductor memory device, comprising: changing a partial pressure ratio in a reaction furnace such that a partial pressure ratio of an impurity gas in a middle term becomes higher than a partial pressure ratio of an impurity gas with respect to the above. By wherein varying the flow rate of the impurity gas flowing into the reactor, a method of manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein changing the partial pressure ratio of the reaction furnace. 3. A process according to claim 2 the non-volatile semiconductor memory device, wherein the continuously changing the flow rate of the impurity gas flowing into the reactor.