JPH0974323A - Digital automatic gain control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital automatic gain control(AGC) circuit which has followup characteristics sufficient for instantaneous reception level fluctuation and can fix a reception level. SOLUTION: Concerning a circuit with which an error (a) of the output level of an AGC amplifier 11 is found by a means 14, a loop band coefficient μis multiplied to the error (a), the delayed error is added to this error by a means 16 after multiplication and the added error is transformed to a control voltage for controlling gain by a means 18, this circuit is provided with a means 23 for transforming a received envelope signal level into a digital value L1 and a means 24 connected between the means 16 and the means 19 so as to supply the L1 as a write/read address and to store a control voltage value A1 into the address of the Li so as to freely write/read it. The value A1 is read by the value L1 and the A1 is supplied through the means 23 to an amplifier 11. At such a time, the output error of the means 16 is controlled to be updated as the stored value A1 read out in advance until the output error of the means 14 becomes '0'.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital automatic gain control (AGC) circuit. This digital AGC circuit removes amplitude fluctuations due to fading and is used in radio communication devices and the like, and is particularly used in receivers in the mobile communication field where reception level fluctuations are severe due to fading.

In mobile communication, an equalizer, an interference canceller, etc. are required due to multipath, co-channel interference and the like. In order to maximize these capabilities, a high-speed digital AGC circuit capable of supplying a stable reception level is required.

[0003]

2. Description of the Related Art A circuit diagram of a conventional digital AGC circuit is shown in FIG. In FIG. 6, 1
1 is an AGC amplifier, 12 is a demodulator, 13 is an envelope detector, 14 is a subtractor, 15 is a multiplier, 16 is an adder, 17
Is a delay device such as a flip-flop, and 18 is a D / A converter.

The AGC amplifier 11 has a dynamic range of several tens of dB, and by changing the gain according to the control voltage output from the D / A converter 18, the received signal dropped to the base band is received. Make the amplitude constant.

The demodulator 12 extracts the in-phase component and the quadrature component by demodulating the signal output from the AGC amplifier 11 and outputs it. This becomes a complex signal. The envelope detector 13 extracts an envelope signal which is an envelope component from the complex signal.

The subtractor 14 calculates and outputs the error a by subtracting a reference value which is a predetermined level that is actually obtained from the envelope signal level. Multiplier 1
5 outputs the band of the feedback loop of the digital AGC circuit, that is, the coefficient μ that determines the loop band and the error a. Here, if μ is increased, the error a
Is output from the multiplier 15 almost as it is, so that a quick response of the feedback loop is possible. However, the operation becomes unstable. When μ is reduced, the response becomes slower but stable operation is achieved. μ is a number of 1 or less.

The adder 16 adds the error output from the adder 16 delayed by the delay device 17 once. Here, the error is gradually integrated. D /
The A converter 18 converts the error output from the adder 16 into a voltage, that is, a gain control voltage, and outputs the voltage to the AGC amplifier 11.

In addition, the error is gradually accumulated in the adder 16 because the error a becomes smaller than the original error when the error a is multiplied by μ, so the error is gradually added so that the original error is obtained. This is because the error a in the output of the subtractor 14 is zero.

In such a configuration, the smaller the value of μ, the longer the integration time in the adder 16, but the stable operation of the AGC amplifier 11 can be obtained even if a large disturbance is introduced.

[0010]

By the way, in the above-mentioned conventional digital AGC circuit, the ability to follow the gentle fluctuation of the reception level due to the distance is sufficient, but the ability to follow the instantaneous fluctuation due to fading is inferior.
There is a problem that the level changes even after the control by the AGC.

For example, in mobile communication, there is a fluctuation of 50 to 60 dB in a place having a large dynamic range, and it is necessary to always follow the fluctuation. Therefore, if μ is increased and the loop band is widened, tracking will be faster,
When extreme fluctuations are introduced, overshoot, that is, tracking is lost, or the error a cannot be brought close to zero. Also, μ
This is because if is smaller, stable operation is achieved, but rapid fluctuation cannot be followed.

The present invention has been made in view of the above circumstances, and provides a digital automatic gain control circuit which has a sufficient follow-up characteristic to the instantaneous reception level fluctuation and can keep the reception level constant. It is intended to be provided.

[0013]

FIG. 1 shows the principle of a digital automatic gain control circuit according to the present invention. The digital automatic gain control circuit shown in FIG. 1 obtains the error a between the output signal level of the AGC amplifier 11 whose gain is controlled so that the level of the received signal is constant and the reference value by the subtracting means 14, and the error a Is multiplied by a coefficient μ that determines the loop band, and the error after the multiplication is delayed by the error to adder 16
And the error after the addition is added by the D / A conversion means 18
Is supplied to the AGC amplifier 11 after being converted into a control voltage for controlling the gain.

A feature of the present invention is that an A / D for converting a reception envelope signal level corresponding to a reception signal into a digital value L1.
A value A1 which is connected between the converting means 23, the adding means 16 and the D / A converting means 18, is supplied with a digital value L1 as a write / read address, and becomes the control voltage at the address specified by the digital value L1. Is provided with a storage means 24 for freely writing / reading.

Then, the stored value A1 in the storage means 24 is read by the digital value L1 and the stored value A1 is D / A.
The AGC amplifier 11 is used as a control voltage via the conversion means 23.
The error output from the adding means 16 at the time of this supply is updated as the previously read storage value A1 until the error output from the subtracting means 14 becomes zero.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a circuit diagram showing the configuration of the digital AGC circuit according to the first embodiment of the present invention. In this figure, parts corresponding to parts of the conventional example shown in FIG. 6 are denoted by the same reference numerals, and description thereof will be omitted.

In FIG. 2, the newly provided elements are
Delay devices 21 and 22, A / D converter 23, DPRAM
(Dual port RAM) 24. The digital AGC circuit of the first embodiment pays attention to the fact that if the reception level is known, the gain of the AGC amplifier 11 is determined 1 to 1 and the estimation is performed several times. A control voltage value for setting the AGC amplifier 11 to a target gain value is stored in the DPRAM 24, and this stored control voltage value is stored in the DPRAM 24 via the D / A converter 18.
It is configured so that a desired gain can be instantly obtained by supplying it to the GC amplifier 11.

The A / D converter 23 converts the received envelope signal level corresponding to the received signal into a digital value, which is D
It is supplied as a read address of the PRAM 24 and is also supplied as a write address via the delay device 22.

The control voltage values stored in the DPRAM 24 are 10 (A1 to A1) if the reception level has 10 levels.
0) is necessary, and this is stored for each storage area of the reception envelope signal levels L1 to L10 which are addresses.

The delay devices 21 and 22 are the DPRAM 2
4, for example, the gain of the AGC amplifier 11 is determined by the control voltage value A1 read from the storage area of the first address.
This is to delay the writing control by one step in order to newly store the control voltage value A1 in the address storage area.

In such a configuration, for example, the control voltage value A1 stored in the storage area of the address indicated by the reception envelope signal level L1 is read from the DPRAM 24,
This control voltage value A1 is passed through the D / A converter 18 to the AGC
If it is supplied to the amplifier 11 and the gain is set,
The error a in this case is fed back, and the DPRAM2
4 is newly written as a control voltage value A1 in the storage area of the address indicated by level L1. That is, the control voltage value A1 is updated.

This update is performed until the error a finally becomes zero. This is the DPR when the error a becomes 0.
This is because the control voltage value A1 of the AM 24 converges to a constant value. If the control voltage value A1 stored in the DPRAM 24 is used when the reception envelope signal level L1 comes after this convergence, the gain can be instantly set to the target value. Therefore, it is possible to stably follow the instantaneous fluctuation due to fading.

Next, a second embodiment will be described with reference to FIG. However, in FIG. 3, parts corresponding to the respective parts of the first embodiment shown in FIG. 2 are designated by the same reference numerals, and description thereof will be omitted.

The second embodiment shown in FIG. 3 is different from the first embodiment shown in FIG. 2 in that a feedback loop is constituted only by the reception envelope signal level, and the control voltage value obtained here is used as an AGC amplifier. 11 is to be supplied.

That is, as shown in FIG. 3, except for the envelope detector 13 shown in FIG. 2, the DPRAM from the digital reception envelope signal level L output from the A / D converter 23.
The control voltage value output from 24 is subtracted, and the subtraction result is output to the subtractor 14.

In the case of the second embodiment, the same effect as that of the first embodiment can be obtained, and since the envelope detector 13 having a large circuit scale does not have to be used, the entire circuit can be reduced accordingly. It will be possible.

Next, a third embodiment will be described with reference to FIG. However, in FIG. 4, the portions corresponding to the respective portions of the first and second embodiments shown in FIGS. 2 and 3 are denoted by the same reference numerals, and the description thereof will be omitted.

The third embodiment shown in FIG. 4 is shown in FIGS.
AGC amplifier 1 used in the first and second embodiments shown in FIG.
1, a demodulator 12, a D / A converter 18, and an A / D converter 23, and a ROM 28.

In the ROM 28, the converged control voltage values A1 to A10 stored in the DPRAM 24 described in the first and second embodiments are stored in advance. In this way, it operates as a feedforward AGC.

If the configuration of the receiver at the stage prior to the AGC loop is known, it is possible to preliminarily determine the storage value of the ROM 28 by a test. In the case of the third embodiment, the same effects as those of the first and second embodiments can be obtained.

Further, FIG. 5 shows a simulation result of AGC characteristics by the digital AGC circuits of the above-described first to third embodiments. In FIG. 5, reference numeral 30 is a reception envelope signal level curve, 31 is an AGC characteristic curve obtained by control of a conventional digital AGC circuit, and 32 is first to third.
6 is an AGC characteristic curve obtained by controlling the digital AGC circuit of the embodiment. As evident from this result,
In the circuit of this embodiment, the reception level is controlled to be constant.

[0032]

As described above, according to the digital AGC circuit of the present invention, it has a sufficient tracking characteristic to the instantaneous reception level fluctuation, so that the reception level fluctuation due to fading is immediately tracked. There is an effect that the reception level can be made constant.

Therefore, an equalizer required for mobile communication,
There is an effect that the ability of the interference canceller or the like can be effectively exhibited.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a digital AGC according to the first embodiment of the present invention.
FIG. 3 is a circuit diagram illustrating a configuration of a circuit.

FIG. 3 is a digital AGC according to a second embodiment of the present invention.
FIG. 3 is a circuit diagram illustrating a configuration of a circuit.

FIG. 4 is a digital AGC according to a third embodiment of the present invention.
FIG. 3 is a circuit diagram illustrating a configuration of a circuit.

FIG. 5 is a diagram showing AGC characteristics of the circuits of the first to third embodiments and the conventional circuit.

FIG. 6 is a circuit diagram showing a configuration of a conventional digital AGC circuit.

[Explanation of symbols]

 11 AGC amplifier 14 subtraction means 16 addition means 18 D / A conversion means 23 A / D conversion means 24 storage means L1 converted digital value of reception envelope signal level A1 stored value which becomes AGC amplifier gain control voltage

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazuo Hase 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor, Kiharu Tajima 1015, Kamedotachu, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited ( 72) Inventor Hidenobu Fukumasa 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Fujitsu Limited

Claims (5)

[Claims] 1. An error between an output signal level of an AGC amplifier whose gain is controlled so that a received signal level is constant and a reference value is obtained by subtracting means, and the error is multiplied by a coefficient μ that defines a loop band. A digital signal obtained by adding the delayed error to the error after the multiplication is added by the addition means, and the error after the addition is converted into a control voltage for controlling the gain by the D / A conversion means and supplied to the AGC amplifier. In the automatic gain control circuit, an A / D conversion unit that converts the reception envelope signal level corresponding to the reception signal into a digital value, and the digital value is connected between the addition unit and the D / A conversion unit. Storage means that is supplied as a read / write address and in which the value to be the control voltage is stored in the address designated by the digital value in a write / read manner. The stored value of the storage means is read out according to the Tal value, the stored value is supplied to the AGC amplifier as the control voltage via the D / A conversion means, and the error output from the addition means at the time of this supply is supplied first. A digital automatic gain control circuit, characterized in that control for updating as a read storage value is performed until an error output from the subtraction means becomes zero. 2. An output signal of the AGC amplifier is converted into an in-phase signal and a quadrature signal by a demodulation means, the converted in-phase signal and a quadrature signal are converted into an envelope signal by an envelope detection means, and this conversion is performed. 2. The digital automatic gain control circuit according to claim 1, wherein the subtraction means calculates an error between the envelope signal level thus generated and the reference value. 3. The difference between the digital value and the stored value is obtained, and the difference is input to the subtracting means instead of the output signal level of the AGC amplifier. Digital automatic gain control circuit. 4. A dual port RAM in the storage means
2. The digital automatic gain control circuit according to claim 1, wherein: 5. A read-only storage means for storing a storage value of the storage means at the time when the error output from the subtraction means becomes 0, and the read-only storage is provided in place of the storage area means. 2. The digital automatic gain control circuit according to claim 1, wherein the gain is controlled by using a stored value of the means.