JPH0973783A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a supply current and to reduce power consumption by sharing a transistor for clock selection signal input in plural word recording parts to decrease the number of transistors to be driven by a clock selection signal. SOLUTION: When a clock selection signal CLKSEL becomes a low level, a transistor MP100 is turned ON. At this time, when an address selection signal ADDSEL-1 becomes a high level, the transistor MP200 of a word recording part 710-1 is turned ON and the transistor MN200 of the part is turned OFF. Consequently, a node N100 becomes a high level and the level is amplified in transistors MP300, MN300 and MP400, MN400 consisting of an inverter to make a word line WD1 a high level to be selected. At this time, word lines WD2-32 become low levels. Thus, charging and discharging currents are reduced and a selection speed is made high-speed by decreasing the number of transistors while sharing the transistor for clock selection signal input in such a manner.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a word decoder for selecting a word line according to the logic of an address selection signal and a clock selection signal.

In recent years, semiconductor memory circuits have been required to have large scale, high integration, high speed, and low power consumption. Particularly, in order to achieve both high speed and low power, the internal synchronous operation is effective. For example, in SRAM and the like, a method of limiting the selection period of the word line and reducing the through current has been used. However, reducing the number of constituent elements is the most effective means for speeding up and lowering the power consumption, and it is necessary to reduce the number of constituent elements in order to realize the higher speed and lower power consumption.

In recent years, local interconnect (local wiring) technology, self-aligned contact technology and the like have been developed as highly integrated technology, and have greatly contributed to the reduction in size of memory cells. Along with the reduction in the size of memory cells, it is necessary to reduce the size of peripheral circuits.

[0004]

2. Description of the Related Art FIG. 5 shows a block diagram of an SRAM. The SRAM 10 mainly includes a clock enable buffer 100 that converts the clock CLK into a signal level used internally, and address buffers 200 to 24 that convert the row addresses X0 to X4 into a signal level used internally.
0, address buffers 300 to 320 for converting column addresses Y0 to Y2 into signal levels used internally, and write to convert a write enable signal for distinguishing between writing and reading of data into a signal level used internally. Enable buffer 400, address buffer 2
A 1/32 predecoder 500 that generates an address selection signal that selects a word line from a row address that is level-converted at 00 to 240, and a data selection signal that selects a data line from a column address that is level-converted at address buffers 300 to 320 1/8 predecoder 60 for generating
A word decoder 700 and a word decoder 700 that select a word line according to the output of the logic of the address selection signal generated by the 0, 1/32 predecoder 500 and the clock level-converted by the clock enable buffer 100.
A cell array 800 and a 1/8 predecoder 600 capable of writing and reading information to and from the word line selected by
A column decoder 900 that selects a bit line according to the data selection signal generated in step S1 and outputs it to the data bus line, and a sense amplifier 1000 and a sense amplifier 100 that amplify the signal of the data bus line output from the column decoder 900.
A data output buffer 1100 for converting a signal amplified by 0 to an external signal level, a write amplifier 1200 for amplifying a write signal, and a data input buffer 1300 for converting write data to a signal level used internally.

FIG. 6 shows an operation waveform diagram of main nodes of the SRAM. (A) shows the address buffers 200 to 240,
Addresses X0 to X4, Y0 supplied to 300 to 320
~ Y2 timing, (B) shows the clock buffer 10
The waveform of the clock CLOCK supplied to 0, (C) is
The waveform of the write enable signal supplied to the write enable buffer 400, (D) is the data input buffer 1
The waveform of the signal supplied to 300, (E) is the node N2
01 data supply timing, (F) indicates node N2
02 waveform, (G) timing of data supply to the node N601, (H) waveform of the node N401, (I).
Is the waveform of the node N801, and (J) is the node N901.
Waveform (H) indicates the output timing of the data buffer 1100.

The word decoder 700 is shown in FIG. 6 (F) during the high level period of the clock CLOCK shown in FIG. 6 (B).
The word line is made selectable as shown in FIG. FIG. 7 shows a block diagram of a conventional word decoder 700. The conventional word decoder has 32 output address selection signals ADDSEL1 to ADDSEL3 of the 1/32 predecoder 500.
32 word decoding units 750-1 to which 2 is supplied
750-32.

Word decoding units 750-1 to 750-3
2 is P-channel transistors MP150, MP25
0, MP350, MP450, N-channel transistors MN150, MN250, MN350, MN450. P-channel transistor MP150, MP
250, N-channel transistors MN150, MN25
0 constitutes a NOR logic circuit, and the transistor M
A clock selection signal is supplied from the clock buffer 100 to the gates of P150 and MN150, and an address selection signal is supplied from the 1/32 predecoder 500 to the gates of the transistors MP250 and MN250. The NOR logic of is output. Further, the transistors MP350, MN350, the transistors MP450, MN450 are configured by connecting inverters in two stages, and the transistors MP150, MN150, MP250, M forming a NOR logic circuit.
Amplify the NOR logic output of N250 to amplify the word lines WD1 to WD1.
A word driver supplied to the WD 32 is configured.

Word decoding units 750-1 to 750-3
A clock signal which is periodically inverted is supplied to 2, and 32 address selection signals are supplied. The address selection signal is set to select the word line when it is at the low level, and one of the 32 address selection signals is set to the low level according to the address. The clock selection signal is the clock C in FIG.
It has a logic that inverts LOCK, and is set so that the word line can be selected at the low level.

Word decoding units 750-1 to 750-3
In No. 2, when the clock selection signal is at the low level and the address selection signal is at the low level, that is, when the word line is selected, the node 150 becomes the high level and the word line W
D is set to a high level, that is, data can be written in or read from the cell. In addition, the word decoding units 750-1 to 750-32 have the node 150 when the clock selection signal is at the low level and the address selection signal is at the high level, that is, when the word line is not selected.
Goes low and the word line WD goes low.
Furthermore, word decoding units 750-1 to 750-32
When the clock selection signal is at the high level, that is, when the word line is not selected, the node 150 is at the low level and the word line WD is at the low level.

As described above, in the conventional semiconductor memory device,
The clock selection signal had to drive each of the 32 word decoding units.

[0011]

However, in the conventional semiconductor memory device, each of the 32 word decoders is provided with a clock selection signal input transistor.
Since the clock selection signal needs to turn on the 64 transistors of 32 clock selection signal input transistors and 32 NOR logic output transistors at the same time, the load on the clock selection signal becomes large. The current consumption of the signal input transistor is large, which is an obstacle to lowering the power consumption. Further, since the clock selection signal is distributed to a large number of clock selection signal input transistors, if one tries to increase the operating speed of the clock selection signal input transistors,
There has been a problem that the driving current needs to be greatly increased and the power consumption is greatly increased.

Further, in the case of high integration of cells using a local interconnect (local wiring) technique or a self-alignment technique in a semiconductor memory device, it is necessary to lay out circuits around the cell array at the same pitch as the cells. In the conventional semiconductor memory device, since the number of elements of the peripheral circuit such as the word decoder is large, the peripheral circuit portion is enlarged and the performance is deteriorated. Therefore, it has been difficult to achieve high integration using the local interconnect (local wiring) technology or the self-alignment technology.

The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor memory circuit capable of reducing power consumption, speeding up, and high integration.

[0014]

According to a first aspect of the present invention, there is provided a clock selection signal input transistor for inputting a clock selection signal for setting a word line selection period, an address selection signal for setting a word line to be selected, and the transistor. In a semiconductor memory device having the word selection unit supplied with the clock selection signal via a transistor for inputting a clock selection signal and selecting a word line according to the address selection signal and the clock selection signal, the clock selection signal input The feature transistor is shared by a plurality of word decoding units.

According to the first aspect of the present invention, the number of transistors to be driven by the clock selection signal can be reduced by sharing the clock selection signal input transistor in the plurality of word decoding units, so that the clock selection signal is supplied. Therefore, the current consumption can be reduced, and therefore the power consumption of the semiconductor memory device can be reduced. Moreover, when the word decoder is driven by the clock selection signal as in the conventional case, the driving current can be made large, so that the transistor The operation speed can be increased and the word line selection speed can be improved.

According to a second aspect of the present invention, the element for outputting the logic of the address selection signal and the clock selection signal in the word decoding section includes a resistance element or a resistance element. According to the second aspect, since the element that outputs the logic of the address selection signal and the clock selection signal of the word line is configured by the resistance element, the capacitance added to the output can be reduced, so that the signal can be output at high speed. You can do it.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION This embodiment is characterized by the structure of a word decoder 700 of a semiconductor memory device shown in FIG. 5, and since the other parts are the same, the structure of the word decoder 700 will be described and the other parts will be described. Is omitted.

FIG. 1 is a circuit diagram of the word decoder of the first embodiment of the present invention. The word decoder 70 of this embodiment
0 indicates to the 32 word lines WD1 to WD32 according to the logic of the clock selection signal input transistor MP100 for inputting the clock selection signal and the address selection signal and the clock selection signal input transistor MP100. 32 word decoding units 710-1 to 710-32 for supplying word line selection signals
It is composed of

Clock selection signal input transistor MP
Reference numeral 100 denotes a P-channel type transistor, the source and drain of which are connected between the drive voltage Vdd and the plurality of word decoding units 710-1 to 710-N, and the gate of the clock selection signal / CLK from the clock buffer 100.
SEL is supplied. The clock selection signal input transistor MP100 is turned on when the clock selection signal / CLKSEL is at a low level, that is, when the word line is selected, and the drive voltage Vdd is set to 32 word decoding units 710.
-1 to 710-32, clock selection signal / CL
When KSEL is at a high level, that is, when the word line is not selected, it is turned off and the supply of the drive voltage Vdd to the 32 word decoding units 710-1 to 710-32 is stopped.

32 word decoding units 710-1 to 71-7
10-32 are P-channel type transistors MP, respectively
200, MP300, MP400, and N-channel type transistors MN100, MN200, MN300, M
It consists of N400. Transistor MP200, M
The N100 and MN200 form a NOR logic circuit together with the clock selection signal input transistor MP100. The gates of the transistors MP200 and MN200 receive the address selection signal / A from the 1/32 predecoder 500.
DDSEL is supplied and clock selection signal / CLKSE
NOR logic of L and the address selection signal / ADDSEL is the drain of the transistor MP200 and the transistor MN.
100, output from the connection point with the drain of MN200.

The transistors MP300 and MN30 are also included.
0, the transistors MP400 and MN400 are the transistors MP300 and MN300, and the transistor MP.
400 and MN400 are respectively connected in series between the drive voltage Vdd and the ground to form an inverter. This 2
Clock selection signal / CLKSEL
And a word driver for amplifying the NOR logic of the address selection signal / ADDSEL and supplying it to the word lines WD1 to WD32. Transistors MP300, MN3
The gate of 00 is connected to the connection point between the drain of the transistor MP200 and the drains of the transistors MN100 and MN200, and the logic obtained by inverting the NOR logic of the clock selection signal / CLKSEL and the address selection signal / ADDSEL is applied to the drain of the transistor MP300 and the transistor. Output from the connection point with the drain of MN300. The gates of the transistors MN400 and MP400 are the drain of the transistor MP300 and the transistor MN300.
Of the clock selection signal / CLKSEL and the address selection signal / ADDSEL.
The inverted NOR logic of and is output from the connection point between the drain of the transistor MN400 and the drain of the transistor MP400.

The connection point between the drain of the transistor MN400 and the drain of the transistor MP400 is connected to the word lines WD1 to WD32, and the word line WD1 is generated according to the NOR logic of the clock selection signal / CLKSEL and the address selection signal / ADDSEL. To WD32 are set to high level or low level and the word lines WD1 to WD are set.
32 is selected or is in a non-selected state. At this time, only one of the 32 word lines WD1 to WD32 is selected and the other 31 word lines are deselected by the address selection signal / ADDSEL.

Next, the operation of this embodiment will be described. When the clock selection signal goes low, the transistor MP1
00 turns on and transistor MN100 turns off. At this time, for example, the address selection signal / ADDS
When the address selection signal / ADDSEL-1 of EL-1 to / ADDSEL-32 goes high, the transistor MP200 of the word decoding unit 710-1 turns on and the transistor MN200 turns off. When the transistor MP200 is turned on and the transistor MN200 is turned off, the node N100 becomes high level and the word line W
D1 goes high, and the word line WD1 is selected.

At this time, the address selection signal / AD
Since DSEL-2 to / ADDSEL-N are at a high level, the transistor MP200 of the word decoding units 710-2 to 710-N is turned off and the transistor MN is turned on.
Since 200 is turned on, the node N100 becomes low level and the word decoding units 710-2 to 710-N.
The word lines WD2 to WD32 connected to are held at a low level.

According to this embodiment, the clock selection signal / C
The transistor MP100 to which LKSEL is supplied is set to 32.
Since the word decoding units 710-1 to 710-32 are commonly used, the number of transistors to be driven by the clock selection signal / CLKSEL can be reduced to about half of the conventional one. Therefore, the clock selection signal /
Since the load of the CLKSEL transistor can be reduced and the charge / discharge current in the transistor can be reduced, constant power can be realized. In addition, clock selection signal / CLKSEL
If the load of 1 is the same as the conventional one, the transistor MP100 that is turned on by the clock selection signal can be designed to be a large transistor, so that the drive current driven by the transistor MP1 can be increased. Therefore, the drive currents of the word decoding units 710-1 to 710-32 can be increased, and therefore the word decoding units 710-1 to 710-32.
Can be improved, and the selection speed of the word lines WD1 to WD32 can be increased.

FIG. 2 is a circuit diagram showing the essential parts of the second embodiment of the present invention. In the figure, the same components as those of FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. The present embodiment differs from the first embodiment in the configuration of the word decoding section. In the word decoding units 720-1 to 720-32 of the present embodiment, the transistor MN100, which constitutes the NOR logic circuit together with the transistor MP100 in the first embodiment, is constituted by the resistance element R.

The resistance element R is a transistor MP100,
The resistance value is set to be sufficiently larger than the ON resistance of the series circuit of the MP200, and has a current driving capability capable of completely setting the node 100 to the low level when the clock selection signal / CLKSEL is in the non-selected high level. . As described above, by using the resistance element R in place of the transistor MN100, the number of transistors connected to the node 100 can be reduced, so that the parasitic capacitance connected to the node 100 can be reduced and the node 100 The signal rise can be performed at high speed, and selection can be performed at high speed.

Further, the number of transistors to be driven by the clock selection signal / CLKSEL can be reduced to 1/32 of that of the conventional transistor, so that the charge / discharge current can be further reduced. FIG. 3 shows a circuit configuration diagram of a main part of a third embodiment of the present invention. In the figure, the same components as those in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted.

In this embodiment, the NOR logic circuit of the first embodiment is configured by a NAND logic circuit, and the logic of selection / non-selection of the clock selection signal and the address selection signal is inverted from that of the first embodiment, and a high level is obtained. Selected at, low level made unselected. Therefore, the clock selection signal input transistor MN110 is composed of an N-channel type transistor, the source and drain of which are connected between the ground and the plurality of word decoding units 730-1 to 730-N, and the gate of which is the clock buffer 100. Clock selection signal CLKS
EL is supplied. The clock selection signal input transistor MN110 turns on when the clock selection signal CLKSEL is at a high level, and a plurality of word decoding units 730-
1 to 730-32 are grounded, and clock selection signal CLK
When SEL is at low level, it is turned off to disconnect the 32 word decoding units 730-1 to 730-32 from the ground.

32 word decoding units 730-1 to 73
30-32 are P-channel type transistors MP210,
MP310 and N-channel type transistor MN21
0, MN310, and P-channel type transistor MP
110 is used. Transistors MN210, M
P110 and MP210 form a NAND logic circuit together with the clock selection signal input transistor MN110. An address selection signal AD is supplied from the 1/32 predecoder 500 to the gates of the transistors MN210 and MP210.
DSEL-1 to ADDSEL-32 are supplied, and the NAND logic of the clock selection signal and the address selection signal is the drain of the transistor MN210 and the transistor MP11.
0, output from the connection point with the drain of MP210.

Next, the operation of this embodiment will be described. When the clock selection signal goes high, the transistor MN1
10 turns on and transistor MP110 turns off. At this time, the address selection signals ADDSEL-1 ...
Address selection signal ADDSE of ADDSEL-32
When L-1 goes high, the word decoding unit 710
−1 transistor MN210 turns on and transistor MP210 turns off. When the transistor MN210 turns on and the transistor MP210 turns off, the node N
100 goes low, word line WD1 goes high, and word line WD100 is selected.

At this time, the address selection signal ADD
Since SEL-2 to ADDSEL-32 are at low level, the transistor MP210 of the word decoding units 710-2 to 710-N is turned off, and the transistor MN2.
Since 10 is turned on, the node N100 becomes high level and the word decoding units 710-2 to 710-32.
The word lines WD2 to WD32 connected to are held at a low level.

FIG. 4 is a circuit diagram of the essential parts of the fourth embodiment of the present invention. In the figure, the same components as those of FIG. 3 are designated by the same reference numerals, and the description thereof will be omitted. The present embodiment differs from the third embodiment in the configuration of the word decoding section. In the word decoding units 740-1 to 740-32 of the present embodiment, the transistor MP110, which constitutes the NAND logic circuit together with the transistor MN110 in the first embodiment, is constituted by the resistance element R.

The resistance element R is a transistor MN110,
Set to a resistance value that is sufficiently larger than the on resistance of the series circuit of the MN210, and has a current driving capability that can bring the node 110 to a completely low level when the clock selection signal CLKSEL is at a high level and the address selection signal is at a low level. Has been done. Thus, the transistor MP110
By using the resistance element R in place of
Since the number of transistors connected to the node 110 can be reduced, the parasitic capacitance connected to the node 110 can be reduced, and the signal of the node 110 can rise at high speed.
The selection can be performed at high speed. Moreover, since the number of transistors to be driven can be reduced by the clock selection signal CLKSEL, the charge / discharge current can be further reduced.

In the first to fourth embodiments, the SR
An example in which the present invention is applied to an AM word decoder has been described, but the present invention is not limited to this, and a semiconductor memory device having a word decoder that limits a selection period by a clock can be applied. Also, in the above embodiment, the number of word lines is three.
Although an example of a semiconductor memory device having two cell arrays has been described, the number of word lines is not limited to this, and the present invention can be applied if the number of word lines is two or more. You can

Further, in the present embodiment, 32 word decoding sections share one clock selection signal input transistor, but some clock selection signal input transistors are provided and several clock selection signal input transistors are provided. A configuration may be considered in which the word decoding unit is divided and shared by the use transistors.

[0037]

As described above, according to the first aspect of the present invention, the number of transistors to be driven by the clock selection signal is reduced by sharing the clock selection signal input transistor in the plurality of word decoding units. Therefore, the current that the clock selection signal should supply can be reduced,
Therefore, the power consumption of the semiconductor memory device can be reduced, and when the word decoder is driven by the clock selection signal which is the same as the conventional one, a large drive current can be obtained, so that the operating speed of the transistor can be increased. It has the feature that the word line selection speed can be improved.

According to the second aspect of the present invention, since the element that outputs the logic of the address selection signal and the clock selection signal of the word line is composed of the resistance element, the capacity added to the output can be reduced, so that the signal output. It has a feature that it can be performed at high speed and the word line can be selected at high speed.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a main part of a first embodiment of the present invention.

FIG. 2 is a circuit configuration diagram of a main part of a second embodiment of the present invention.

FIG. 3 is a circuit configuration diagram of a main part of a third embodiment of the present invention.

FIG. 4 is a circuit configuration diagram of a main part of a fourth embodiment of the present invention.

FIG. 5 is a block diagram of an SRAM.

FIG. 6 is an operation waveform diagram of main nodes of the SRAM.

FIG. 7 is a configuration diagram of a main part of a conventional example.

[Explanation of symbols]

100 clock buffer 200 to 240, 300 to 320 address buffer 400 write enable buffer 500 1/32 predecoder 600 1/8 decoder 700 word decoder 710-1 to 710-32 word decode section 800 cell array 900 column decoder 1000 sense amplifier 1100 data Output buffer 1200 Write amplifier 1300 Data input buffer MP100, MN110 Clock selection signal input transistor R resistance / ADDSEL, ADDSEL address selection signal / CKLSEL, CKLSEL clock selection signal

Claims (2)

[Claims] 1. A clock selection signal input transistor for inputting a clock selection signal for setting a word line selection period, an address selection signal for setting a word line to be selected, and the clock selection signal via the clock selection signal input transistor. In a semiconductor memory device which is supplied with a signal and has a word decoding section for selecting a word line in accordance with the address selection signal and the clock selection signal, the clock selection signal input transistor is shared by a plurality of word decoding sections. A semiconductor memory device characterized by: 2. The word decoding unit is configured to include a resistance element or a resistance element as an element that outputs logic of an address selection signal and a clock selection signal of the word line. Semiconductor memory device.