JP3133847B2 - Semiconductor memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory, and more particularly to a technique effective for shortening a cycle time.

[0002]

2. Description of the Related Art In a semiconductor memory, when writing data, an address signal for specifying an address to be written, a data input signal for specifying data to be written, and a write pulse for enabling writing are applied. Generally, a write pulse must have a predetermined pulse width determined by the response characteristics of a memory cell array, and must be applied to an address signal and a data input signal while securing a predetermined setup time and hold time. . These timing conditions with respect to the write pulse are becoming increasingly severe with the speeding up of the semiconductor memory, and are the most important factor preventing the speeding up of the cycle time. On the other hand, the wiring between the logic LSI that generates the write pulse and the memory LSI has large parasitic capacitance and parasitic inductance. Therefore, the write pulse formed by the logic LSI is delayed by these parasitic capacitances and the like, and its waveform is deformed. For this reason, it is becoming difficult to form a write pulse that satisfies the strict timing conditions described above outside the memory LSI. Therefore, as a method of solving this problem, a write pulse generation circuit is provided inside the memory LSI, and the memory L is synchronized with a clock signal.
There is a method of generating a write pulse inside the SI. According to this method, writing can be performed stably and at high speed without being affected by the wiring capacitance and the parasitic inductance between the logic LSI and the memory LSI, and the cycle time can be shortened. An example of a prior art in which a write pulse generation circuit is provided inside a memory LSI is disclosed in Japanese Patent Application Laid-Open No. 63-308789.

[0003]

In the prior art, the write pulse generating circuit (hereinafter abbreviated as WPG) is constituted by a normal logic circuit. On the other hand, in the example a bipolar memory cell, SBD (S chottky B arrier D iode), pnp transistors, very high resistance element of sheet resistance, such as fine transistors, a normal logic circuit contains elements that are not used. Further, the circuit configuration of the write circuit for driving the memory cell array is different from a normal logic circuit. Therefore, when the element characteristics fluctuate due to manufacturing variations, the fluctuations in the circuit characteristics of the WPG and the fluctuations in the response characteristics of the memory cell array are completely different. For example,
Even if the junction capacitance of the SBD increases and the inversion time of the memory cell increases, the pulse width of the write pulse generated by WPG does not change. For this reason, in the prior art, a margin is given to the pulse width of the write pulse, the setup time, and the hold time in consideration of the change in the response characteristics of the memory cell array due to the change in the element characteristics in advance. The size of the timing margin will be described with reference to FIG. For example, due to variations in the characteristics of the elements constituting the memory cell,
It is assumed that the time trev from the start of writing until the information of the memory cell is inverted fluctuates by ± 30%. It is also assumed that the pulse width tw of the write pulse generated by the WPG fluctuates by ± 20% due to variations in the characteristics of the elements constituting the logic circuit. In the prior art, since the constituent elements and the circuit configuration of the WPG and the memory cell are completely different, trev and tw can be changed completely independently. For this reason, a case may occur where trev increases by 30% (point A) and tw decreases by 20% (point B). Therefore, in order to design a WPG so that writing can be performed no matter how the element characteristics fluctuate, the design center value tw (typ) of tw and the center value trev (typ) of trev
As shown in FIG. 4, it is necessary to satisfy the relationship of 0.8 tw (typ)> 1.3 trev (typ) ∴tw (typ)> 1.625 trev (typ). That is, tw (typ) needs to be designed to be 62.5% larger than trev (typ), even though trev varies only 30%. The setup time and the hold time also need to have a considerably large timing margin, which is an obstacle to further shortening the write cycle time. An object of the present invention is to provide a semiconductor memory which can reduce the above-mentioned timing margin and can operate at high speed.

[0004]

In order to achieve the above-mentioned object, according to the present invention, for example, as shown in FIG. 1 or FIG.
The memory cells arranged in a lattice (for example, memory cells included in the RAM in FIG. 1, for example, each cell of C0... Cn in FIG. 2) and a clock signal CLK and a write control signal R / W from outside are received. In a semiconductor memory having a write pulse generation circuit WPG for generating a write pulse WE, and a write circuit for receiving the write pulse WE and a data input signal and writing data to the memory cell, the write pulse generation circuit WPG includes: The memory cell has a write port WP and a read port RP, and has at least a dual-port memory cell DPC (hereinafter simply referred to as a dual-port cell) having the same configuration as the memory cell, for example, C0 in FIG. (Dummy memory cell) and the write port W
A write circuit DW for providing a write output to P and a pulse generating circuit PG for obtaining an output from the read port RP and generating the write pulse WE are provided.

Here, the write port, that is, a write circuit for giving a write output to, for example, WP in FIG. 2, for example, a circuit including a dummy write amplifier DWA and a dummy bit line drive circuit DBD in FIG. 2 writes data to the memory cells. Write circuit, for example, write amplifier WA in FIG.
And a circuit including the bit line drive circuit BD.

Alternatively, the pulse generating circuit PG for generating the write pulse WE by obtaining an output from the read port, that is, for example, the RP in FIG. 2, detects the inversion time of the dual port cell DPC, and And a circuit for generating a write pulse proportional to

Alternatively, the output from the read port, for example, the RP in FIG.
The pulse generating circuit PG for generating the data is a sense circuit for reading the storage data of the dual port cell DPC, for example, the DSA shown in FIG.
A latch circuit that receives and holds K, for example, DL in the same figure, a comparison circuit that compares the output signal of the latch circuit DL with the output signal of the sense circuit DSA, for example, the CMP in FIG. 3, and an output signal of the comparison circuit CMP , And a delay circuit for delaying the signal, for example, DLY in FIG.

[0008]

According to the present invention, writing is performed on a dual-port cell having almost the same response as that of a memory cell, and the inversion of the information is detected to determine a writing pulse width. Therefore, no matter how the element characteristics fluctuate, the fluctuation amount of the write pulse width tw and the cell inversion time trev always become the same. Therefore, it is unlikely that trev becomes large and tw becomes small unlike the prior art. According to the present invention, the timing margin conventionally required can be significantly reduced, so that the cycle time can be shortened.
That is, according to the present invention, a dummy memory cell in which data is written in the same manner as a memory cell is provided, and the dummy memory cell includes a dual port cell DPC including the same configuration as the memory cell.
, It is possible to simulate the write response operation of the memory cell with the dual port cell DPC. Then, the write response operation can be artificially detected through the read port of the dual port cell DPC. This detection may be performed in the pulse generation circuit PG. Thereby, the pulse width determined from the response characteristics of the memory cell can be found in a pseudo manner. Further, if a pulse is generated in the pulse generation circuit PG so as to secure a setup time and a hold time for a data input signal and the like and is output as a write pulse, a change in element characteristics due to application of the write pulse is obtained. Will be compensated. Therefore, the above-mentioned timing margin can be greatly reduced and the cycle time can be increased.

In order to ensure this compensation, the write circuit for providing a write output to the write port of the dual port cell DPC and the write circuit for writing data to the memory cell have the same configuration, or the pulse generating circuit PG It is apparent from the above description that it is desirable to include a circuit that detects the inversion time of the dual port cell DPC and generates a write pulse proportional to the inversion time.

In the pulse generation circuit of the present invention, as will be described in detail later, a sense circuit, a latch circuit, and a comparison circuit detect the inversion time of the dual port cell DPC and output a pulse having a pulse width corresponding to the inversion time. obtain. Further, the pulse width extending circuit and the delay circuit can provide the pulse width with a minimum margin such as a setup time. Therefore, these circuits can contribute to a significant reduction in the timing margin by compensating the element characteristics.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a diagram showing a basic configuration of the present invention. W
PG is a write pulse generation circuit, and RAM is a RAM including a cell array of memory cells, a read / write circuit, and the like.
The main body. DW is a write circuit for writing to a dual port cell, DPC is a dual port cell, PG
Is a logic circuit that generates a write pulse based on a read signal from a dual port cell. The DPC is included in a dummy memory cell (hereinafter simply referred to as a dummy cell) together with its write port (write port) WP and read port (read port) RP. The dummy cells are provided to simulate memory cells. CLK is a clock signal, R / W is a write control signal, and WE is a write pulse. Since the dual port cell can be configured by making only a slight change to the memory cell as described later, the response to the write operation is almost the same as that of the main memory cell. In the present invention, the write circuit DW writes data to the dual port cell DPC from the write port WP in synchronization with the clock signal CLK, and detects that the information has been inverted by the PG based on the read signal from the read port RP. A write pulse having a pulse width corresponding to the inversion time is generated. Therefore, no matter how the characteristics of the main body memory cell change, the amount of change in the inversion time of the memory cell and the amount of change in the pulse width of the write pulse always become equal. For example, as shown in FIG. 5, when trev changes so as to increase by 30%, tw changes at point C, that is, tw changes by 30%. For this reason, it is unlikely that trev increases and tw decreases as in the related art. Therefore, as shown in FIG. 5, it is sufficient to design tw (typ) = trev (typ), and tw can be made much smaller than in the conventional art. As a result, the cycle time can be significantly reduced.

FIG. 2 is a diagram showing a configuration example of the present invention.
FIG. 3 is a diagram showing the timing relationship of each signal. FIG.
, WPG is a write pulse generation circuit, WA is a write amplifier, CA is a cell array, and BD is a bit line drive circuit. WPG is a dummy cell array DCA including a dual port cell DPC, and a dummy bit line driving circuit DB.
D, a dummy write amplifier DWA, a sense amplifier DSA for detecting information of a dual port cell, a master / slave latch circuit DL, a comparison circuit CMP, an inverter INV, a pulse width expansion circuit STR, a delay circuit DLY, and an OR circuit OR
Consists of

The dummy cell array DCA includes one dual-port cell DPC and n dummy cells DC1 to DCnn having exactly the same structure as the memory cells C1 to Cn. The number of cells connected to the bit lines is made equal to the cell array CA. The high potential VH is applied to the word line of the DPC and the dummy cell D
A low potential VL is applied to the word lines C1 to DCn, and DP is applied.
It is configured so that writing is performed on C. The DPC has one write port and one read port, and can read even during writing. Since the dual-port cell can be configured by making only minor changes to the main memory cell, the response to the write operation is almost the same as that of the memory cell. Also, the dummy bit line driving circuit D
The circuit configuration of the BD and the dummy write amplifier DWA is configured exactly the same as the BD and the WA. With this configuration, it is possible to equalize the inversion time trev of the memory cell in the dummy cell array DCA and the cell array CA, regardless of how the element characteristics vary. WP of the dummy cell array DCA is a write port, and RP is a read port. DL is a master / slave latch, which takes in data at the rising edge of the clock signal CLK. When the dummy write signal DWE is “0”, the dummy write amplifier DWA outputs the dummy data signal D
Works to write DIB information.

The comparison circuit CMP is constituted by an EXOR circuit.
"0" if the input signals match, "" if not
1 ". The operation of this circuit will be described in detail below with reference to Fig. 3. This circuit operates in synchronization with the clock signal CLK, and one cycle starts from the rising edge of CLK. Upon rising, the information of the dual port cell DPC is taken into the latch circuit DL.In the example of FIG.3, the stored information of the DPC is "0", so the read information RD of the DPC is "0", and Output D
DI becomes "0". Therefore, the output DWE of the comparison circuit CMP becomes “0”. DDI is the inverter IN
The output signal DDIB becomes "1". Therefore, a "1" write operation to the dummy cell array DCA starts. When the storage information of the DPC is inverted and becomes "1", the sense amplifier detects this and the RD changes to "1", so that the output DWE of the CMP becomes "1" and the write operation ends. As described above, in this circuit, DWE is set to “0” in synchronization with the CLK signal, the inverted write is performed on the DPC, and the fact that the information has been inverted is sensed by the sense amplifier DSA.
And DWE is returned to "1". For this reason, the pulse width of the DWE is determined by the inversion time of the DPC and the DSA.
And the delay time of CMP. Usually DSA and C
Since the delay time of MP is very small as compared with the inversion time of the cell, the pulse width of DWE is almost equal to the inversion time of the cell. The pulse width of the DWE is increased by a pulse width extending circuit STR so that a minimum margin is provided, the delay is delayed by a desired setup time by a delay circuit DLY. A write pulse is supplied to a write amplifier. As described above, in this circuit, the dummy cell array that responds in the same manner as the cell array is provided, the fact that the information of the dual port cell is inverted is detected, and the write pulse width is determined. However, the variation amount between the write pulse width tw and the cell inversion time trev can be made equal.

FIG. 6 shows an embodiment of a dummy cell array DCA and a dual-port cell sense amplifier DSA. Here, a case where the memory cell is configured by CMOS is shown. Dummy cells DC1 to DCn are MOS
Flip-flop including transistors MP0, MP1, MN0, MN1 and transfer gates MT0, MT1
Consists of The structure and arrangement of the dummy cells are exactly the same as those of the main cell array. The dual port cell DPC is configured by adding read MOSs MTR0 and MTR1 to a main body cell. Flip-flops and transfer gates for writing (MPD0, MPD1, MND0,
MND1, MTW0, MTW1) are the same as the dummy cells. Therefore, the response to the write operation is almost the same as that of the main memory cell. One end of the read MOS is connected to the storage node of the DPC, and the other end is connected to the sense amplifier DSA.
Connected to. The sense amplifier DSA has a load resistance RL0,
RL1 and a differential amplifier circuit. Now, for example, MND0
Are conducting and MND1 is non-conducting,
A current flows to RL0 via MTR0, and the base potential of bipolar transistor QS0 decreases. This potential change is expressed by transistors QS0, QS1, QEF0, resistor RS
0, amplified by a differential amplifier circuit including a current source IS, and output as a read signal RD of a dual port cell. By adopting such a configuration, the state of the DPC can be continuously monitored even during the writing, and the inversion of the information of the DPC can be detected. Here, a memory cell in which a flip-flop is formed by CMOS is described as an example. However, the flip-flop may be formed by NMOS and a resistor, or a PMOS using NMOS and a polycrystalline silicon film.
May be configured.

FIG. 7 shows another embodiment of the dual port cell. In this embodiment, the read MOSs MTR0, MTR
The gate of TR1 is connected to the storage node, and the drain is connected to the sense amplifier DSA. The configuration of the DSA may be the same as the embodiment of FIG. Now, for example, if MND0 is conducting and MND1 is non-conducting, the gate of MTR0 becomes low potential, the gate of MTR1 becomes high potential,
A current flows to RL1 via R1, and the base potential of bipolar transistor QS1 decreases. This potential change is expressed by transistors QS0, QS1, QEF0, resistor RS0,
The signal is amplified by a differential amplifier circuit including a current source IS and output as a read signal RD of a dual port cell. By adopting such a configuration, the state of the DPC can be continuously monitored even during the writing, and the inversion of the information of the DPC can be detected.

FIG. 8 shows still another embodiment of a dual-port cell in which a CMOS inverter is connected to a storage node of the cell. CMOS inverter is PMOS
MPR0, MPR1, NMOS MNR0, MNR1, high potential VOH is applied to the source of the PMOS, and NMO
A low potential VOL is applied to the source of S. With this configuration, the output of the CMOS inverter becomes one of the potentials VOH and VOL according to the information of the DPC. VOH and VOL are set to appropriate potentials so that the transistors constituting the sense amplifier DSA do not saturate.
As a technique for realizing a high-speed and highly-integrated memory, there is a technique described in Japanese Patent Application Laid-Open No. 3-76096. In this technique, a voltage smaller than a power supply voltage of a chip is applied to a CMOS memory cell to reduce the drive amplitude of a word line and a bit line, thereby realizing high speed operation. Since the drive amplitude of the bit line can be reduced, the bit line drive circuit can be constituted by a high-speed ECL circuit, and the write cycle time can be significantly increased. This technique and the present invention can be easily combined. In this case, it is only necessary to reduce the power supply voltage applied to the dummy cell and the dual port cell. Further, the circuit configuration of the dual port cell may be any of FIGS.

FIG. 9 shows another embodiment of the dummy cell array, in which the present invention is applied to a bipolar memory. Here, an example of a cell with an SBD and a resistance as a load is shown. This cell is suitable for high-speed operation and is mainly used as a cache memory of a large computer. The dummy cells DC1 to DCn have exactly the same structure as the main body cell. The dual-port cell DPC has a configuration in which read transistors QR0 and QR1 are added to a main body cell. The bases of QR0 and QR1 are connected to the DPC storage nodes. The transistors QBB0 and QBB1 are
0 and QR1 are respectively connected to form a current switch, and a reference potential VBB is applied to a base thereof. VBB
Is set to an intermediate potential between the high potential and the low potential of the storage nodes A and B of the DPC. Now, for example, the storage node A has a high potential,
Assuming that B has a low potential, the transistor QR0 is turned on and the transistor QR1 is turned off. As a result, a current flows through the load resistance RL0 of the sense amplifier DSA, and the base potential of the bipolar transistor QS0 decreases. This potential change is expressed by transistors QS0, QS1, QEF0,
The signal is amplified by a differential amplifier circuit including a resistor RS0 and a current source IS and output as a read signal RD of the dual port cell DPC. By adopting such a configuration, the state of DPC can be continuously monitored even during writing, and
The information inversion of the PC can be detected.

FIG. 10 is a diagram showing an example of WPG arrangement. Here, an example is shown in which the cell array is divided into two and the word driver WD is arranged at the center of the chip. The dummy cell array DCA is arranged at the center of the chip adjacent to the cell array CA. Circuits other than DCA in the WPG (latch circuits, comparison circuits, etc.) are arranged at locations indicated by CNTL in the figure. Thus, the WE signal line from the WPG to the write amplifier WA can be shortened, and the write cycle time can be shortened. Next, an embodiment of the delay circuit DLY will be described. The delay circuit DLY is a circuit that delays the write pulse by the setup time. Normally, the setup time is almost equal to the delay time t (A−W) from the address signal to the word line drive signal. Therefore, it is desirable that the delay time in DLY be equal to t (A−W). This is DL
This can be achieved by making the circuit configuration of Y the same as that of the word decoder.

FIG. 11 shows a wired OR and an ECL NOR.
5 shows an example of a delay circuit for reproducing a delay time of a word decoder obtained by combining circuits. FIG. 11A shows a word decoder, and FIG. 11B shows a corresponding delay circuit. The decoder in (a) is a bipolar SRAM
And address signals A0 to AB3 by address buffers AB0 to AB3.
A3 positive and negative signals are generated, a wired OR is obtained, and predecoding is performed. The ECLNOR circuits XD0 and XD1 further decode to obtain word line drive signals W0 and W1. The delay time of this circuit is substantially equal to the sum of the delay time of the address buffer and the delay time of the ECL NOR circuit. Accordingly, the delay circuit corresponding to the address buffer AB and the ECL as shown in FIG.
This can be easily realized by connecting the NOR circuits XD in series.

FIG. 12 shows an example of a delay circuit for reproducing the delay time of the diode decoder. FIG.
12A shows a word decoder, and FIG. 12B shows a corresponding delay circuit. The decoder (a) is used frequently in a bipolar SRAM, and performs decoding by an AND circuit composed of diode-connected transistors. Address buffers AB0 to AB3 generate positive and negative signals of address signals A0 to A3, and these signals are decoded by AND circuits AND0 and AND1. The delay time of this circuit is substantially equal to the sum of the delay time of the address buffer and the delay time of the AND circuit. Therefore,
The corresponding delay circuit can be easily configured by connecting the address buffer AB and the AND circuit AND in series as shown in FIG.

FIG. 13 shows an example of a delay circuit for reproducing the delay time of a word decoder constituted by a BiCMOS circuit. FIG. 13A shows a word decoder, and FIG.
(B) shows a corresponding delay circuit. (A)
Is often used in a BiCMOS SRAM and performs decoding by a BiCMOS NAND and NOR circuit. The address buffers AB0 to AB3 generate positive and negative signals of the address signals A0 to A3,
These signals are converted into C by the level conversion circuits LC0 and LC1.
MOS level is converted to the BiCMOS NAND circuit P
Predecode is performed by D0 and PD1. Furthermore, Bi
The final stage decoding is performed by the CMOS NOR circuits MD0 and MD1 to obtain word line drive signals W0 and W1. The delay time of this circuit is substantially equal to the sum of the delay times of the address buffer, the level conversion circuit, the NAND circuit, and the NOR circuit. Therefore, the delay circuit corresponding to this, as shown in (b), the address buffer AB and the level conversion circuits LC, N
It can be easily configured by connecting the AND circuit PD and the NOR circuit MD in series. As described above, by configuring the delay circuit DLY according to the configuration of the word decoder, the setup time can be set to an optimal value. By doing so, it is not necessary to take useless timing margins, so that the cycle time can be further shortened.

FIG. 14 shows an example of the configuration of the pulse width extending circuit STR. FIG. 14A shows a circuit configuration, and FIG.
(B) shows an operation waveform. The pulse width extending circuit can be composed of a plurality of inverters and a NOR circuit as shown in FIG. After the input signal IN is inverted by the inverter i0, it is delayed as necessary through an even-numbered inverter. Here, an example in which delay is performed by four inverters i1 to i4 is shown. By taking the NOR of the delayed signal B and the signal A before the delay, a signal OUT having a wider pulse width than the input signal IN is obtained. Here, the pulse width increases by the same amount as the delay time of the inverters i1 to i4. Therefore, a desired pulse width can be obtained by appropriately adjusting the number of stages of the inverter.

FIG. 15 shows an example of a plan view of the dummy cell of the embodiment of FIG. FIG. 15 is also a plan view of the body cell since the dummy cell and the body cell have exactly the same structure. In the figure, L indicates LOCOS, FG indicates a first-layer polycrystalline silicon film, SG indicates a second-layer polycrystalline silicon film, and CNT indicates a contact hole pattern. Transfer MOSs MT0 and MT1 are provided at the top of the cell, and a driver M is provided at the center.
OS MN0 and MN1 are connected to PMOS MP0 and M
P1 is arranged. Cross-coupling of the two inverters is performed using SG.

FIG. 16 shows an example of a plan view of the dual port cell of FIG. It has a structure in which read transfer MOSs MTR0 and MTR1 are added to the cell of FIG. The other parts are exactly the same as the main body cell, and the response to the write operation is almost the same as the main body memory cell.

FIG. 17 shows an example of a plan view of the dual port cell of FIG. It has a structure in which readout MOSs MTR0 and MTR1 are added to the cell of FIG. Since the gate of MTR0 can be formed of the same FG as the gates of MND0 and MPD1, the area can be reduced. Also in this embodiment, the flip-flop portion and the transfer M
Since the parts of the OS MTW0 and MTW1 can be made exactly the same as the main body cell, the response to the write operation can be made almost the same as the main body memory cell.

FIG. 18 shows an example of a plan view of the dual port cell of FIG. The read CMOS inverters MNR0, MPR0, MNR are added to the cell of FIG.
1, MPR1 is added. Also in the case of this embodiment, the flip-flop portion and the transfer MOS
Since the portions of MTW0 and MTW1 can be made exactly the same as the main body cell, the response to the write operation can be made almost the same as that of the main body memory cell. When the bit line discharge time at the time of writing is shorter than the memory cell inversion time or when the variation of the bit line discharge time is small, WP
Even if the dummy cells are removed from G, the performance of WPG hardly decreases.

FIG. 19 shows a dummy cell CD from the embodiment of FIG.
This is an example in which 1 to DCn are removed. In this configuration, since the bit line discharge time is not included in the pulse width of the DWE, it is necessary to increase the pulse width by the pulse width extending circuit. With this configuration, the area occupied by the WPG can be significantly reduced.

[0029]

As described above, according to the present invention, writing is performed on a dual-port cell having almost the same response as that of a memory cell, and the inversion of the information is detected to determine a writing pulse width. Therefore, no matter how the element characteristics change, the width of the write pulse and the change amount of the cell inversion time always become the same. This makes it possible to reduce the timing margin caused by the change in element characteristics, which has been required conventionally, and to greatly shorten the cycle time.

[Brief description of the drawings]

FIG. 1 is a diagram showing a basic configuration of the present invention.

FIG. 2 is a diagram showing a configuration example of the present invention.

FIG. 3 is a diagram showing a timing relationship of each signal.

FIG. 4 is an explanatory diagram of a conventional technique.

FIG. 5 is an explanatory diagram of the present invention.

FIG. 6 is a diagram showing a configuration example of a dummy cell array.

FIG. 7 is a diagram showing another embodiment of a dual port cell.

FIG. 8 is a diagram showing still another embodiment of the dual port cell.

FIG. 9 is a diagram showing another embodiment of the dummy cell array.

FIG. 10 is a diagram showing an example of WPG arrangement.

FIG. 11 illustrates a configuration example of a delay circuit.

FIG. 12 illustrates a configuration example of a delay circuit.

FIG. 13 illustrates a configuration example of a delay circuit.

FIG. 14 is a diagram showing a configuration example of a pulse width extending circuit.

FIG. 15 is a plan view of a dummy cell.

FIG. 16 is a plan view of a dual port cell.

FIG. 17 is a plan view of a dual port cell.

FIG. 18 is a plan view of a dual port cell.

FIG. 19 is a diagram showing a configuration example of a simplified WPG.

[Explanation of symbols]

WPG: write pulse generation circuit, RAM: RAM body including cell array, read / write circuit, DPC
... Dual port cell, WP ... Write port, RP ... Read port,
PG: pulse generation circuit, R / W: write control signal,
WE: write pulse, DW: write circuit to dual port cell, CA: cell array, BD
... Bit line drive circuit, WA ... Write amplifier, DCA ... Dummy cell array, DBD ...
Dummy bit line drive circuit, DWA: dummy write amplifier, C0 to Cn: memory cells, DC1 to DCn:
Dummy cell, DSA ... Sense amplifier DL ... Master slave latch circuit CMP ...
Comparison circuit STR: pulse width expansion circuit, DLY:
Delay circuit. INV: Inverter OR: OR circuit

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kazuo Kanaya 1-280 Higashi-Koikekubo, Kokubunji-shi, Tokyo Inside Hitachi, Ltd. Central Research Laboratory (72) Inventor Yoji Deji 1-280 Higashi-Koikekubo, Kokubunji-shi, Tokyo Hitachi, Ltd. Central Research Laboratory (72) Inventor Takeshi Kusunoki 3681 Hayano, Mobara-shi, Chiba Hitachi Devices Engineering Co., Ltd. (56) References JP-A-1-236991 (JP, A) (58) Fields investigated (Int. . ^7, DB name) G11C 11/41 - 11/419

Claims (4)

(57) [Claims] 1. A memory cell arranged in a lattice, a write pulse generating circuit for generating a write pulse in response to an external clock signal and a write control signal, and a memory cell receiving the write pulse and a data input signal A write circuit for writing data to the memory cell, wherein the write pulse generation circuit has at least a dual-port memory cell having a write port and a read port and having the same configuration as the memory cell, and has a response characteristic of the memory cell. And a pulse generating circuit for generating a write pulse by obtaining an output from the read port and a write circuit for giving a write output to the write port. 2. The semiconductor memory according to claim 1, wherein a write circuit for providing a write output to said write port has the same configuration as a write circuit for writing data to said memory cells. 3. A semiconductor memory according to claim 1, wherein a pulse generation circuit for obtaining an output from said read port and generating said write pulse detects an inversion time of said dual port memory cell, A semiconductor memory including a circuit for generating a write pulse proportional to an inversion time. 4. The semiconductor memory according to claim 1, wherein said pulse generation circuit generates an output from said read port and generates said write pulse.
A sense circuit for reading stored data of a dual-port memory cell, a latch circuit for receiving and holding the stored data by the clock signal, a comparing circuit for comparing an output signal of the latch circuit with an output signal of the sense circuit, A semiconductor memory comprising: a pulse width extending circuit for extending a pulse width of an output signal of the comparison circuit; and a delay circuit for delaying the signal.