JPH0969625A - Field-effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve pinch-off characteristic or noise characteristic so as to reduce variance of threshold voltage by a method wherein the concentration of Fe acceptors in a semi-insulative InP substrate is at least 50 times as high as the sum of those of donor impurities consisting of Si, S, Sn, and Se at low level therein. SOLUTION: A field-effect transistor is formed on a semi-insulating InP substrate 11 with a buffer layer 12 interposed. The concentration of Fe acceptor in the substrate 11 is made at least 50 times as high as the sum of those of donor impurities consisting of Si, S, Sn, and Se at low level therein. In addition, the layer 12 is comprised of a first buffer 21 with Fe including doped P, a second buffer 22 with Fe including the doped P, and an intrinsic semiconductor layer 23 formed between the layers 21 and 22. Thus, the leak current in the layer 12 can be suppressed, and noise characteristic and variance of threshold voltage can be also reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor, and more particularly to a field effect transistor formed on a semi-insulating InP substrate via a buffer layer, which is suitable for high frequency, low noise and high output.

[0002]

2. Description of the Related Art As a field effect transistor suitable for high frequency, low noise, and high output, one having a channel layer formed on a semi-insulating InP substrate is known. As an example, a high electron mobility transistor (hereinafter referred to as HEMT)
Since the cross-sectional structure is shown in FIG. 6, the manufacturing process of this HEMT will be first described step by step.

On the semi-insulating InP substrate 1, non-doped or Fe is formed by a metal organic chemical vapor deposition method (MOCVD method).
The doped InP buffer layer 2 is 300 nm, the non-doped InGaAs channel layer 3 is 20 nm, the non-doped InAlAs spacer layer 4 is 3 nm thereon, and the n-type I
The nAlAs electron supply layer 5 is 20 nm, and the undoped InAlAs Schottky contact layer 6 is 20 nm,
Finally, the n-type InGaAs ohmic contact layer 7
Grow sequentially to 0 nm. Then, a source electrode 8 and a drain electrode 9 are formed on the n-type InGaAs ohmic contact layer 7 by vapor deposition, and then a part of the n-type InGaAs ohmic contact layer 7 is etched to expose the non-doped InAlAs Schottky contact layer 6. Then, the gate electrode 10 is formed on this exposed portion.

A conventional HEMT formed in this way
In the wafer, residual impurities such as Si, C, and O adhering to the surface of the semi-insulating InP substrate 1 before growth are mixed into the interface between the growth layer and the substrate and serve as donors.
Carriers were sometimes accumulated at the interface with the P buffer layer 2. When the interface carrier concentration is high, a leak current is generated in the buffer layer due to the interface carriers during operation of the HEMT device, and pinch-off characteristics, noise characteristics and the like are significantly deteriorated. In addition, since the residual impurity concentration at the interface greatly varies between the wafer inner surface and the wafer,
The variation in the threshold voltage of the HEMT device also becomes large, which is an obstacle to the integration of the HEMT device.

Therefore, it is necessary to lower the interfacial carrier concentration, and there are two methods as a countermeasure, one of which is a semi-insulating InP substrate before the HEMT is grown by the metal organic chemical vapor deposition method. In this method, the donor impurity concentration on the surface of No. 1 is lowered. As means for this, the semi-insulating InP substrate 1 is subjected to a wet treatment or the like to remove surface impurities, or after the semi-insulating InP substrate 1 is introduced into the reaction tube in the metal organic chemical vapor deposition method. It is possible to heat-treat the semi-insulating InP substrate 1 in a PH3 gas atmosphere. However, even by these means, the donor impurity concentration on the surface of the semi-insulating InP substrate 1 cannot be reduced to a sufficient extent, and it requires time for wet treatment and heat treatment, and equipment, chemicals, PH3 gas, etc. Since the cost is also increased, there are inconveniences such as an increase in product cost.

Another method for reducing the interface carrier concentration is to dope the buffer layer 2 with Fe. When the buffer layer 2 is doped with Fe, the Fe acceptor compensates carriers near the interface, so that the interface carrier concentration can be lowered. However, even with this method, there were the following problems and it could not be said that it was a sufficient countermeasure. That is, normally, in the metalorganic vapor phase epitaxy, the growth is performed at about 650 ° C., but in that case, the Fe acceptor concentration in InP is saturated at about 1 × 10 ¹⁷ cm ⁻³ . However, when the Fe concentration is 1 × 10 ¹⁷ cm ⁻³ and the sheet donor concentration at the interface is 1 × 10 ¹² cm ⁻² or more, carriers remain at the interface, so that a buffer layer having a high resistance is surely obtained. Is difficult. Further, in order to supply the Fe doping raw material to the reaction tube during growth, a small amount of Fe remaining in the reaction tube is mixed into the channel layer and the electron supply layer, so that the concentration of the two-dimensional electron gas and the electron transfer. There is a possibility that it may cause a decrease in degree.

Further, as described above, as the InP is used for the substrate 1 and the buffer layer 2 of the field effect transistor of FIG. 6, it is common to use a semiconductor having the same composition as the substrate 1 for the buffer layer 2. Is. This is because using a semiconductor having a positive ΔE _C with the semiconductor of the substrate for the buffer layer has a greater effect of confining carriers inside the channel layer. However, there is a problem that a leak current flows in the buffer layer as described above.

[0008]

As described above, in the conventional field effect transistor formed on the semi-insulating InP substrate, carriers accumulated in the interface between the buffer layer and the InP substrate cause the accumulation in the buffer layer. There is a problem in that a leak current flows, resulting in deterioration of device characteristics such as pinch-off characteristics and noise characteristics, and an increase in variations in threshold voltage. The present invention has been made to solve such a problem.

[0009]

The present invention is a semi-insulating material I
In a field effect transistor formed on a nP substrate via a buffer layer, Fe in the semi-insulating InP substrate is used.
If the acceptor concentration is Si in the semi-insulating InP substrate,
It is formed 50 times or more higher than the sum of the concentrations of the shallow-level donor impurities composed of S, Sn, and Se.
The semi-insulating InP substrate may be doped with an impurity that forms a donor level whose energy from the conduction band is deep, and the impurity that forms the deep donor level may be Ti or Cr. .

Further, according to the present invention, in a field effect transistor formed on a semi-insulating InP substrate via a buffer layer, the buffer layer is a first buffer composed of a semiconductor layer containing P doped with Fe. A layer, a second buffer layer made of a Fe-doped P-free semiconductor layer, and Fe provided between the second buffer layer and the first buffer layer are not doped, And a semiconductor layer not containing P (so-called intrinsic semiconductor layer). In the field effect transistor of the present invention, the thickness of the semiconductor layer not doped with Fe and containing no P may be 3 to 100 nm.

Furthermore, the present invention is a semi-insulating InP.
In a field effect transistor formed on a substrate via a buffer layer, the Fe acceptor concentration in the semi-insulating InP substrate is set to Si, S,
The buffer layer is formed 50 times or more higher than the sum of the concentrations of the shallow-level donor impurities made of Sn and Se, and the buffer layer is a first buffer layer made of a semiconductor layer containing P doped with Fe. A second buffer layer made of a Fe-doped semiconductor layer not containing P, and Fe provided between the second buffer layer and the first buffer layer is not doped and P It is formed of a semiconductor layer not containing it (a so-called intrinsic semiconductor layer).

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of a field effect transistor according to the present invention will be described in detail below with reference to FIGS. 1 to 5.

FIG. 1 illustrates the resistivity of the InP substrate and the sheet resistance of the buffer layer with respect to the ratio of the Fe acceptor concentration N _A and the shallow donor impurity concentration N _D in the InP substrate in order to explain the point of the present invention. It is a characteristic view showing the relationship with. Shallow donor impurity concentration N in conventional InP substrate
_D is in the range of 2 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ⁻³ , and the shallow donor impurity concentration N _D of the semi-insulating InP substrate 1 of the field effect transistor shown in FIG. 6 is 5 × 10 ¹⁵ cm ^−3. Met. Therefore, in FIG. 1, the horizontal axis represents the ratio (N _A / N _D ) of the Fe acceptor concentration N _A and the donor impurity concentration N _D when N _D = 5 × 10 ¹⁵ cm ⁻³ . In the figure, the broken line shows the resistivity (Ωcm) of the InP substrate, and the solid line shows the sheet resistance (Ω / □) of the buffer layer.

Referring to FIG. 1, as the Fe acceptor concentration N _A in the InP substrate is increased, N _A becomes equal to the shallow donor impurity concentration N _D in the InP substrate (N _A =
In the vicinity of N _D ), the resistivity of the InP substrate sharply increases, and F
The e-acceptor concentration N _A reaches its maximum in the vicinity of three times the donor impurity concentration N _D (N _A = 3N _D ). Further, it can be seen that the resistivity starts to decrease when the Fe acceptor concentration N _A is increased. The resistivity decreases when the Fe acceptor concentration N _A exceeds a certain level because the hole concentration in the substrate increases. Therefore, conventionally, the Fe acceptor concentration N _A for doping the InP substrate is usually 2 to 5 times, and at most 10 times, the donor impurity concentration N _D , and specifically, in most cases, 2 ×. 10 ^{16 to} 5 × 10
Fe doping of ¹⁶ cm ⁻³ was performed. However, when a Fe-doped substrate in this range is used, if donor impurities are accumulated at the interface, the sheet resistance of the buffer layer becomes 10 ⁵ Ω / □ or less, and a high-resistance buffer layer cannot be obtained. It was

On the other hand, in the present invention, the Fe acceptor concentration N _A in the InP substrate is 50 times or more the shallow donor impurity concentration N _{D in} the InP substrate, that is, the Fe acceptor concentration N _A is 1 × 10 ¹⁷ cm ^{−. It is set to 3} or more.
As a result, the effect of compensating for the interfacial carriers is enhanced, and the sheet resistance of the buffer layer becomes 10 ⁷ Ω / □ or more, so that the buffer layer having a high resistance can be reliably formed.

FIG. 2 shows a cross-sectional structure of a HEMT (high electron mobility transistor) as an embodiment of the present invention.

The manufacturing method of the InP substrate used for this HEMT is as follows. First, Fe, Ti-doped InP
A single crystal ingot was added to Liquid Encapsul.
It was grown by the aged Czochralski method (LEC method). After that, through a slicing, lapping, and etching process, semi-insulating Fe, Ti-doped InP substrate 1
Completed 1. The Fe acceptor concentration N _A of the semi-insulating Fe, Ti-doped InP substrate 11 is 5 × 10 ^17.
I made it cm ^-3 .

Next, a non-doped InP buffer layer 12 of 300 nm is formed on the semi-insulating Fe, Ti-doped InP substrate 11 by metalorganic vapor phase epitaxy (MOCVD method).
Next, the non-doped InGaAs channel layer 3 is set to 20 nm,
Non-doped InAlAs spacer layer 4 with 3 nm, n-type I
20 nm nAlAs electron supply layer 5, undoped InA
lAs Schottky contact layer 6 20 nm, n-type I
The nGaAs ohmic contact layer 7 was sequentially grown to 20 nm. After that, a source electrode 8 and a drain electrode 9 are formed on the n-type InGaAs ohmic contact layer 7 by vapor deposition, and then a part of the n-type InGaAs ohmic contact layer 7 is etched to obtain non-doped InA.
The lAs Schottky contact layer 6 was exposed, and the gate electrode 10 was formed on the exposed portion.

HE of this invention made as described above
Since MT has a high Fe acceptor concentration N _A in the semi-insulating Fe and Ti-doped InP substrate 11, not only the leak current at the interface between the InP substrate 11 and the InP buffer layer 12 but also the leak current at the InP buffer layer 12 itself. Could also be lowered. That is, conventionally, since the conduction band is lowered at the interface of the substrate due to the accumulation of the interfacial carriers, the current leakage due to the residual carrier in the non-doped InP buffer layer 12 has a size that cannot be ignored. However, in the present invention, even if the InP buffer layer 12 is not doped during the growth by the metal organic chemical vapor deposition method, the conduction band is largely lifted at the substrate interface and the carriers in the InP buffer layer 12 are depleted. No current leakage occurs in the InP buffer layer 12. As a result, there is no need for Fe doping during the growth process by metalorganic vapor phase epitaxy,
F from the undoped InGaAs channel layer 3 to the upper layer
It becomes possible to prevent the mixture of e. Further, since it is not necessary to use the Fe raw material, it is possible to reduce the cost required for the growth by the metal organic chemical vapor deposition method.

Further, in the present invention, F in the InP substrate 11 is
Since the e acceptor concentration N _A is increased, the resistivity is normally lowered, but in order to prevent this, in the present invention, when the InP single crystal ingot is manufactured, F
e, the energy from the conduction band is about 0.
It is doped with impurities forming a deep donor level of 3 eV. As such impurities, Ti and Cr are preferable, and for example, Ti is 10 to 100% of the Fe concentration.
The Fermi level E _F of the InP substrate is fixed in the range of E _C = E _F = 0.62 to 0.70 eV, that is, approximately in the center of the band gap, when doped in the range.
As a result, it is possible to obtain the InP substrate 11 whose resistivity does not decrease even if the Fe concentration is increased.

As described above, the Fermi level E _F is fixed by doping the impurities that form a deep donor level such as Ti and Cr, and the in-plane threshold voltage during the operation of the field effect transistor is fixed. Uniformity and reproducibility can be enhanced. As a result, the yield when the field effect transistors are integrated is significantly improved. This effect is particularly effective when a n-channel field effect transistor and a p-channel field effect transistor are formed on the same substrate because a buffer layer having high resistance can be obtained for either type of field effect transistor. Is.

Now, in order to verify the effect of the present invention,
A FeMT acceptor concentration in the InP substrate 11 is 50 times or more higher than the sum of the concentrations of donor impurities at a shallow level, and a HEMT not doped with Ti and T
H doped with i to a concentration of 1 × 10 ¹⁷ cm ⁻³
An EMT was manufactured, and the withstand voltage between elements was measured for the conventional HEMT to examine the yield at which a high resistance buffer layer was obtained. Further, the average value of the noise characteristics at a frequency of 12 GHz and the variation in the threshold voltage were measured. The number of samples was 100 in each case, and the results are shown in Table 1.

[0023]

[Table 1] As can be seen from Table 1, the characteristics of the HEMT of the present invention are
In all respects, such as high resistance of the buffer layer, noise characteristics, and variations in threshold voltage, the HEMT is significantly improved. Although the difference between the Fe- and Ti-doped substrate and the Fe-doped substrate is not so large, the Fe- and Ti-doped substrate was slightly superior. Therefore, it can be seen that the effect of the present invention can be obtained regardless of whether the semi-insulating InP substrate 11 is Fe, Ti-doped or Fe-doped.

Next, as another embodiment of the present invention,
A field effect transistor having an improved buffer layer will be described.

FIG. 3 shows the structure of the buffer layer initially manufactured by the inventors. That is, semi-insulating In
Fe-doped I as a first buffer layer on the P substrate 1
Fe-doped InA as the nP layer 21 and the second buffer layer
The 1As layer 22 was laminated. Regarding the growth of this structure, the inventor has found that the Fe-doped InAlAs layer 22 and the Fe-doped In
It was found that when the P layer 21 is adjacent to the P layer 21, diffusion of P from the InP layer into the Fe-doped InAlAs layer is promoted. When P is mixed in the Fe-doped InAlAs layer, the bonding force between P and Fe is very strong, and it is presumed that P is bonded to Fe. As a result, it was considered that Fe was inactivated and the resistivity of the Fe-doped InAlAs layer was lowered.

Therefore, in order to eliminate such a problem, in the present invention, Fe-doped In which is the first buffer layer is used.
P layer and Fe-doped InAlA which is the second buffer layer
By inserting a semiconductor insertion layer which is not doped with Fe and does not contain P between the s layer and the s layer, it is possible to prevent the coupling between P of the first buffer layer and Fe of the second buffer layer. I chose That is, the cross-sectional structure of the buffer layer of the field effect transistor according to the present invention is shown in FIG. 4, in which the semi-insulating InP substrate 1 is sequentially doped with the Fe-doped InP layer 21 and Fe as the first buffer layer. InA as a semiconductor insertion layer not containing P and not containing P
1As layer 23, Fe-doped In which is the second buffer layer
The AlAs layer 22 is laminated.

FIG. 5 shows an example of a sectional structure of a field effect transistor having such a buffer layer. Crystal growth of each layer is performed by metalorganic vapor phase epitaxy (MOCVD).
Method), growth temperature 650 ° C., growth pressure 70 torr
At this point, the lattice matching was performed on the InP substrate. Trimethylindium, trimethylgallium, trimethylaluminum, arsine, and phosphine were used as the raw materials, ferrocene was used as the Fe dopant, and disilane was used as the Si dopant.

Next, the manufacturing process will be described. First, on the semi-insulating InP substrate 1 (which may be Fe or Ti-doped InP substrate 11), the Fe-doped InP layer is 100 nm as the first buffer layer 21, the non-doped InAlAs layer is 40 nm as the semiconductor insertion layer 23, and the second Buffer layer 22
A Fe-doped InAlAs layer is grown as 300 nm. The semiconductor insertion layer 23 is not limited to the InAlAs layer, and a semiconductor layer containing no P such as InGaAs and GaAs can be used. The thickness of the semiconductor insertion layer 23 is preferably in a range that is sufficient to prevent diffusion of P from the InP layer and does not allow leakage current due to background carriers to flow, and is typically 3 to 100.
nm is appropriate.

Next, the non-doped InGaAs channel layer 3 is 20 nm, the non-doped InAlAs spacer layer 4 is 3 nm, and the donor concentration is 3 × 10 ¹⁸ cm ^-3.
The s electron supply layer 5 and the non-doped InAlAs Schottky contact layer 6 are sequentially grown to 20 nm and 20 nm, respectively. Next, a donor concentration of 5 × 10 5 which becomes an ohmic contact layer
After growing an ¹⁸ cm ⁻³ n-type InGaAs layer to a thickness of 20 nm, a portion for forming a gate electrode is removed by etching.
A type InGaAs ohmic contact layer 7 is formed.
Next, the gate electrode 10 is formed on the Schottky contact layer 6.
Is vapor-deposited from AuGe alloy, and the source electrode 8 and the drain electrode 9 are vapor-deposited from Pt on the ohmic contact layer 7.

When the characteristics of the field effect transistor manufactured through these steps were examined, the sheet resistance of the buffer layer was 1 × 10 ⁶ Ω / □ or more. The sheet resistance of the buffer layer of the structure shown in FIG. 3 grown under the same conditions is 1 ×
The semiconductor insertion layer 23, which is about 10 ³ Ω / □ and is not doped with Fe and does not contain P, is provided between the first buffer layer 21 and the second buffer layer 22. Was found to have significantly increased resistance. This is because, as described above, this is a semiconductor insertion layer that is not doped with Fe and does not contain P (non-doped In
AlAs layer), the Fe-doped InP layer as the first buffer layer to the Fe-doped I layer as the second buffer layer.
It is presumed that this is because as a result of suppressing the diffusion of P into the nAlAs layer, the passivation of Fe in the Fe-doped InAlAs layer was suppressed.

[0031]

As described in detail above, according to the present invention, by increasing the Fe acceptor concentration N _A in the InP substrate, carriers at the substrate interface are compensated and the resistance of the buffer layer is increased. In addition, since the buffer layer has two layers and the semiconductor insertion layer is provided between the two layers, the effect of confining carriers is enhanced, and the resistance of the buffer layer is increased. For this reason, the leak current in the buffer layer can be surely suppressed, and the field-effect transistor exhibiting superior characteristics to the conventional one in terms of yield, noise characteristics, variation in threshold voltage, etc. of the high resistance buffer layer. Can be provided.

[Brief description of drawings]

FIG. 1 shows the ratio of Fe acceptor concentration N _A to shallow donor impurity concentration N _D in an InP substrate (where N _D = 5 × 10 ^15).
FIG. 3 is a characteristic diagram showing the relationship between the resistivity of the InP substrate and the sheet resistance of the buffer layer with respect to cm ⁻³ ).

FIG. 2 is a cross-sectional view showing the structure of a high electron mobility transistor (HEMT) as an embodiment of the present invention.

FIG. 3 is a cross-sectional view showing the structure of an initially manufactured buffer layer.

FIG. 4 is a sectional view showing a structure of a buffer layer according to the present invention.

FIG. 5 is a sectional view showing a structure of another embodiment of the field effect transistor according to the present invention.

FIG. 6 is a cross-sectional view showing a structure of a conventional HEMT.

[Explanation of symbols]

1 Fe-doped InP substrate 2 Non-doped (or Fe-doped) InP buffer layer 3 Non-doped InGaAs channel layer 4 Non-doped InAlAs spacer layer 5 n-type InAlAs electron supply layer 6 Non-doped InAlAs Schottky contact layer 7 n-type InGaAs ohmic contact layer 8 Source electrode 9 Drain electrode 10 Gate electrode 11 Fe, Ti-doped (or Fe-doped) InP substrate 12 Non-doped InP buffer layer 21 First buffer layer (Fe-doped InP layer) 22 Second buffer layer (Fe-doped InAlAs layer) 23 Semiconductor insertion layer (InAlAs layer)

Claims (3)

[Claims] 1. A field effect transistor formed on a semi-insulating InP substrate via a buffer layer, wherein the Fe acceptor concentration in the semi-insulating InP substrate is Si, S, A field effect transistor characterized by being 50 times or more higher than the sum of the concentrations of shallow-level donor impurities composed of Sn and Se. 2. A field effect transistor formed on a semi-insulating InP substrate via a buffer layer, wherein the buffer layer comprises a first buffer layer made of a semiconductor layer containing P doped with Fe, and Fe. A second buffer layer made of a semiconductor layer containing no doped P, and Fe provided between the second buffer layer and the first buffer layer not doped and containing P A field-effect transistor, characterized in that it is formed from a semiconductor layer that does not exist. 3. A field effect transistor formed on a semi-insulating InP substrate via a buffer layer, wherein the Fe acceptor concentration in the semi-insulating InP substrate is Si, S, The buffer layer is formed 50 times or more higher than the sum of the concentrations of the shallow-level donor impurities made of Sn and Se, and the buffer layer is a first buffer layer made of a semiconductor layer containing P doped with Fe. A second buffer layer made of a Fe-doped semiconductor layer not containing P, and Fe provided between the second buffer layer and the first buffer layer is not doped and P A field effect transistor, which is formed of a semiconductor layer which does not include.