JPH0969049A - Information processor and its control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a CPU to easily start the processing of a DSP fast as to the information processor which includes the CPU and DSP provided on a single chip. SOLUTION: The control method for the information processor which has the CPU 140 and DSP 190 on the single chip includes a step for providing one of a plurality of instructions by the CPU 140, a step for deciding whether or not the instruction is a single start instruction (calldsp instruction), a step for stopping or continuing the operation of the CPU 140 and sending information showing its start instruction to the DSP 190 when it is decided that the instruction is the start instruction, and a step for receiving the information indicating the start instruction from the CPU 140 and controlling the operation of the DSP 190 according to the information indicating the start instruction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a central processing unit (hereinafter abbreviated as "CPU") and a digital signal processor (hereinafter "DS") provided on a single chip.
And a control method thereof.

[0002]

2. Description of the Related Art FIG. 7 shows the configuration of a conventional information processing apparatus in which a CPU 720 and a DSP 770 are connected. CPU7
20 and DSP 770 are provided on different chips. In the conventional information processing device having such a configuration, the CPU 720 uses the DS
It is common to activate P770.

Referring to FIG. 7, CPU 720 is a CPU
A memory 711 that stores a plurality of instructions that the 720 should execute.
And a control circuit 712 that decodes an instruction output from the memory 711 and controls the operation of a controlled circuit (not shown) such as an arithmetic unit or a register according to the decoded instruction.
And an output port 714 for outputting an address of an instruction to be read by the memory 711 under the control of 12
And The output port 714 is composed of a plurality of bits (for example, 16 bits), and one bit (for example, the most significant bit) among them is connected to the DSP 770. The 1-bit value connected to the DSP 770 is set to 0 or 1 by the control circuit 712, and the output port 7
Held by 14.

The DSP 770 has an input port 7 that receives 1 bit (for example, the most significant bit) of the output port 714 as an input.
60, a memory 761 for storing a plurality of instructions to be executed by the DSP 770, an instruction output from the memory 761 is decoded, and a controlled circuit such as an arithmetic unit or a register is read according to the decoded instruction or the value of the input port 760. A control circuit 762 for controlling the operation (not shown) and an instruction pointer 763 for outputting the address of the instruction to be read by the memory 761 under the control of the control circuit 762 are included. The control circuit 762 is
When the value of the input port 760 is “0”, the preset address is written in the instruction pointer 763.

The operation of the conventional information processing apparatus when the CPU 720 activates the processing executed by the DSP 770 will be described below.

Assume that the most significant bit of output port 714 of CPU 720 is connected to input port 760 of DSP 770. In this case, the CPU 720 outputs an interrupt request to the DSP 770 by rewriting the value of the most significant bit preset to “1” to “0”. To rewrite the value of this most significant bit, use the following 3
It is achieved by performing one step. That is, (1) the contents of the output port 714 are written in a register (not shown) incorporated in the CPU 720, and (2) the most significant bit of the above register is set to "0".
An arithmetic logic operation circuit (not shown) built in 20 calculates the logical product of the above register and x'7FFF '(x''represents a hexadecimal number) and stores the calculation result in the above register. (3) Output the value of the above register to the output port 714
Write in.

The value of the most significant bit is written in the input port 760 of the DSP 770, and the input port 760 outputs the value to the control circuit 762. When the value of the input port 760 is “0”, the control circuit 762 forcibly writes a value set in the instruction pointer, for example, x′FFF0 ′. As a result, the branch to the address x'FFF0 'of the memory is executed, and the DSP 770 executes a predetermined process (execution of an interrupt process). Thus, from the CPU to D
The processing executed by the SP is activated in the form of an interrupt.

[0008]

However, in the information processing apparatus having the above configuration, the CPU side needs to perform several steps of processing before the interrupt request is output, and the DSP side that receives the interrupt request also has to do so. Since many machine cycles are required until the interrupt processing is executed, there is a problem that the processing on the DSP side cannot be activated at high speed. Further, since a plurality of instructions must be combined in a predetermined order to realize the interrupt request, the procedure for realizing the interrupt request is complicated and the structure of the program stored in the memory 711 is also complicated. For this reason, there is a problem that the load of the programmer at the time of creating the program is large and the readability of the program is low, so that the efficiency of testing and debugging after the program is created is low.

Further, with the recent remarkable progress in the LSI microfabrication technology, it has become possible to integrate a plurality of processors having different architectures, such as a CPU and a DSP, on a single chip. However, in consideration of such a new configuration, an information processing apparatus and a control method thereof suitable for activating the processing executed by the DSP from the CPU have not been proposed.

The present invention provides a C on a single chip.
It is an object of the present invention to provide an information processing apparatus including a PU and a DSP, in which a CPU can easily and rapidly execute processing of a DSP, and a control method thereof.

[0011]

An information processing apparatus according to the present invention includes a first processor and a second processor provided on a single chip.
The first processor activates the processing of the second processor by a procedure that calls a subroutine.

The first processor designates a first memory for storing a plurality of instructions and a first memory for designating an address of one instruction to be read out of the plurality of instructions stored in the first memory.
Instruction pointer means, first reading means for reading an instruction corresponding to an address designated by the first instruction pointer means from the first memory, and controlling execution of the instruction read by the first reading means 1 control means, when the instruction is a single activation instruction, the operation of the first instruction pointer means is stopped or continued, and information indicating the activation instruction is sent to the second processor. And a first control means. The second processor includes a second memory for storing a plurality of instructions, a second instruction pointer unit for designating an address of one instruction to be read out of the plurality of instructions stored in the second memory, and the second processor. Second read means for reading an instruction corresponding to the address designated by the two instruction pointer means from the second memory, and second control means for controlling the execution of the instruction read by the second read means, Second control means for receiving information indicating the activation instruction from the first processor and setting the address of the instruction designated by the second instruction pointer means to a predetermined address in accordance with the information indicating the activation instruction. ing.

After the processing of the second processor is activated, the operation of the first processor may be stopped or continued.
When the first processor stops its operation after the processing of the second processor is started, the first processor restarts its operation after the processing of the second processor is completed. When the first processor continues its operation even after the processing of the second processor is started, the first processor is controlled so that the processing of the first processor branches to a predetermined address after the processing of the second processor ends. .

The notification of the end of processing by the second processor is the first notification.
It may be performed by transmitting an interrupt request to the processor, or may be performed by writing a predetermined value in a predetermined register provided in the first processor. When the notification of the end of processing by the second processor is issued by the latter, the first processor refers to the content of the predetermined register when executing the specific branch instruction, and thus the processing by the second processor is completed. Whether or not it can be detected.

It is also possible to switch the operation / stoppage of the operation of the first processor after the activation of the processing of the second processor according to the contents of a predetermined register.

A control method of the present invention is a control method of an information processing apparatus comprising a first processor and a second processor provided on a single chip, wherein the first processor has a plurality of instructions. Providing one instruction, determining whether the instruction is a single activation instruction, and, if the instruction is determined to be the activation instruction, the operation of the first processor Stopping or continuing, and sending information indicating the activation instruction to the second processor, receiving information indicating the activation instruction from the first processor, and receiving the second information according to the information indicating the activation instruction. Controlling the operation of the processor.

Further, another information processing apparatus of the present invention has a first processor and a second processor provided on a single chip, and the first processor performs the processing in the first processor. Using the same start-up instruction that starts up, the process of the second processor is started up as if by calling a subroutine.

The first processor is a first memory for storing a plurality of instructions, the first memory being assigned an address in a first range, and the plurality of instructions stored in the first memory. First instruction pointer means for designating an address of one instruction to be read, first reading means for reading an instruction corresponding to the address designated by the first instruction pointer means from the first memory, and the first reading First control means for controlling the execution of the instruction read by the means. The second processor is a second memory that stores a plurality of instructions, and a second memory to which an address in a second range different from the first range is assigned, and the second memory that is stored in the second memory. Second instruction pointer means for designating an address of one instruction to be read out of the plurality of instructions;
It is provided with second reading means for reading an instruction corresponding to the address designated by the instruction pointer means from the second memory, and second control means for controlling the execution of the instruction read by the second reading means. . When the instruction read by the first reading means is a single activation instruction, the first control means determines that the predetermined address corresponding to the activation instruction is the address in the first range and the first address. It is determined which of the addresses in the range 2 is included, and when the predetermined address corresponding to the activation instruction is included in the addresses in the first range, the instruction designated by the first instruction pointer means Is set to the predetermined address corresponding to the activation instruction, and when the predetermined address corresponding to the activation instruction is included in the addresses in the second range, the operation of the first instruction pointer means is performed. Stop or continue, and send information indicating the start instruction to the second processor. The second control means receives information indicating the activation instruction from the first processor, and the address of the instruction designated by the second instruction pointer means corresponds to the activation instruction in accordance with the information indicating the activation instruction. It is set to the predetermined address.

After the processing of the second processor is activated, the operation of the first processor may be stopped or continued.
When the first processor stops its operation after the processing of the second processor is started, the first processor restarts its operation after the processing of the second processor is completed. When the first processor continues its operation even after the processing of the second processor is started, the first processor is controlled so that the processing of the first processor branches to a predetermined address after the processing of the second processor ends. .

Another control method of the present invention is a control method of an information processing apparatus comprising a first processor and a second processor provided on a single chip, wherein the first processor is a first processor. Has a first memory to which addresses in the range are assigned, and the second processor has a second memory to which addresses in a second range different from the first range are assigned. 1 out of a plurality of instructions stored in the first memory
A step of providing one instruction, a step of determining whether the instruction is a single start instruction, and a step corresponding to the start instruction when the instruction is determined to be the start instruction. Of the address of the first range and the address of the second range, and a predetermined address corresponding to the start command is included in the address of the first range. If it is determined that the first
Controlling the operation of the processor, stopping the operation of the first processor when it is determined that the predetermined address corresponding to the start instruction is included in the addresses of the second range, and Sending information indicating the activation instruction to the second processor, receiving information indicating the activation instruction from the first processor, and controlling operation of the second processor according to the information indicating the activation instruction Includes and.

According to the present invention, a single activation instruction (cal) read from the first memory included in the first processor.
second instruction included in the second processor by the ldsp instruction).
The address of the instruction to be read by the memory is set to a predetermined value. As a result, when starting the processing on the second processor side from the first processor side, the programmer can use a single cal.
All you have to do is code the ldsp instruction. As a result, the programming effort is greatly reduced. Also,
Since the readability of the program is also improved, it is easy to test, debug, and reuse the program. Furthermore, since an input / output port for connecting the first processor and the second processor is not required, the processing of the first processor can be started up at high speed.

Further, according to the present invention, the first processor included in the first processor according to the address corresponding to the single start instruction (call instruction) read from the first memory included in the first processor. It is determined whether to access the memory or a second memory included in the second processor. When the first memory included in the first processor is to be accessed, the start instruction sets the address of the instruction to be read by the first memory included in the first processor to a predetermined value. When the second memory included in the second processor is to be accessed, the start instruction sets the address of the instruction to be read by the second memory included in the second processor to a predetermined value. As a result, the programmer does not have to use different start instructions depending on whether the program to be executed is stored in the first memory of the first processor or the second memory of the second processor, and does not use a single start instruction. (Call instruction) can be used for coding. As a result, the programming effort is greatly reduced. Further, since the readability of the program is improved, it is easy to test, debug and reuse the program. Furthermore, since an input / output port for connecting the first processor and the second processor is not required, the processing of the first processor can be started up at high speed.

[0023]

Embodiments of the present invention will be described below.

(First Embodiment) FIG. 1 shows the arrangement of an information processing apparatus according to the first embodiment of the present invention. The information processing device includes a CPU 140 and a DSP 190. CP
The U 140 and the DSP 190 are provided on the single chip 100. In the information processing apparatus of this embodiment, the CPU
Reference numeral 140 activates the processing for the DSP 190 as if calling a subroutine. That is, DSP
After the processing of 190 is started, the CPU 140 stops its operation, and after the processing of the DSP 190 is completed, the CPU 140 restarts its operation.

The CPU 140 includes a memory 111, an instruction pointer 113 and a control section 112. Memory 11
1 stores a plurality of instructions to be executed. The memory 111 has an instruction pointer 113 out of the plurality of instructions.
The instruction stored in the address output from is read. The instruction read from the memory 111 is the control unit 11
2 is supplied. The control unit 112 controls the execution of the instruction read from the memory 111. Instruction pointer 113
Outputs the address of the instruction to be read from the memory 111 according to the control signal 122. The address value of the instruction to be read from the memory 111 is set in the instruction pointer 113. The instruction pointer 113 is updated by adding 1 to the value when the control signal 122 is “1”, and stops updating the value when the control signal 122 is “0”.

The control unit 112 includes an instruction decoder 115 and a control circuit 120. The instruction decoder 115
The instruction read from the memory 111 is decoded, and the control signal 116 and the address 124 are generated according to the input instruction. The control circuit 120 generates the control signal 122, the control signal 126, and the control signal group 128 according to the control signal 116 and the control signal 172. The control signal group 128 is used to control the operation of controlled circuits (not shown) such as arithmetic units and registers.

The DSP 190 includes a memory 161, an instruction pointer 163, an instruction decoder 170, and a control circuit 180. The memory 161 stores a plurality of instructions to be executed. The memory 161 reads the instruction stored in the address output from the instruction pointer 163 among the plurality of instructions. The instruction read from the memory 161 is supplied to the instruction decoder 170. The instruction decoder 170 decodes the instruction read from the memory 161, and outputs “1” to the control signal 172 when the input instruction is an “instruction to terminate the processing (ret instruction)”. If not, "0" is output to the control signal 172. The control circuit 180 receives the control signal 126 from the control circuit 120 of the CPU 140, and sets the control signal 182 to “1” when the value of the control signal 126 is “1”. The instruction pointer 163 outputs the address of the instruction read from the memory 161. In addition, the instruction pointer 16
3 receives the address 124 from the instruction decoder 115 of the CPU 140, and holds the address 124 when the control signal 182 is “1”.

The operation of the information processing apparatus of this embodiment having the above configuration will be described below.

The instruction pointer 113 normally adds the held values one by one and outputs the address of the instruction read by the memory 111. The instruction read from the memory 111 is decoded by the instruction decoder 115. Instruction decoder 115
Is a control signal 1 when the input instruction is an “instruction for activating the processing of the DSP 190 (callsp instruction)”.
16 active and DSP to address 124 at the same time
At 190, the head address of the memory 161 in which the program to be started is stored is output. For example, the instruction stored at the address x'0100 'of the memory 111 is c
If alldsspx is '0005', address 12
4 is output as x'0005 '. When the control signal 116 is active, the control circuit 120 outputs “0” to the control signal 122 and simultaneously outputs “1” to the control signal 126. Since the control signal 122 is "0", the instruction pointer 113 stops updating and continues to hold the address to be executed next. This stops the processing inside the CPU 140.

Next, the control circuit 180 inside the DSP 190
When the control signal 126 is "1", the instruction pointer 16
Control signal 182 to write the value of address 124 to
"1" is output to. The instruction pointer 163 is the control signal 1
Since 82 is "1", the value of the address 124 is taken as its content and output to the memory 161. That is, at this time, the instruction pointer 163 outputs x'0005 'to the memory 161. After that, the instruction pointer 163 executes the program stored in the memory 161 by incrementing the value by one.

When the instruction read from the memory 161 is the "instruction for instructing the end of processing (ret instruction)",
The instruction decoder 170 outputs "1" to the control signal 172, and also issues an instruction to stop the operation of the instruction pointer 163. The control circuit 120 outputs “1” to the control signal 122 when the control signal 172 is “1”. Instruction pointer 1
In No. 13, since the control signal 122 is "1", the updating of the value is restarted.

The above operation is shown in FIG. CP by the above
The U140 activates the process to the DSP 190 as if by calling a subroutine. Also DSP19
When 0 is operating, the CPU 140 stops, and after the processing of the DSP 190 ends, the CPU 140 resumes operation.

(Second Embodiment) In the information processing apparatus of the first embodiment, when the CPU starts the processing of the DSP, the operation of the CPU is stopped until the processing is completed. The information processing apparatus according to the second embodiment enables the CPU to continue operating even after the DSP processing is activated,
It realizes parallel processing of the CPU and the DSP.

FIG. 2 shows the configuration of the information processing apparatus of the second embodiment according to the present invention. The information processing device is a CPU 240.
And DSP 190. CPU240 and DSP
190 is provided on a single chip 100.

In FIG. 2, the same components as those of the information processing apparatus shown in FIG. 1 are designated by the same reference numerals. The difference from the configuration of the information processing apparatus shown in FIG. 1 is that an instruction pointer 113, an instruction decoder 115 and a control circuit 12 are provided.
0 is an instruction pointer 213 and an instruction decoder 215, respectively.
And the control circuit 220 is replaced.

The CPU 240 includes a memory 111, an instruction pointer 213 and a control section 212. Memory 11
The instruction read from 1 is supplied to the control unit 212. The control unit 212 controls the execution of the instruction read from the memory 111. The instruction pointer 213 outputs the address of the instruction to be read from the memory 111 according to the control signal 222. The instruction pointer 213 contains the memory 1
The address value of the instruction to be read from 11 is set.
The instruction pointer 213 holds the address 228 when the control signal 222 is “1”, and the control signal 222 is “0”.
In the case of, it is updated by adding 1 to the value.

The control unit 212 includes an instruction decoder 215 and a control circuit 220. The instruction decoder 215
The instruction read from the memory 111 is decoded, and the control signal 216 and the address 124 are generated according to the input instruction. The control circuit 220 generates the control signal 222, the address 228, the control signal 126, and the control signal group 128 according to the control signal 216 and the control signal 172. The control signal group 128 is used to control the operation of controlled circuits (not shown) such as arithmetic units and registers.

The operation of the information processing apparatus of this embodiment having the above configuration will be described below.

The difference from the operation of the information processing apparatus shown in FIG. 1 is that the instruction pointer 213 during the operation of the DSP 190.
Control and the instruction read from the memory 161 is ret
This is control of the instruction pointer 213 in the case of an instruction.

The instruction read from the memory 111 is decoded by the decoder 215. Instruction decoder 215
The input instruction is "The processing of DSP190 is started,
And, an instruction (calld) for continuing the operation of the CPU 240.
sp2 instruction) ”, the control signal 216 is activated, and at the same time, the head address of the memory 161 in which the program to be activated by the DSP 190 is stored is output to the address 124. For example, x'0 of the memory 111
The instruction stored in the address 100 'is called callsp2
When it is x'0005 ', x'0 is assigned to the address 124.
005 'is output. The control circuit 220 receives the control signal 216
Is active, the control signal 222 continues to output “0”, and at the same time, the control signal 126 outputs “1”. Since the control signal 222 is "0", the instruction pointer 213 continues to update its value. This causes the CPU 240 to continue operating.

On the other hand, when the instruction read from the memory 161 is the "instruction to terminate the processing (ret instruction)", the instruction decoder 170 outputs "1" to the control signal 172, and the instruction pointer It issues an instruction to stop the operation of 163. When the control signal 172 is "1", the control circuit 220 outputs "1" to the control signal 222, and at the same time, outputs a preset value to the address 228, for example, x'F000 '. Since the control signal 222 is "1", the instruction pointer 213 holds the address 228 and at the same time saves the value before holding the address 228 in the storage means (not shown). The control circuit 220 outputs “0” to the control signal 222 after the instruction pointer 213 holds the address 228. As a result, the instruction pointer 213 has the address 22
After holding the value of 8, the value is updated by adding 1 to it. As a result, the process is executed from the preset address 228 (for example, x'F000 ') in the memory 111.

The above operation is shown in FIG. CP by the above
The U240 activates the process for the DSP 190 as if by calling a subroutine. Also DSP19
Even when 0 is operating, the CPU 240 is operating and D
After the processing of SP190 is completed, the CPU 240 recognizes the completion of the processing of DSP190 by branching to a preset address 228.

(Third Embodiment) In the information processing apparatus of the third embodiment, the CPU is provided with a register used for monitoring whether or not the processing of the DSP is completed. D
When the processing of SP is completed, a predetermined value is written in the register. When the instruction read from the memory is a specific branch instruction (jmpreg instruction), the CPU refers to the value of the register. In this way,
The CPU monitors whether or not the processing of the DSP has been completed by executing the jmpreg instruction. If the value of the register is a predetermined value, the CPU processing branches to the address designated by the jmpreg instruction. This allows
The CPU recognizes the end of processing in the DSP.

FIG. 3 shows the configuration of an information processing apparatus according to the third embodiment of the present invention. The information processing device is a CPU 340.
And DSP 190. CPU340 and DSP
190 is provided on a single chip 100.

In FIG. 3, the same components as those of the information processing apparatus shown in FIG. 2 are designated by the same reference numerals. The difference from the configuration of the information processing apparatus shown in FIG. 2 is that the instruction decoder 215 and the control circuit 220 are replaced with the instruction decoder 315 and the control circuit 320, respectively, and the register 3
This is the point where 30 is added.

The CPU 340 includes a memory 111, an instruction pointer 213 and a control unit 312. Memory 11
The instruction read from 1 is supplied to the control unit 312. The control unit 312 controls the execution of the instruction read from the memory 111. The instruction pointer 213 outputs the address of the instruction to be read from the memory 111 according to the control signal 322. The instruction pointer 213 contains the memory 1
The address value of the instruction to be read from 11 is set.
The instruction pointer 213 holds the address 328 when the control signal 322 is “1”, and the control signal 322 is “0”.
In the case of, it is updated by adding 1 to the value.

The control unit 312 includes an instruction decoder 315 and a control circuit 320. The instruction decoder 315 is
The instruction read from the memory 111 is decoded, and the control signal 316, the control signal 317, and the address 124 are generated according to the input instruction. The control circuit 320 generates the control signal 322, the address 328, the control signal 126, and the control signal group 128 according to the control signal 316, the control signal 317, and the value of the register 330. The control signal group 128 is
It is used to control the operation of controlled circuits (not shown) such as arithmetic units and registers.

The operation of the information processing apparatus of this embodiment having the above configuration will be described below.

The difference from the operation of the information processing apparatus shown in FIG. 2 is the control of the instruction pointer 213 when the instruction read from the memory 161 is a ret instruction.

The instruction read from the memory 111 is decoded by the decoder 315. Instruction decoder 315
The input instruction is "The processing of DSP190 is started,
In addition, an instruction (calld) for continuing the operation of the CPU 340
sp2 instruction) ”, the control signal 316 is activated, and at the same time, the head address of the memory 161 in which the program to be activated by the DSP 190 is stored is output to the address 124. For example, x'0 of the memory 111
The instruction stored in the address 100 'is called callsp2
When it is x'0005 ', x'0 is assigned to the address 124.
005 'is output. The control circuit 320 outputs the control signal 216
Is active, the control signal 322 continues to output “0”, and at the same time, the control signal 126 outputs “1”. Since the control signal 322 is "0", the instruction pointer 213 continues to update its value. This causes the CPU 340 to continue operating.

On the other hand, when the instruction read from the memory 161 is the “instruction to terminate the processing (ret instruction)”, the instruction decoder 170 outputs “1” to the control signal 172, and the instruction pointer It issues an instruction to stop the operation of 163. Register 33 when control signal 172 is "1"
0 is set to "1". The instruction decoder 315 outputs a control signal when the instruction read from the memory 111 is “an instruction that checks the state of the register 330 and branches to a specific address when the value of the register 330 is“ 1 ”(jmpreg instruction)”. Activate 317. Control circuit 32
0 means register 3 if control signal 317 is active
When the content of 30 is read and the value is "1", "1" is output to the control signal 322, and at the same time, jm is output to the address 328.
The branch destination address specified by the preg instruction is output.
For example, the instruction read from the memory 111 is jpre
g x'0300 'instruction, x'at address 328
It outputs 0300 '. Since the control signal 322 is "1", the instruction pointer 213 sets the address 328 to (x'03
00 ') Hold. The control circuit 320 uses the instruction pointer 21
3 holds the address 328, and then outputs “0” to the control signal 322. As a result, the instruction pointer 213 holds the value of the address 328 and then updates the value by adding 1 to the value. As a result, the process is executed from the address 328 (x'0300 ') of the memory 111.

The above operation is shown in FIG. From the above, C
The PU 340 activates the process to the DSP 190 as if by calling a subroutine. Also DSP1
The CPU 340 is operating even when 90 is operating,
After the processing of the DSP 190 is completed, the CPU 340 stores the memory 111
The value of the register 330, that is, whether the processing of the DSP 190 is completed, is monitored by the instruction of the program stored in (jmpreg instruction), and after the processing of the DSP 190 is completed, jm
The end of processing in the DSP 190 is recognized by branching to the address specified by the preg instruction.

(Fourth Embodiment) In the information processing apparatus of the fourth embodiment, a register for storing information indicating whether the CPU operation is stopped or continued while the DSP is operating is a CPU.
It is provided in. The CPU switches between stopping and continuing the operation of the CPU during the operation of the DSP according to the contents of the register. This switching combines the function of the calldsp instruction mentioned in the first embodiment and the function of the calldsp2 instruction mentioned in the second embodiment into one instruction (call).
dsp3 instruction).

FIG. 4 shows the configuration of an information processing apparatus according to the fourth embodiment of the present invention. The information processing device is a CPU 440.
And DSP 190. CPU440 and DSP
190 is provided on a single chip 100.

In FIG. 4, the same components as those of the information processing apparatus shown in FIG. 2 are designated by the same reference numerals. The difference from the configuration of the information processing apparatus shown in FIG. 2 is that the instruction pointer 213, the instruction decoder 215, and the control circuit 22.
0 is the instruction pointer 4113 and the instruction decoder 41, respectively.
5 and the control circuit 420, and a register 432 is added.

The CPU 440 includes the memory 111, an instruction pointer 413 and a control unit 412. Memory 11
The instruction read from 1 is supplied to the control unit 412. The control unit 412 controls the execution of the instruction read from the memory 111. The instruction pointer 413 outputs the address of the instruction to be read from the memory 111 according to the control signals 422 and 423. The address value of the instruction to be read from the memory 111 is set in the instruction pointer 413. The instruction pointer 413 is updated by adding 1 to the value held when the value of the control signal 422 is “1”, and the value held when the value of the control signal 422 is “0” is updated. Stop updating. Further, the instruction pointer 413 newly holds the address 428 when the value of the control signal 423 is “1”.

The control unit 412 includes an instruction decoder 415 and a control circuit 420. The instruction decoder 415 is
The instruction read from the memory 111 is decoded, and the control signal 416 and the address 124 are generated according to the input instruction. The control circuit 420 controls the control signal 42 according to the control signal 416, the control signal 172, and the contents of the register 432.
2, control signal 423, address 428, and control signal 126
And a control signal group 128 are generated. Control signal group 128
Are used to control the operation of controlled circuits (not shown) such as arithmetic units and registers.

The operation of the information processing apparatus of this embodiment having the above-mentioned structure will be described below.

The difference from the operation of the information processing apparatus shown in FIG. 2 is that the instruction pointer 413 is changed according to the contents of the register 432.
This is the point where the control of can be switched. As a result, the stop / continuation of the operation of the CPU 440 during the operation of the DSP 190 is switched according to the contents of the register 432.

A value of "0" or "1" is preset in the register 432 via a data bus (not shown).

The processing when the value preset in the register 432 is "0" will be described. The instruction read from the memory 111 is decoded by the instruction decoder 415. The instruction decoder 415 calls the input instruction to call.
When it is a dsp3 instruction, the control signal 416 is activated, and at the same time, the head address of the memory 161 in which the program to be activated by the DSP 190 is stored is output to the address 124. For example, x'01 of the memory 111
The instruction stored at address 00 'is call sp3
When it is x'0005 ', it is x'00 at the address 124.
05 'is output. When the control signal 416 is active, the control circuit 420 outputs "0" to the control signal 422, stops updating the instruction pointer 413, and simultaneously outputs "1" to the control signal 126. The control circuit 420 outputs “1” as the control signal 422 when the control signal 172 is “1”. The control signal 422 of the instruction pointer 413 is “1”.
Therefore, the update of the value is restarted.

The processing when the value preset in the register 432 is "1" will be described. The instruction read from the memory 111 is decoded by the instruction decoder 415. The instruction decoder 415 calls the input instruction to call.
When it is a dsp3 instruction, the control signal 416 is activated, and at the same time, the head address of the memory 161 in which the program to be activated by the DSP 190 is stored is output to the address 124. For example, x'01 of the memory 111
The instruction stored at address 00 'is call sp3
When it is x'0005 ', it is x'00 at the address 124.
05 'is output. When the control signal 416 is active, the control circuit 420 continues to output “1” to the control signal 422 and simultaneously outputs “1” to the control signal 126. Since the control signal 422 is "1", the instruction pointer 413 continues to update its value, whereby the CPU 440 continues to operate. When the control signal 172 is "1", the control circuit 420 outputs "1" to the control signal 423, and at the same time, the address 4
A value preset to 28, for example, x'F000 'is output. Since the control signal 423 is "1", the instruction pointer 413 holds the address 428, and at the same time saves the value before holding the address 428 in the storage means (not shown). In the control circuit 420, the instruction pointer 413 has the address 4
After holding 28, “0” is output as the control signal 423. As a result, the instruction pointer 413 holds the value of the address 428 and then updates the value by adding 1 to the value. As a result, the process is executed from the preset address 428 (for example, x'F000 ') in the memory 111.

In this way, according to the value preset in the register 432, the call mentioned in the first embodiment is called.
Function of dsp instruction and calld referred to in the second embodiment
The function of the sp2 instruction can be realized by one instruction (call sp3 instruction).

(Fifth Embodiment) In the information processing apparatus of the first embodiment, the callsp command always activates the DSP process, and it is necessary to instruct it by another command when the CPU subroutine is executed. was there. For this reason,
The programmer has to use different instructions depending on whether the program he wants to use is a subroutine inside the CPU or a subroutine inside the DSP. The information processing apparatus of the fifth embodiment improves on this point, and has a unified single instruction (call instruction) regardless of whether it is a subroutine inside the CPU or a subroutine inside the DSP. And execute processing in the CPU and D
It is possible to activate processing to the SP. FIG. 5 shows the configuration of the information processing apparatus of the fifth embodiment according to the present invention. The information processing device includes a CPU 540 and a DSP.
590 and. The CPU 540 and the DSP 590 are provided on the single chip 500.

The CPU 540 includes a memory 511, an instruction pointer 513 and a controller 512. Memory 51
1 stores a plurality of instructions to be executed. Further, the memory 511 is assigned with a certain range of addresses. For example, 1024 words from address 0 to address x'3FF 'are assigned to the memory 511. The memory 511 has an instruction pointer 51 among the plurality of instructions.
The instruction stored in the address output from 3 is read. The instruction read from the memory 511 is the control unit 5
12 are supplied. The control unit 512 controls the execution of the instruction read from the memory 511. Instruction pointer 51
3 is a memory 511 according to the control signals 522 and 523.
The address of the instruction to be read from is output. An address value of an instruction to be read from the memory 511 is set in the instruction pointer 513. The instruction pointer 513 is updated by adding 1 to the value when the control signal 522 is “1”, and stops updating the value when the control signal 522 is “0”. Also, the instruction pointer 513
Is the address 518 when the control signal 523 is "1".
Hold the contents of.

The control unit 512 includes an instruction decoder 515 and a control circuit 520. The instruction decoder 515 is
The instruction read from the memory 511 is decoded, and the control signal 516 and the address 518 are generated according to the input instruction. The control circuit 520 generates a control signal 522, a control signal 523, a control signal 526, and a control signal group 528 according to the control signal 516, the address 518, and the control signal 572. The control signal group 528 is used to control the operation of a controlled circuit (not shown) such as an arithmetic unit and a register.

The DSP 590 includes a memory 561, an instruction pointer 563, an instruction decoder 570 and a control circuit 580. The memory 561 stores a plurality of instructions to be executed. Addresses in a range different from the range assigned to the memory 511 are assigned to the memory 561. For example, the memory 561 is assigned 1024 words from the address x'400 'to the address x'7FF'. The memory 561 reads the instruction stored in the address output from the instruction pointer 563 among the plurality of instructions. The instruction read from the memory 561 is supplied to the instruction decoder 570. Instruction decoder 570
Decodes the instruction read from the memory 561 and outputs "1" to the control signal 572 when the input instruction is "instruction for instructing the end of processing (ret instruction)", and otherwise In that case, “0” is output as the control signal 572. The control circuit 580 is the control circuit 52 of the CPU 540.
The control signal 526 is received from 0, and when the value of the control signal 526 is "1", the control signal 582 is set to "1". The instruction pointer 563 outputs the address of the instruction read from the memory 561. The instruction pointer 563 is the CPU
The address 518 is received from the instruction decoder 515 of 540, and the address 518 is held when the control signal 582 is "1".

The operation of the information processing apparatus of this embodiment having the above configuration will be described below.

The instruction pointer 513 normally increments the value held by it and outputs the address of the instruction read by the memory 511. The instruction read from the memory 511 is decoded by the instruction decoder 515. The instruction decoder 515 activates the control signal 516 when the input instruction is an instruction (call instruction) for instructing branch to a subroutine, and the memory 51 instructed together with the call instruction.
1 or the subroutine start address of the memory 561 is output to the address 518. For example, x'10 of the memory 511
When the instruction stored in the address 0'is the call x'200 'instruction, x'200' is output to the address 518.

The control circuit 520 checks the value of the address 518 when the control signal 516 is active, and outputs "1" to the control signal 523 and "0" to the control signal 526 if it is the address of the memory 511. Since the control signal 523 is "1", the instruction pointer 513 holds the content of the address 518. Further, the control circuit 580 outputs “0” as the control signal 582 because the control signal 526 is “0”.
For example, the instruction read from the memory 511 is called
When the address is x'200 ', since the address x'200' is the area of the memory 511, the instruction pointer 513 is x'2.
00 'is held and the instruction pointer 563 does not update the held content. The above operation is shown in FIG.

If the control signal 516 is active, the control circuit 520 checks the value of the address 518, and if it is the address of the memory 561, the control signals 522 and 523 are "0" and the control signal 526 is "1". Is output. The instruction pointer 513 stops updating because the control signal 522 is "0". Further, the control circuit 580 outputs “1” as the control signal 582 because the control signal 526 is “1”.
For example, the instruction read from the memory 511 is called
When it is x'500 ', the address x'500' is the area of the memory 561, so the instruction pointer 513 stops updating its value, and the instruction pointer 563 holds x'500 'and then changes to that value. Sequential memory 5 by adding 1
The address is output to 61, and the instruction stored in the memory 561 is executed. The above operation is shown in FIG.

When the instruction read from the memory 561 is an instruction (ret instruction) for instructing the end of processing, the instruction decoder 570 outputs "1" to the control signal 572, and the operation of the instruction pointer 563 is changed. Give instructions to stop.
The control circuit 520 outputs "1" as the control signal 522 when the control signal 572 is "1". Since the control signal 522 is "1", the instruction pointer 513 restarts updating its value.

As described above, the memory 511 and the memory 561
Addresses in different ranges are assigned to the memory 51 and the memory 51 depending on the start address of the subroutine indicated by a single call instruction.
By automatically switching the access to 1 and the access to the memory 561, it is possible to unify the calling procedure of the subroutine inside the CPU 540 and the calling procedure of the subroutine inside the DSP 590. cal
The start address of the subroutine indicated by the l instruction is the memory 51.
If the area is 1, the CPU 540 continues to operate.
When the start address of the subroutine indicated by the call instruction is the area of the memory 561, the same operation as the information processing apparatus of the first embodiment is performed. That is, after activating the processing of the DSP 590, the CPU 540 stops its operation and
After the processing of SP590 ends, the CPU 540 restarts its operation.

(Sixth Embodiment) The information processing apparatus of the sixth embodiment is c when compared with the information processing apparatus of the fifth embodiment.
This is a modification of the processing when the start address of the subroutine indicated by the all instruction is the area of the memory 561.
The information processing apparatus of this embodiment performs the same operation as that of the information processing apparatus of the second embodiment when the start address of the subroutine indicated by the call instruction is the memory area included in the DSP. That is, the CPU continues its operation even after the DSP processing is started, and after the DSP processing is completed, the CPU
Is a DSP by branching to a preset address
Recognize the end of processing in. FIG. 6 shows the configuration of the information processing apparatus of the sixth embodiment according to the present invention. The information processing device includes a CPU 640 and a DSP 590. C
The PU 640 and the DSP 590 are provided on the single chip 500.

In FIG. 6, the same components as those of the information processing apparatus shown in FIG. 5 are designated by the same reference numerals. The difference from the configuration of the information processing apparatus shown in FIG. 5 is that the instruction pointer 513 and the control circuit 520 are replaced by the instruction pointer 613 and the control circuit 620, respectively.

The CPU 640 includes a memory 511, an instruction pointer 613 and a control unit 612. Memory 51
The instruction read from 1 is supplied to the control unit 612. The control unit 612 controls the execution of the instruction read from the memory 511. The instruction pointer 613 outputs the address of the instruction to be read from the memory 511 according to the control signals 522, 523 and 623. Instruction pointer 6
In 13, an address value of an instruction to be read from the memory 511 is set. The instruction pointer 613 has the control signal 5
When 22 is "1", the value is updated by adding 1 and when the control signal 522 is "0", the updating of the value is stopped. When the control signal 523 is “1”, the content of the address 518 is held and the control signal 623 is held.
Is 1, the contents of the address 628 are retained.

Control unit 612 includes an instruction decoder 515 and a control circuit 620. The instruction decoder 515 is
The instruction read from the memory 511 is decoded, and the control signal 516 and the address 518 are generated according to the input instruction. The control circuit 620 generates the control signal 522, the control signal 523, the control signal 623, the address 628, the control signal 526, and the control signal group 528 according to the control signal 516, the address 518, and the control signal 572. The control signal group 528 is used to control the operation of a controlled circuit (not shown) such as an arithmetic unit and a register.

The operation of the information processing apparatus of this embodiment having the above-mentioned structure will be described below.

The difference from the operation of the information processing apparatus shown in FIG. 5 is that the instruction pointer 613 during the operation of the DSP 590.
Control and the instruction read from the memory 561 is ret
This is control of the instruction pointer 613 in the case of an instruction.

The control circuit 620 checks the value of the address 518 if the control signal 516 is active, and outputs "1" to the control signal 523 and "0" to the control signal 526 if it is the address of the memory 511. Since the control signal 523 is "1", the instruction pointer 613 holds the contents of the address 518. For example, when the instruction read from the memory 511 is call x'200 ', x'200'
Since the address is the area of the memory 511, the instruction pointer 6
13 holds x'200 ', and the instruction pointer 563 does not update the held content.

If the control signal 516 is active, the control circuit 620 checks the value of the address 518, and if it is the address of the memory 561, the control signal 522 is set to "1",
“0” is output to the control signal 523 and “1” is output to the control signal 526. The control signal 522 of the instruction pointer 613 is “1”
So keep working. For example, x ′ of the memory 511
When the instruction at address 100 'is call x'500', since the address at x'500 'is the area of the memory 561, the instruction pointer 613 keeps updating its value (x'1.
01 ', x'102' ,. . . ), Instruction pointer 563
Holds x'500 'and then adds 1 to that value to sequentially output addresses to the memory 561.
The instruction stored in 1 is executed.

When the control signal 572 is "1", the control circuit 620 outputs "1" to the control signal 623, and at the same time, the preset address 628 (for example, x'3F0 ').
Is output to the instruction pointer 613. Instruction pointer 613
Since the control signal 623 is "1", the address 628 is used as its held content.

In this way, the memory 511 and the memory 561 are
Addresses in different ranges are assigned to the memory 51 and the memory 51 depending on the start address of the subroutine indicated by a single call instruction.
By automatically switching the access to 1 and the access to the memory 561, it is possible to unify the calling procedure of the subroutine inside the CPU 540 and the calling procedure of the subroutine inside the DSP 590. cal
The start address of the subroutine indicated by the l instruction is the memory 51.
If the area is 1, the CPU 540 continues to operate.
When the start address of the subroutine indicated by the call instruction is the area of the memory 561, the same operation as the information processing apparatus of the second embodiment is performed. That is, the CPU 640 continues the operation even after the processing of the DSP 590 is activated, and the DS
After the processing of P590 is completed, the CPU 590 recognizes the completion of the processing of the DSP 590 by branching to the preset address.

Information such as which process of the DSP is to be activated in the above embodiment is stored in the memory 161, 561 or the like, and the program start addresses 124, 518 are stored.
However, this is not limited to the head address as long as it corresponds one-to-one with the process to be executed by the DSP 190, 590.

Further, although the callsp instruction or the like is used as the instruction for starting the processing to the DSP 190, 590 or the like,
It goes without saying that the description in the above embodiment is not limited to this.

Further, in the above-described embodiment, the CPU and the DS are
Although the information processing apparatus including the P has been described, the present invention is not limited to the CPU.
Is not limited to the combination of the DSP and the DSP. The present invention can be effectively applied when two or more processors of the same type or different types are integrated on a single chip.

[0087]

According to the present invention, the first CPU included in the CPU
A single activation instruction (calls) read from memory
(p instruction) sets the address of the instruction to be read by the second memory included in the DSP to a predetermined value. This allows the programmer to code a single callsp instruction when activating the processing on the DSP side from the CPU side. As a result, the programming effort is greatly reduced. Further, since the readability of the program is improved, it is easy to test, debug and reuse the program.

FIG. 13 shows an example of a procedure in which the CPU activates the processing of the DSP. (A) is a coding example in the case of the conventional information processing apparatus shown in FIG. 7, and (b)-(e) is a coding example in the case of the information processing apparatus of each Example of this invention.

Further, since the input / output port for connecting the CPU and the DSP is unnecessary, the CPU can start the processing of the DSP at high speed.

The operation of the CPU can be continued even after the processing of the DSP is activated. As a result, the CPU and the DSP operate in parallel, so that the processing can be executed more efficiently. In addition, a register for storing the notification of the end of processing of the DSP is provided, and an instruction for referring to the value of the register is executed to execute D
By monitoring the end of SP processing, D
It becomes possible for the CPU side to detect the end of the processing of the SP.

Further, a register for storing information relating to continuation / stop of the CPU operation is provided, and the continuation / stop of the CPU operation is switched according to the contents of the register to realize two functions with one instruction. It becomes possible.

Further, according to the present invention, a single start instruction (call) read from the first memory included in the CPU is used.
1st included in the CPU according to the address corresponding to the (instruction)
It is determined whether to access the memory or the second memory included in the DSP. When the first memory included in the CPU is to be accessed, the start instruction sets the address of the instruction to be read by the first memory included in the CPU to a predetermined value. When the second memory included in the DSP is to be accessed, D
The address of the instruction to be read by the second memory included in the SP is set to a predetermined value. As a result, the programmer does not use a different start instruction depending on whether the program to be executed is stored in the first memory of the CPU or the second memory of the DSP, and a single start instruction (call instruction) is used. Can be coded with. As a result, the programming effort is greatly reduced. Further, since the readability of the program is improved, it is easy to test, debug and reuse the program. Further, since the input / output port for connecting the CPU and the DSP is not required, the CPU can start the processing of the DSP at high speed.

The operation of the CPU can be continued even after the activation of the processing of the DSP. As a result, the CPU and the DSP operate in parallel, so that the processing can be executed more efficiently.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an information processing apparatus according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of an information processing apparatus according to a second embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of an information processing apparatus according to a third embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of an information processing apparatus according to a fourth exemplary embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of an information processing apparatus according to a fifth exemplary embodiment of the present invention.

FIG. 6 is a block diagram showing the arrangement of an information processing apparatus according to the sixth embodiment of the present invention.

FIG. 7 is a diagram showing a configuration of a conventional information processing device.

FIG. 8 is a diagram showing an operation of the information processing apparatus according to the first embodiment of the present invention.

FIG. 9 is a diagram showing an operation of the information processing apparatus according to the second embodiment of the present invention.

FIG. 10 is a diagram showing an operation of the information processing apparatus according to the third embodiment of the present invention.

FIG. 11 is a diagram showing an operation of the information processing apparatus according to the fifth embodiment of the present invention.

FIG. 12 is a diagram showing an operation of the information processing apparatus according to the fifth embodiment of the present invention.

FIG. 13 is a diagram showing a coding example of a procedure in which the CPU activates the processing of the DSP. (A) is a coding example in the case of a conventional information processing apparatus, (b) is a coding example in the case of the information processing apparatus of the first embodiment of the present invention, (c)
Is a coding example in the case of the information processing apparatus of the second and third embodiments of the present invention, (d) is a coding example in the case of the information processing apparatus of the fourth embodiment of the present invention, and (e) is the present invention. 13 is a coding example in the case of the information processing apparatus of the fifth and sixth embodiments of FIG.

[Explanation of symbols]

111, 161, 511, 561 memory 113, 163, 213, 413, 513 instruction pointer 120, 180, 220, 320, 420, 520, 6
20 control circuit 170, 515 instruction decoder 140, 240, 340, 540, 640 CPU 190, 590 DSP

Claims (14)

[Claims] 1. An information processing apparatus comprising a first processor and a second processor provided on a single chip, wherein the first processor includes a first memory for storing a plurality of instructions, and First instruction pointer means for designating an address of one instruction to be read out of the plurality of instructions stored in the first memory, and an instruction corresponding to the address designated by the first instruction pointer means for the first memory. First read means for reading from the first read means and first control means for controlling the execution of the instruction read by the first read means, and if the instruction is a single start-up instruction, the first instruction The operation of the pointer means is stopped or continued, and the information indicating the start instruction is added to the second information.
A second memory for storing a plurality of instructions, and one instruction to be read out of the plurality of instructions stored in the second memory. Second instruction pointer means for designating an address, second reading means for reading an instruction corresponding to the address designated by the second instruction pointer means from the second memory, and instruction read by the second reading means A second control means for controlling execution of the instruction, receiving information indicating the activation instruction from the first processor, and determining an address of an instruction designated by the second instruction pointer means according to the information indicating the activation instruction. An information processing apparatus comprising: a second control unit that sets a predetermined address. 2. The second control means stops the operation of the second instruction pointer means when the instruction read by the second reading means is a single end instruction, and Information indicating an end instruction is sent to the first processor, the first control means receives information indicating the end instruction from the second processor, and the first instruction pointer means of the first instruction pointer means receives the information indicating the end instruction. The information processing apparatus according to claim 1, which controls an operation. 3. The first control means stops the operation of the first instruction pointer means when the instruction read by the first reading means is the activation instruction, and the end In response to the information indicating the command, the first
The information processing apparatus according to claim 2, wherein the operation of the instruction pointer means is started. 4. The first control means continues the operation of the first instruction pointer means when the instruction read by the first reading means is the start-up instruction, and the end. The information processing apparatus according to claim 2, wherein the address of the instruction designated by the first instruction pointer means is set to a predetermined address according to information indicating the instruction. 5. The first processor further comprises storage means for storing information indicating the end instruction received from the second processor, and the first control means reads by the first reading means. If the executed instruction is a single branch instruction,
The information processing apparatus according to claim 2, wherein the operation of the first instruction pointer means is controlled according to the contents of the storage means. 6. The first processor further comprises storage means for storing information defining the operation of the first control means, and the first control means is operable to store the first control means in accordance with the contents of the storage means. The information processing apparatus according to claim 1, which controls the operation of the 1-instruction pointer means. 7. An information processing device comprising a first processor and a second processor provided on a single chip, wherein the first processor is a first memory for storing a plurality of instructions. A first memory to which addresses in a first range are assigned, first instruction pointer means for designating an address of one instruction to be read out of the plurality of instructions stored in the first memory, and the first memory It is provided with first reading means for reading the instruction corresponding to the address designated by the instruction pointer means from the first memory, and first control means for controlling the execution of the instruction read by the first reading means. The second processor is a second memory that stores a plurality of instructions, and a second memory to which an address in a second range different from the first range is assigned, and the second memory are stored in the second memory. He said Second instruction pointer means for designating an address of one instruction to be read out of the instruction, second reading means for reading out an instruction corresponding to the address designated by the second instruction pointer means from the second memory, Second control means for controlling the execution of the instruction read by the two reading means, and the instruction read by the first reading means is a single activation instruction in the first control means. In this case, the predetermined address corresponding to the start command is the address of the first range and the second address.
Which address is included in the range, and when the predetermined address corresponding to the start instruction is included in the address in the first range, the instruction designated by the first instruction pointer means The address is set to the predetermined address corresponding to the start instruction, and the operation of the first instruction pointer means is stopped when the predetermined address corresponding to the start instruction is included in the addresses in the second range. Alternatively, the information indicating the activation instruction is transmitted to the second processor, and the second control means receives the information indicating the activation instruction from the first processor, and in response to the information indicating the activation instruction. An information processing apparatus for setting an address of an instruction designated by the second instruction pointer means to the predetermined address corresponding to the activation instruction. 8. The second control means stops the operation of the second instruction pointer means when the instruction read by the second reading means is a single end instruction, and Information indicating an end instruction is sent to the first processor, the first control means receives information indicating the end instruction from the second processor, and the first instruction pointer means of the first instruction pointer means receives the information indicating the end instruction. The information processing device according to claim 7, which controls an operation. 9. The first control means stops the operation of the first instruction pointer means when the instruction read by the first reading means is the activation instruction, and the end operation. In response to the information indicating the command, the first
The information processing apparatus according to claim 8, wherein the operation of the instruction pointer means is started. 10. The first control means continues the operation of the first instruction pointer means when the instruction read by the first reading means is the start-up instruction, and ends the operation. The first according to the information indicating the command
The information processing apparatus according to claim 8, wherein the address of the instruction designated by the instruction pointer means is set to a predetermined address. 11. A method of controlling an information processing apparatus comprising a first processor and a second processor provided on a single chip, wherein the first processor provides one instruction out of a plurality of instructions. And a step of determining whether the instruction is a single activation instruction, and if the instruction is determined to be the activation instruction, stop or continue the operation of the first processor. And sending information indicating the activation instruction to the second processor, receiving information indicating the activation instruction from the first processor, and controlling the operation of the second processor according to the information indicating the activation instruction And a control method including a step of performing. 12. The control method includes the steps of providing one instruction of a plurality of instructions in the second processor, determining whether the instruction is a single end instruction, and the instruction. Is determined to be the end instruction, the step of stopping the operation of the second processor and sending information indicating the end instruction to the first processor; and the end instruction from the second processor. 12. The control method according to claim 11, further comprising the step of receiving information indicating that the end instruction is received, and controlling the operation of the first processor according to the information indicating the end instruction. 13. A method of controlling an information processing apparatus comprising a first processor and a second processor provided on a single chip, wherein the first processor is assigned addresses in a first range. The second processor has a second memory to which addresses in a second range different from the first range are assigned, and the second processor is stored in the first memory. Providing one of the plurality of instructions, determining whether the instruction is a single start instruction, and determining that the instruction is the start instruction, A step of determining whether the predetermined address corresponding to the start command is included in the address of the first range or the address of the second range; and the predetermined address corresponding to the start command is set to the first address. If it is determined to be included in the address range of According to the step of controlling the operation of the first processor, and when it is determined that the predetermined address corresponding to the start instruction is included in the addresses of the second range, the operation of the first processor is performed. Stopping or continuing and sending information indicating the activation instruction to the second processor; receiving information indicating the activation instruction from the first processor, and the second processor according to the information indicating the activation instruction Controlling the operation of the. 14. The control method comprises: providing one of a plurality of instructions stored in the second memory; determining whether the instruction is a single end instruction. If the instruction is determined to be the end instruction, the operation of the second processor is stopped, and information indicating the end instruction is sent to the first processor; The control method according to claim 13, further comprising the step of receiving information indicating the end instruction and controlling the operation of the first processor according to the information indicating the end instruction.