JPH0965154A - Color picture transfer device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently utilize a picture transfer means and to accelerate a transfer speed both in the case of point sequentially transferring pictures to point sequential picture input/output equipments and in the case of surface sequentially transferring the pictures to surface sequential picture input/output equipments. SOLUTION: Inside a picture storage part 12, picture data are stored so as to make bus transfer burst length N×M words be continuous addresses for respective color components. A point sequential picture input/output part 13 is provided with a rearrangement function between point sequential data and data for the respective bus transfer burst length × M words for the respective color components and transfers the picture data after rearrangement through a picture transfer bus 11 to the picture storage part 12. Also, the picture data are received from the picture storage part 12 through the picture transfer bus 11, rearranged to the point sequential picture data and then, utilized or outputted to an outside. A surface sequential picture input/output part 14 performs input and output in the form of the data to be transferred.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a color image transfer device for transferring a color image.

[0002]

2. Description of the Related Art FIG. 16 is a block diagram showing an example of a conventional image transfer device. In the figure, 61 is an image transfer bus, 62 is an image storage unit, and 63 and 64 are image input / output circuits. In the image transfer device shown in FIG. 16, an image is transferred between the image input / output circuit 63 or 64 and the image storage unit 62 using the image transfer bus 61.

The image input / output circuits 63 and 64 accept image data generated, input from the outside, or sent via the image transfer bus 61. The image storage unit 62 stores image data. The image transfer bus 61 includes an image storage unit 62 and an image input / output circuit 6.
Image data is transferred to and from the terminals 3 and 64.

FIG. 17 is an explanatory diagram of an example of image data of a color image. Generally, a color image has data of a plurality of color components for each pixel. Then, as shown in FIG. 17, each color component is recorded or transmitted in raster order. In the color image shown in FIG. 17, the color components A,
B, C, ..., Z exist and are recorded in raster order for each color component.

When the above-mentioned image input / output circuits 63 and 64 perform such input / output of color images or transfer them via the image transfer bus 61 and store them in the image storage unit 62, each color of the color image is input. There are two methods for transmitting and accumulating components, that is, point order and plane order. FIG. 18 is an explanatory diagram of dot order and plane order. 18 (1) and (3) shows 1
6 illustrates a method of accessing each pixel. FIG.
8 (2) and 8 (4) illustrate a method of simultaneously accessing a plurality of devices. Here, it is assumed that the color components of the color image are three types A, B, and C.

The plane order method is shown in FIG. 18 (1) or FIG.
This is shown in (2). In the plane order method, first, the color component A of all pixels is accessed, and then the color component B is accessed. Furthermore, the color component C of all pixels is accessed before the color component C is accessed.

The point-sequential method is shown in FIG. 18 (3) or FIG.
It is shown in (4). In the dot-sequential method, for example, FIG.
As shown in (3), in the method of accessing one pixel at a time, the color components of one pixel are sequentially arranged, for example, ABCABC ...
・ It is accessed in the order of. Further, as shown in FIG. 18 (4), in the method of simultaneously accessing a plurality of pixels, each color component ABC of one pixel is simultaneously accessed.

FIG. 19 is a block diagram showing an example of a conventional image input / output circuit. In the figure, 71 is an image input unit,
72 is an image processing circuit, and 73 is an image output unit. FIG.
The image input / output circuit shown in "Fuji Xerox Technical Report", No. It is a simplified version of Figure 2.9 on page 7, 1992, page 33.

An image is input from the image input section 71. The input image is normally output to the image output unit 73 through the image processing circuit 72. When an image is input to the image input / output device from an external device, images of three colors L ^* , a ^* , and b ^* are simultaneously input in a 24-bit width. in this case,
This corresponds to FIG. 18 (4) described above. When an image is output from this image input / output device to an external device, L
^{The *} color image is output with an 8-bit width, then a ^* , and then b ^* . In this case, FIG.
It corresponds to (1). That is, when inputting image data to this image input / output device, it must be in dot order with a width of 24 bits. When the image data is output from this image input / output device, the plane order is 8 bits wide.

In the conventional image transfer device shown in FIG.
When the images are stored in the image storage unit 62, either the point order or the plane order is used.

Next, the operation of the image transfer bus 61 shown in FIG. 16 will be described. Hereafter, the bus width will be referred to as a word. FIG. 20 is an explanatory diagram of the bus transfer method. In the image transfer bus 61, as shown in FIG. 20, one word of data is transferred in one clock. When accessing consecutive addresses in the image storage unit 62, it is only necessary to specify the first address and
Words can be transferred with continuous clocks. However, N is an integer here. This continuous transfer
Hereinafter referred to as burst transfer. In the case of transferring pixels with discontinuous addresses, this burst transfer is impossible, and it becomes necessary to newly set the address, and the transfer speed becomes slow.

Consider a case where an image is transferred from the image storage unit 62 of FIG. 16 to the image input / output units 63 and 64 using the image transfer bus 61. FIG. 21 is an explanatory diagram of a case where color images are accumulated and transferred in plane order, and FIG. 22 is an explanatory diagram of a case where color images are accumulated and transferred in dot order. Accumulation in face-to-face order,
When transferring, as shown in FIG. 21, the image can be transferred by accumulating an image for each color component in the image accumulating unit 62 and repeating burst transfer for each color component.

Further, when accumulating and transferring in point order,
As shown in FIG. 22, the image storage section 62 stores image data of each color component for each pixel, and burst transfer can be repeated for each pixel for transfer. If the total bit width of the image data of each color component of one pixel does not match the word, dummy data may be packed and transferred, as indicated by X in FIG.

In the prior art as described above, as the image input / output circuits 63 and 64, when a circuit for performing face-order input / output and a circuit for performing point-order input / output are present at the same time,
The following problems occur.

First, the images are stored in the image storage section 62 in the plane order as shown in FIG. 21, and the images are transferred to the image input / output circuit in the point order in the point order as shown in FIG. In this case, in order to collect the image data of each color component, it is necessary to access the image storage unit 62 and transfer the image data,
Since burst transfer is not possible, the transfer speed will drop.

In the case where images are stored in the image storage unit 62 in point order and the images are transferred to the image input / output circuit in point order in point order, further, as shown in FIG. If the total bit width of the image data of each color component of 1 pixel does not match the word width, the dummy data is packed and transferred, so that the bus is wastefully used for the dummy data. Bus utilization efficiency will decrease.

Further, the images are accumulated in the image accumulating section 62 in the point order as shown in FIG. 22, and the images are transferred to the plane order image input / output circuit in the plane order as shown in FIG. In such a case, it is necessary to access the pixels one by one and transfer the data one by one, and since the burst transfer cannot be performed, there is a problem that the transfer speed is lowered.

[0018]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned circumstances, and is for transferring images in a dot order to a dot-sequential image input / output device and for a screen-sequential image input / output device. It is an object of the present invention to provide a color image transfer device in which the image transfer means is efficiently used and the transfer speed is improved when the images are transferred in order.

[0019]

According to a first aspect of the present invention, in a color image transfer device for transferring a color image having a plurality of color components, an image capable of burst transfer of information for each predetermined transfer unit. A transfer means, an image storage means for arranging and storing each color component of the color image in an integer multiple of the transfer unit of the image transfer means, and an address of the image storage means to be subjected to the burst transfer are generated. The image processing apparatus includes an image address generating means, a dot-sequential image input / output means, and a plane-sequential image input / output means.
Image data holding means for holding an image which has been transferred using the image transfer means or which is to be transferred and which is arranged at an integer multiple of the transfer unit of the image transfer means, a dot-sequential image and the image An image data rearranging means for rearranging the image data between the images arranged at every integer multiple of the transfer unit of the transfer means is provided.

According to a second aspect of the present invention, in the color image transfer apparatus according to the first aspect, the image storage means is
Each color component of the color image is arranged in every integer multiple of the image transfer unit of the image transfer means, and is arranged in an address space wider than the address space of the image transfer means. It is characterized by having a window address register for holding a part thereof, and an address generating means for generating an address for the burst transfer from an address obtained from the image address generating means and the contents of the window address register. .

According to a third aspect of the present invention, in the color image transfer apparatus according to the second aspect, the image storage means has an integral multiple of the transfer unit × the number of color components + the number of invalid pixels of the image transfer means. It is characterized by being narrower than the address space.

According to a fourth aspect of the invention, in the color image transfer apparatus according to the first aspect, the image storage means is
Each color component of the color image is arranged in an integral multiple of the image transfer unit of the image transfer means, and the address space width of the image transfer means is divided by the number of color components, and a dedicated address space is allocated to each color component. It is characterized by.

According to a fifth aspect of the present invention, in the color image transfer apparatus according to the first aspect, the image address generating means includes an image address holding means, an address increase number holding means, and the image address holding means. An address adding means for adding the content and the content of the address increment number holding means and giving it to the image accumulating means is provided, and the address increment number holding means, when performing transfer to and from the point sequential input / output means. It is characterized in that the transfer unit length of the image transfer means is held and the address difference up to the next same color component is held when the transfer to the plane sequential input / output means is carried out.

According to a sixth aspect of the invention, in the color image transfer apparatus according to the fifth aspect, the image storage means is
Each color component of the color image is arranged and stored for each transfer unit of the image transfer means, and the address increase number holding means, when performing transfer with the plane sequence input / output means, the next same color It is characterized by holding the image transfer unit x the number of color components, which is the address difference up to the component.

[0025]

According to the invention described in claim 1, the color components of the color image are arranged and stored in the image storage means in an integer multiple of the transfer unit of the image transfer means, and the images are transferred in plane order. In this case, the image address generating means calculates the image address so that the same color components are continuously transferred in the plane-sequential image input / output device. When the images are input and output in dot order, the images are transferred in the order in which they are stored in the image storage means. At this time, in the dot-sequential image input / output means, the image data rearranging means rearranges the image data between the dot-sequential images and the images arranged at integer multiples of the transfer unit of the image transfer means. In this way, the images in dot order are rearranged in a format to be stored in the image storage means and then transferred, and the transferred images are rearranged in dot order. As a result, transfer can be performed in the same manner regardless of whether the image is a plane order image or a dot order image. Further, since it is stored in the image storage means for each transfer unit and transferred by the image transfer means for each transfer unit, for example, it is not necessary to send dummy data as shown in FIG. It can be used efficiently and the transfer speed can be improved.

According to the second aspect of the present invention, in the image storage means, each color component of the color image is arranged in an integral multiple of the image transfer unit of the image transfer means, and the address space of the image transfer means is set. Is also located in a large address space. In this case, it is not possible to access only by the address given to the image storage means via the image transfer means,
The address of the image storage means or a part of the address is held in the window address register, and the address generation means generates an address for burst transfer from the address obtained through the image transfer means and the contents of the window address register. . As a result, even an image transfer unit having an address space narrower than the address space of the image storage unit can transfer an image having a large amount of data.

According to the invention of claim 3, according to claim 2,
In the invention described in, the transfer unit is an integral multiple of x the number of color components +
The image data is arranged so that the number of invalid pixels is smaller than the address space of the image transfer means. With this, it is possible to transfer the image data of an integral multiple of the transfer unit for all the color components without resetting the window address register. The number of settings can be reduced, the load can be reduced, and the transfer speed can be improved.

According to the invention described in claim 4, in the image storage means, each color component of the color image is arranged in every integer multiple of the image transfer unit of the image transfer means, and the address space of the image transfer means is set. Divide by the number of color components and allocate a dedicated address space to each color component. Thereby, for example, even when the address space of the image storage means is wider than the address space of the image transfer means, access is performed within the address space width of the image transfer means as much as possible in the case of dot-sequential image transfer. It is possible to reduce the load of address setting by preventing the address space from being set frequently.

According to the invention described in claim 5, the image address generating means can generate the address only by adding the contents of the image address holding means and the contents of the address increment number holding means. At this time, the address increment number holding means holds the transfer unit length of the image transfer means when performing the transfer with the point order input / output means, and transfers with the plane order input / output means. When performing, the address difference up to the next same color component may be held.

According to the sixth aspect of the present invention, when the data is transferred to and from the plane-order input / output means, the address increment holding means stores the image transfer unit which is the address difference up to the next same color component. By holding the number of × color components, the added value can be made constant.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 shows a first embodiment of a color image transfer apparatus of the present invention.
2 is a schematic diagram of an example of an image storage unit, FIG. 3 is a configuration diagram of an example of a point-sequential image input / output unit, and FIG. 4 is a similar plane-sequential image input / output unit. It is a block diagram of an example of a part. In the figure, 11 is an image transfer bus, 12 is an image storage unit, 13 is a point sequence image input / output unit, 14 is a plane sequence image input / output unit, 21 is an image address, 22 is image data, 23 is an image memory, and 31 is an image memory. An image address, 32 is an image address generation circuit, 33 is image data, 34 is an image data buffer, 35 is an image data generation / use circuit, 36 is an image data rearrangement circuit, 41 is an image address, 42 is an image address generation circuit, 43 Is image data, and 44 is an image data generation / use circuit.

The image transfer bus 11 has a 1-word width, and as described with reference to FIG.
Burst transfer is possible in which word data is transferred and N words are continuously transferred.

The image storage unit 12 has an internal image memory 23.
have. The image memory 23 uses the image address 21 provided from the image transfer bus 11 during burst transfer.
The image data 22 of N words transferred from is sequentially stored, or N from the given image address 21 is stored.
The word image data 22 is sequentially read and output.

FIG. 5 is an explanatory diagram of an example of the image data storage method in the first embodiment of the present invention. As shown in FIG. 5, the image data is stored in the image memory 23 such that the bus transfer burst length N × M words are consecutive addresses for each color component. Here, M is an integer variable. It does not matter which color component is stored at any address. In addition, it is assumed that the blank portion between different color components is filled with invalid data.

Returning to FIGS. 1 to 4, the dot-sequential image input / output unit 13
Generates image data in dot order or receives image data in dot order from the outside, rearranges the image data, and then transfers the image data to the image storage unit 12 via the image transfer bus 11. In addition, the image data is received from the image storage unit 12 via the image transfer bus 11 and is used after being rearranged into the dot order image data, or is output to the outside.

As shown in FIG. 3, the dot-sequential image input / output unit 13 has an image data buffer 34, an image data generating / using circuit 35, and an image data rearranging circuit 36. The image data buffer 34 stores the image data 33 to be transferred via the image transfer bus 11 or the image transfer bus 11
The image data 33 transferred via is held. The image data generation / use circuit 35 generates image data in a dot order or receives the image data from the outside, and the image transfer bus 11
The image data, which is transferred via the image data and is rearranged in dot order by the image data rearrangement circuit 36, is used or output to the outside. The image data rearranging circuit 36 transfers the image data in dot order and the image storage unit 12 by transferring the image data via the image transfer bus 11.
Converts between image data in the format to be stored in.

FIG. 6 is an explanatory diagram of an example of rearranging image data in the first embodiment of the present invention. The image data stored in the image storage unit 12 from the image data buffer 33 via the image transfer bus 11, or the image storage unit 1
The image data stored in No. 2 and transferred to the image data buffer 33 via the image transfer bus 11 is, as shown in FIG. 6A, data for each bus transfer burst length × M words for each color component. Is. On the other hand, the image data in the image data generation / use circuit 35 is dot-order image data as shown in FIG. The image data rearranging circuit 36 converts the image data shown in FIG.
Rearrange the image data in the order of dots shown in
The image data in the dot order shown in FIG. 6 (2) is rearranged into the image data shown in FIG. 6 (1).

Returning to FIGS. 1 to 4, the plane-sequential image input / output unit 14
Generates image data in the plane order or receives image data in the plane order from the outside and transfers the image data to the image storage unit 12 via the image transfer bus 11. Further, image data is received from the image storage unit 12 via the image transfer bus 11. Since the received image data is the image data in the plane order, it can be used as it is or output to the outside.

The plane image input / output unit 14 has an image data generation / use circuit 44, as shown in FIG. The image data generation / use circuit 44 generates image data in a plane order or receives it from the outside, transfers the image data 43 via the image transfer bus 11, and the image data transferred via the image transfer bus 11. 43 is used or output to the outside.

In this embodiment, the address generation circuit 32,
42 are provided in the dot sequence image input / output unit 13 and the plane sequence image input / output unit 14, respectively. Address generation circuit 3
2 operates at the time of data transfer with the dot-sequential image input / output unit 13 to generate and output an image address 31 to be given to the image memory 23 in the image storage unit 12. Further, the address generation circuit 42 operates at the time of data transfer with the plane-sequential image input / output unit 14 and operates in the image memory 23 in the image storage unit 12.
The image address 41 to be given to is generated and output.

The operation of the first embodiment of the present invention will be described below. When the image is transferred from the dot-sequential image input / output unit 13 to the image storage unit 12, the image data generating / creating circuit 35 inputs the image data in the dot order to the image data rearranging circuit 36, and as shown in FIG. From the point order shown in Fig. 6 (1)
As shown in, each color component has a bus transfer burst length N × M (M
Is an integer) The words are rearranged so as to be arranged for each word and stored in the image data buffer 34. Then, the rearranged image data in the image data buffer 34 is burst-transferred via the image transfer bus 11. Before the start of each burst transfer, the address generation circuit 32 generates an address of the image storage unit 12 for storing,
The image address 21 is stored in the image memory 23 in the image storage unit 12.
Give as.

From the image storage unit 12 to the dot-sequential image input / output unit 13
When the image data is transferred to, the burst transfer is performed in the order of being stored in the image storage unit 12. The transferred image data is input to the dot-sequential image input / output unit 13 and stored in the image data buffer 34. Image data sorting circuit 36
As shown in FIG. 6 (1), the state in which the color components are arranged for each bus transfer burst length N × M (M is an integer) words is changed to the dot-order image data shown in FIG. 6 (2). And input to the image data generation / use circuit 35. Before the start of each burst transfer, the address generation circuit 32 generates the address of the image storage unit 12 in which the image data to be transferred is stored, and supplies it as the image address 21 of the image memory 23 in the image storage unit 12. .

The plane image input / output unit 14 to the image storage unit 12
When the image data is transferred to, the image in the plane order is burst transferred from the image data generation / use circuit 44. Before the start of each burst transfer, in the address generation circuit 42,
Generate the address of the image storage unit 12 for the next storage,
The image address 21 is stored in the image memory 23 in the image storage unit 12.
Give as.

From the image storage unit 12 to the plane order image input / output unit 14
When the image data is transferred to, the address generation circuit 42 generates the address of the image storage unit 12 in which the image data to be transferred next is stored before the start of each burst transfer. Burst transfer is performed using this address.

FIG. 7 is a partial block diagram showing a concrete example of the dot-sequential image input / output unit 13 in the first embodiment of the present invention.
In the figure, the same parts as those in FIG. 3 are designated by the same reference numerals. 5
Reference numeral 1 is a color switching circuit, 52 is a FIFO, and 53 is a pixel buffer circuit. Here, the case where the number of colors is 3 is shown. The bus width of the image transfer bus 11 is 32 bits, and for burst transfer, 32 bits are 1 word,
Words shall be transferred in succession. Further, it is assumed that the image data of each color component is composed of 8 bits.

The FIFO 52 is an 8-bit (= 1 byte) wide FIFO memory provided for each color component.
Each FIFO 52 has a capacity of at least the burst transfer length of the image transfer bus 11, that is, 32 bytes (4 bytes × 8 words). The color switching circuit 51 selects the FIFO 52 corresponding to the color component to be transferred. FIFO
A pixel buffer circuit 53 for synchronizing the input and output of the three FIFOs 52 is provided between 52 and the image data generation / use circuit 35. Here, the three colors are synchronized, and 24-bit image data is input / output to / from the image data generation / use circuit 35.

From the dot-sequential image input / output unit 13 to the image storage unit 12
In the case of the transfer to, the 24-bit (8 bits × 3 colors) image data is transferred from the image data generation / use circuit 35 to the pixel buffer circuit 53. In the pixel buffer circuit 53, each color component is decomposed into 8 bits and is input to the FIFO 52 corresponding to each color component.

Image data of at least 32 pixels is used for each F
When input to the IFO 52, burst transfer for each color component is possible. The color switching circuit 51 is a FIFO
Select 52. The image data of the color component is sequentially read from the selected FIFO 52 and is passed to the image transfer bus 11. In the image transfer bus 11, when 4 bytes are read, this is set as 1 word, and 8 words are burst-transferred. That is, 32 bytes are burst-transferred from the selected FIFO 52. When the FIFO 52 has a capacity of 32 × M bytes, this burst transfer can be continuously performed M times.

When the transfer for one color component is completed, the color switching circuit 51 selects the next FIFO 52,
Similarly, the image data in the selected FIFO 52 is burst-transferred. In this way, for all the FIFOs 52, the color switching circuits 51 are sequentially switched to perform burst transfer.

From the image storage unit 12 to the dot-sequential image input / output unit 13
Image transfer bus 11 for each word
The image data transferred via the image data is decomposed into 8 bits each and sequentially passed to the color switching circuit 51. The color switching circuit 51 selects the FIFO 52 according to the color component of the transferred image data. The burst-transferred image data of 8 words is sequentially input to the selected FIFO 52. When the FIFO 52 has a capacity of 32 × M bytes, this burst transfer can be continuously performed M times. When burst transfer is completed for one color component, F corresponding to the next color component to be transferred
The IFO 52 is selected by the color switching circuit 51, and the image data burst-transferred in the same manner is sequentially input to the selected FIFO 52. In this way, all the color components are input to the corresponding FIFO 52.

The pixel buffer circuit 53 includes each FIFO 52.
Image data of 8 bits each is read out from each of them, and thereby 24-bit image data for one pixel is created. Then, the created 24-bit image data is passed to the image data generation / use circuit 35. In this way, the image data stored in the image storage unit 12 is converted into dot-order image data and passed to the image data generation / use circuit 35.

Conventionally, in the case of transferring the image data in the dot order as described above, 8-bit dummy data is added to 24-bit image data for one pixel to obtain a 32-bit image as 32-bit data. The transfer was performed via the transfer bus 11. However, in the present invention, since the transfer is performed using the entire 32 bit width of the image transfer bus 11 as described above, the image transfer bus 11 can be effectively used and the transfer speed can be improved.

In the case of this specific example, since every 32 bytes are transferred, the lower 5 bits can be configured not to be transferred as an address given to the image storage section 12. In this case, it is possible to expand the accessible address space 32 times by using 5 bits which are not transferred as the upper address.

Next, the second color image transfer device of the present invention will be described.
An example will be described. In the first embodiment described above,
The addresses generated by the address generation circuits 32 and 42 are given to the image storage unit 12 via the image transfer bus 11.
At this time, the space accessible by the address given to the image storage unit 12 via the image transfer bus 11 may be smaller than the total address space of the image storage unit 12. For example, the image storage unit 12 via the image transfer bus 11
There are 2 spaces accessible by the address given to
If the total address space of the image storage unit 12 is 256 megabytes, the image transfer bus 11
Only a part of the image storage unit 12 can be accessed only by the address obtained via the. The second embodiment shows a configuration effective in such a case. Hereinafter, an address space (bus input / output address space) accessible by an address obtained via the image transfer bus 11 is called a window.

FIG. 8 is an explanatory diagram of windows in the second embodiment of the color image transfer apparatus of the present invention. As shown in FIG. 8, a part of the total image memory address space becomes a window. If the top address of the window is the window address, the image transfer bus 1
It is a space that can be accessed by an address obtained via 1. By arbitrarily setting the window address, it is possible to set the window in an arbitrary portion of the total image memory address space. In the second embodiment, the window address is held by the image storage unit 12, and the window address can be set arbitrarily, so that the total image memory address space can be accessed.

The configuration of the second embodiment of the color image transfer apparatus of the present invention is the same as the first embodiment except for the image storage section 12.
This is the same as the embodiment. FIG. 9 is a block diagram showing an example of the image storage section in the second embodiment of the color image transfer apparatus of the present invention. In the figure, the same parts as those in FIG. Reference numeral 24 is an address adder, 25 is a window address register, and 26 is an image address. The window address register 25 holds the window address shown in FIG. The value held at this time may be the entire address of the image memory 23 or only a part of the higher order.

The address adder 24 generates an image address 26 to be given to the image memory 23 from the value of the window address register 25 and the image address 21 given from the image transfer bus 11. At this time, if the window address register 25 holds the entire address for accessing the image memory 23, the address adder 24
Simply needs to add. When the window address register 25 holds a part of the address, the necessary bit shift or the like is performed and then the addition is performed.

In this way, the address in the image memory 23 can be designated by the address in the window obtained via the image transfer bus 11 and the value of the window address register. Although not explicitly shown in FIG. 3 and FIG. 4, in the dot-sequential image input / output unit 13 and the plane-sequential image input / output unit 14, is a circuit for designating a window address provided separately? Alternatively, it is provided in the address generation circuits 32 and 42, and the window address is transferred to the window address register 25 in advance.

FIG. 10 is an explanatory diagram showing an example of the image data storage system in the second embodiment of the color image transfer apparatus of the present invention. In the second embodiment, the image data in the window can be accessed without resetting the window address register 25. Therefore, as shown in FIG. 10, the bus transfer burst length N × M × the number of color components + the number of invalid pixels is limited to the window length or less so that the color components in the same pixel fall within the same window. Here, it is assumed that the blank portions between different color components are filled with invalid pixels.

By storing the image data in the image storage unit 12 in this way, particularly in the transfer with the dot-sequential image input / output unit 13, the image of the number of pixels transferred by the bus transfer burst length N × M words is obtained. Data can be transferred without changing the window address register. Therefore, the number of window address conversions can be reduced to reduce the load and improve the transfer speed.

FIG. 11 is an explanatory diagram of another example of the image data storage system in the second embodiment of the color image transfer apparatus of the present invention. In this example, the width of the window is divided into the number of color components, and a dedicated window is assigned to each color component.
In this case, each color component may be accumulated in the page order for each page, or may be accumulated continuously by an integral multiple of the distributed window width. Even in this case, since the image data of all color components can be transferred without changing the window, it is possible to reduce the number of conversions of the window address especially in the transfer with the dot-sequential image input / output unit 13. it can.

In the case of this example, an independent transfer mechanism for the number of colors is used, and the transfer mechanism to be used depends on which of the distributed windows the value of the image address 21 obtained from the image transfer bus 11 is included in. You can switch. Alternatively, the image address 21 obtained from the image transfer bus 11
The address adder 24 may calculate the image address 26 depending on which of the distributed windows the value of is included in. At this time, the distributed window address is
For example, it is possible to use various methods such as having window address registers for the number of colors or performing address calculation with one window address register and an offset value.

Next, the third embodiment of the color image transfer device of the present invention will be described.
An example will be described. The third embodiment shows an example in which the address generation circuits 32 and 42 of the first embodiment described above are configured by an address adder, an address register, and an address increment number register. In the first embodiment, the address generation circuits 32 and 42 are connected to the dot-sequential image input / output unit 1
3 and the plane-sequential image input / output unit 14 are provided, the configuration of the third embodiment differs from that of the first embodiment.

FIG. 12 is a block diagram showing an example of the dot-sequential image input / output unit in the third embodiment of the color image transfer apparatus of the present invention, and FIG. It is a figure. In the figure, parts similar to those in FIGS. 3 and 4 are designated by the same reference numerals, and description thereof will be omitted. 37 and 45 are address adders, 38 and 46 are address registers, 39 and 47
Is an address increment register.

The dot-sequential image input / output unit 13 is provided with an address adder 37, an address register 38, and an address increment number register 39. The address register 38 has
The image address from the previous transfer is stored. The address difference with the next color component to be transferred is stored in the address increment number register 39. The address adder 37 calculates the sum of the value of the address register 38 and the value of the address increment number register 39, and generates the image address 31.

The plane image input / output unit 14 is provided with an address adder 45, an address register 46, and an address increment number register 47. In the address register 46,
The image address from the previous transfer is stored. The address increment number register 47 stores the address difference up to the next same color component. The address adder 45 calculates the sum of the value of the address register 46 and the value of the address increment number register 47 to generate the image address 41.

FIG. 14 is an explanatory diagram showing an example of an image data storage system in the third embodiment of the color image transfer apparatus of the present invention. In the image memory 23 of FIG. 2, as shown in FIG. 14, the respective color components are accumulated so as to be arranged at continuous addresses by the length of the bus transfer burst length N × M words. Here, M is an integer. Then, different color components are arranged for each length of the bus transfer burst length N × M words. The order of each color component is fixed.

Next, the third embodiment of the color image transfer apparatus of the present invention will be described.
An example of the operation in this embodiment will be described. When transferring images from the dot-sequential image input / output unit 13 to the image storage unit 12,
An image in dot order is input from the image data generating / using circuit 35 to the image data rearranging circuit 36, and as shown in FIG. 6, each color component is in the bus transfer burst length N × M (M is an integer) word. Rearrange as if you were lining up. The image data resulting from the rearrangement is burst-transferred to the image transfer bus 11. In the address increment number register 39,
The address difference with the next color component to be transferred is accumulated.
Prior to each burst transfer, the address adder 3
7 calculates the sum of the value of the address register 38 in which the previous address is stored and the value of the address increment number register 39, and generates the image address 31 for storing the transferred image data in the image storage unit 12. To do.

From the image storage unit 12 to the dot-sequential image input / output unit 13
When transferring images to, the burst transfer is performed in the order in which they are stored in the image storage unit 12. The image data is transferred to the dot-sequential image input / output unit 13 and input to the image data rearranging circuit 36. Then, as shown in FIG. 6, from the state where each color component is arranged for each bus transfer burst length N × M (M is an integer) words, the images are rearranged in a dot order image and input to the image data generation / use circuit 35. To be done. The address increment number register 39 stores the address difference with the next color component to be transferred. Prior to the burst transfer, the address adder 37 calculates the sum of the value of the address register 38 in which the previous address is stored and the value of the address increment number register 39, and determines the image address of the image storage unit 12 to be transferred. appear.

From the plane image input / output unit 14 to the image storage unit 12
When the image is transferred to, the image in the plane order is burst transferred from the image data generation / use circuit 44. The address increment number register 47 stores the address difference up to the next same color component. Prior to the burst transfer, the address adder 45 calculates the sum of the value of the address register 46 in which the previous address is stored and the value of the address increment number register 47, and stores the transferred image data in the image storage unit 12. An image address 41 for generating the image is generated.

From the image storage section 12 to the plane order image input / output section 14
When transferring an image to the address increase number register 47
The address difference up to the next same-color component is stored in, and before the burst transfer, the sum of the value of the address register 46 and the value of the address increment number register 47 in which the previous address is stored is calculated and transferred. The image address of the image storage unit 12 is generated. Then, burst transfer is performed using this address.

Here, when the data is transferred to and from the plane-sequential image input / output unit 14, the number of increased addresses can be fixed by setting M to 1. FIG. 15 is an explanatory diagram of a specific example of the image data storage system in the third embodiment of the color image transfer apparatus of the present invention. In FIG. 15 (1), M =
2 shows the case, and FIG. 15 (2) shows the case where M = 1.

As shown in FIG. 15 (1), when M = 2, it is considered to transfer in the plane order. At the time of transfer, 4 bytes are transferred as 1 word, and the bus transfer burst length is N words. The data transferred in one burst transfer is N × 4 = b bytes. When image data is stored in the image storage unit 12 as shown in FIG. 1 (1), for example, in order to transfer an image of the color component A, continuous 2N words of the color component A are burst twice. After transfer by transfer, the color component B of 2N words existing in between and the color component C of 2N words similarly are skipped, and the next color component A is transferred. Therefore, it is necessary to increase the image addresses used for transfer like b, 5b, b, 5b, ....

As shown in FIG. 15 (2), let us consider a case where M = 1 is used and data is transferred in the same plane order. In this case, after the N-word color component A is transferred, the N-word existing color components B and C are skipped, and the next existing color component A is transferred. Therefore, the image addresses used for transfer may be increased like 3b, 3b, 3b, .... That is, when M = 1, it is sufficient to increase the address fixedly. In this way, when the increase number of addresses is fixed, it is not necessary to update the address increase number register 47, and the load can be reduced. Further, since it may be a constant, there is no need to configure the register, and the configuration can be simplified.

In the above description of the third embodiment, the modification of the first embodiment has been shown, but the structure of the second embodiment can be incorporated, and the structure of the image storage unit 12 is shown in FIG. It is also possible to adopt the configuration shown in FIG.

In each of the above embodiments, the dot-sequential image input / output unit 1
The transfer between the image storage unit 3 and the image storage unit 12 and between the plane-sequential image input / output unit 14 and the image storage unit 12 has been described. However, the present invention is not limited to this, and for example, transfer may be performed between the dot sequence image input / output unit 13 and the plane sequence image input / output unit 14.

In each of the above embodiments, one point-sequential image input / output unit and one plane-sequential image input / output unit are used. Even if the plane-sequential image input / output unit of is connected to the image transfer bus 11,
Similarly, a color image can be transferred. Also,
The point-sequential image input / output unit and the plane-sequential image input / output unit may be configured by separate devices for the image input unit and the image output unit, or only one of them may be used. At this time, the number of image input units and the number of image output units are arbitrary. Further, it may be a plane order image input point order image output section or a point order image input plane order image output section.

Specific examples of the above-described plane-sequential image input / output unit, plane-sequential image input unit, and plane-sequential image output unit may be, for example, an image scanner, an image printer, or an image communication apparatus. Further, a specific example of the dot-sequential image input / output unit, the dot-sequential image input unit, or the dot-sequential image output unit may be, for example, an image scanner, an image printer, or an image communication device. Furthermore, as a specific example of the image memory 23 in the image storage unit 12, for example, a dynamic random access memory (DRAM) can be used.

In the first and second embodiments described above, the address generation circuits 32 and 42 are used. In the third embodiment, the address registers 38 and 46 and the address increment number register 3 are used.
9, 47 and address adders 37, 45 are arranged in the dot-sequential image input / output unit 13 or the plane-sequential image input / output unit 14.
However, the circuit for calculating these addresses does not have to be placed in the dot-sequential image input / output unit 13 or the plane-sequential image input / output unit 14, and may be connected to the image transfer bus as an independent address control unit. Good. At this time, an address control unit common to the dot-sequential image input / output unit and the plane-sequential image input / output unit may be used. The address calculation may be performed by software or the like.

[0080]

As is apparent from the above description, according to the present invention, when images are transferred to the point-sequential image input / output device in the point order, and when the image is transferred to the face-sequential image input / output device in the surface order. In both cases of transfer, since the image can be transferred in bursts for each color component, the transfer speed can be improved. In the case of transferring images in point order to a point order image input / output device,
And, even if the bit width of one pixel does not match the word width, the image is burst transferred for each color component.
There is no need to pack and transfer dummy pixels as in the past.
The bus utilization efficiency can be improved, and the transfer speed can be improved.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram showing a first embodiment of a color image transfer device of the present invention.

FIG. 2 is a configuration diagram showing an example of an image storage unit in the first embodiment of the color image transfer apparatus of the present invention.

FIG. 3 is a configuration diagram showing an example of a dot-sequential image input / output unit in the first embodiment of the color image transfer apparatus of the present invention.

FIG. 4 is a configuration diagram showing an example of a plane-sequential image input / output unit in the first embodiment of the color image transfer apparatus of the invention.

FIG. 5 is an explanatory diagram of an example of an image data storage method in the first embodiment of the color image transfer apparatus of the present invention.

FIG. 6 is an explanatory diagram of an example of rearranging image data in the first embodiment of the color image transfer device of the invention.

FIG. 7 is a partial configuration diagram showing a specific example of the dot-sequential image input / output unit 13 in the first embodiment of the color image transfer apparatus of the invention.

FIG. 8 is an explanatory diagram of a window in the second embodiment of the color image transfer device of the present invention.

FIG. 9 is a configuration diagram showing an example of an image storage unit in a second embodiment of the color image transfer apparatus of the present invention.

FIG. 10 is an explanatory diagram showing an example of an image data storage method in the second embodiment of the color image transfer apparatus of the present invention.

FIG. 11 is an explanatory diagram of another example of the image data storage method in the second embodiment of the color image transfer apparatus of the present invention.

FIG. 12 is a configuration diagram showing an example of a dot-sequential image input / output unit in the third embodiment of the color image transfer device of the invention.

FIG. 13 is a configuration diagram showing an example of a plane-sequential image input / output unit in the third embodiment of the color image transfer apparatus of the invention.

FIG. 14 is an explanatory diagram of an example of an image data storage system in the third embodiment of the color image transfer apparatus of the present invention.

FIG. 15 is an explanatory diagram of a specific example of the image data storage system in the third embodiment of the color image transfer apparatus of the present invention.

FIG. 16 is a block diagram showing an example of a conventional image transfer device.

FIG. 17 is an explanatory diagram of an example of image data of a color image.

FIG. 18 is an explanatory diagram of dot order and plane order.

FIG. 19 is a block diagram showing an example of a conventional image input / output circuit.

FIG. 20 is an explanatory diagram of a bus transfer method.

FIG. 21 is an explanatory diagram of a case where color images are accumulated and transferred in plane order.

FIG. 22 is an explanatory diagram of a case where color images are accumulated and transferred in dot order.

[Explanation of symbols]

11 ... Image transfer bus, 12 ... Image storage unit, 13 ... Point-order image input / output unit, 14 ... Face-order image input / output unit, 21 ... Image address, 22 ... Image data, 23 ... Image memory, 24 ... Address adder , 25 ... Window address register, 2
6 ... Image address, 31 ... Image address, 32 ... Address generation circuit, 33 ... Image data, 34 ... Image data buffer, 35 ... Image data generation / use circuit, 36 ... Image data sorting circuit, 37 ... Address adder, 38 ... Address register, 39 ... Address increment number register, 41 ...
Image address 42 ... Address generation circuit 43 ... Image data 44 ... Image data generation / use circuit 45 ... Address adder 46 ... Address register 47 ... Address increment number register 51 ... Color switching circuit 52 ... FIF
O, 53 ... Pixel buffer circuit, 61 ... Image transfer bus, 6
2 ... Image storage unit, 63 ... Image input / output circuit, 64 ... Image input / output circuit, 71 ... Image input unit, 72 ... Image processing circuit, 7
3 ... Image output unit.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Taro Yokose 430 Nakai-cho, Nakara-cho, Ashigaragami-gun, Kanagawa Green Tech Nakai Fuji Xerox Co., Ltd. (72) Inventor Isao Uesawa 430 Sakai, Nakai-cho, Ashigarakami-gun, Kanagawa Green Tech Nakakai Fuji Xerox Co., Ltd.

Claims (6)

[Claims] 1. A color image transfer device for transferring a color image having a plurality of color components, and image transfer means capable of burst transfer of information for each predetermined transfer unit, and each color component of the color image for the image. Image storage means for arranging and storing the transfer unit in an integer multiple of the transfer unit; image address generation means for generating an address of the image storage means to be subject to the burst transfer; and dot-sequential image input / output means. A plane-sequential image input / output unit, wherein the dot-sequential image input / output unit is an image that has been transferred using the image transfer unit or is to be transferred, and is an integer multiple of the transfer unit of the image transfer unit. Image data holding means for holding the images arranged in the image data, and an image data rearranging means for rearranging the image data between the dot-sequential images and the images arranged every integer multiple of the transfer unit of the image transfer means. A color image transfer device comprising image data rearranging means. 2. The image storage means is arranged such that each color component of a color image is arranged every integer multiple of an image transfer unit of the image transfer means, and is arranged in an address space wider than the address space of the image transfer means. A window address register for holding the address of the image storage means or a part of the address, and an address generation for generating an address for the burst transfer from the address obtained from the image address generation means and the contents of the window address register. The color image transfer device according to claim 1, further comprising means. 3. The color image transfer according to claim 2, wherein in the image storage means, the integral multiple of the transfer unit × the number of color components + the number of invalid pixels is narrower than the address space of the image transfer means. apparatus. 4. The image storage means is arranged such that each color component of a color image is arranged every integer multiple of an image transfer unit of the image transfer means, and the address space width of the image transfer means is divided by the number of color components, The color image transfer apparatus according to claim 1, wherein a dedicated address space is allocated to each color component. 5. The image address generating means adds an image address holding means, an address increase number holding means, a content of the image address holding means and a content of the address increase number holding means to the image storing means. The address increment number holding means holds the transfer unit length of the image transfer means when performing transfer with the point order input / output means, 2. The color image transfer device according to claim 1, wherein the address difference up to the next same color component is held when the transfer is performed between the color image transfer devices. 6. The image storage means arranges and stores each color component of a color image for each transfer unit of the image transfer means, and the address increment number holding means is arranged between the address sequential input / output means. 6. The color image transfer apparatus according to claim 5, wherein the image transfer unit × the number of color components, which is an address difference up to the next same color component, is held when the transfer is performed.