JPH0964851A - Communication method for selecting error processing function automonously, its transmitter, its receiver and transmission state discrimination circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow the method to have provision for all expected events by applying error check to a signal subjected to correction processing and selecting an input signal for an error check circuit providing an output of a correct error check result so as to conduct reception processing. SOLUTION: A demodulator 21 demodulates a reception signal and gives the result to a 1st error check circuit 22 and an error correction coder 23. If the received signal is not the information provided with error correction information by a transmitter 1, the circuit 22 provides an output denoting it that the check result is correct. If the received signal is the information provided with error correction information by the transmitter 1, the circuit 22 provides an output denoting it that the check result is not correct. On the other hand, the coder 23 tries to conduct error correction decoding and provides an output to a 2nd error check circuit 24. When an output of the demodulator 21 is a signal provided with error correction information, the circuit 24 provides an output of denoting it that the check result is correct and when the output of the demodulator 21 is a signal not provided with error correction information, the circuit 24 provides an output of denoting it that the check result is not correct. A 2nd signal selection circuit 25 selects either an input of the circuit 22 or an input of the circuit 24.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication device having an error processing function, and more particularly to a communication device which autonomously selects an error processing function.

Recently, the spread of digital mobile phones has been remarkable, and in parallel with this, the spread of digital mobile phones having adapters for data and facsimile has started. Especially in the US, data communication by the latter is Movile.
There is a notable trend to call mobiles as offices, called computing.

Generally, in wireless communication, the communication quality is easily affected by the radio wave propagation state in the space, but especially in mobile communication, not only the radio wave propagation state in the space but also the building, the terrain,
Alternatively, the communication quality is likely to change due to the influence of the distance from the base station. Therefore, there is a strong demand for the realization of a communication method and a communication device capable of performing stable communication regardless of the transmission state including all of the radio wave propagation state, the building and terrain, and the distance to the base station.

[0004]

2. Description of the Related Art For example, in Japanese Patent Laid-Open No. 63-172536, the coding rate at the time of transmission is changed according to the quality of the transmission state detected by the receiving side of the other station, and the line quality is detected by the received signal of the own station. There is disclosed a variable coding rate digital communication device which multiplexes the detected information into a transmission signal and transmits the multiplexed signal, and the other station transmits the encoded information accordingly.

[0005]

According to the above-mentioned prior art, each time the channel quality measured by the local station changes, the other station transmits information to that effect, and the other station must encode based on the information. I have to.

Therefore, the transmitting side needs a circuit for multiplexing the line quality information and the receiving side needs a circuit for separating the information, which makes the device complicated. Also, the transmitting side relies on the channel quality information transmitted from the receiving side of the other station, that is, it encodes heterogeneously, so if the line quality information receives an error during transmission, the transmitting side Cannot determine which rule should be used for encoding. In order to prevent this, it is necessary to error-correction code and transmit the line quality information, which is originally about ON / OFF signals, which inevitably reduces the transmission efficiency.

In view of the above problems, it is an object of the present invention to provide a communication method in which a transmitting side and a receiving side autonomously select an error processing function, and a transmitting device and a receiving device thereof.

[0008]

FIG. 1 illustrates the principle of the present invention. In FIG. 1, reference numeral 1 is a transmitter of its own station, and 2 is a receiver of a partner station.

In the transmitter, 11 is an analog / digital conversion circuit (A / D), 12 is a first verification code addition circuit, 13 is an error correction encoder, 14 is a second verification code addition circuit, and 15 is a reception. A transmission state determination circuit that determines the quality of the transmission state based on the signal received by the device, and 16 selects the outputs of the first test code addition circuit and the second test code addition circuit according to the signal output by the transmission state determination circuit. The first signal selection circuit 17 is a modulator for converting a digital signal to be transmitted into a radio frequency band signal.

In the receiving device, 21 is a demodulator for converting a signal in the radio frequency band into a digital signal, and 22 is a first error test for performing an error test corresponding to the coding rule of the first test code adding circuit. A circuit, 23 is an error correction decoder for decoding in accordance with the encoding rule of the error correction encoder, and 24 is a second error for performing an error test in accordance with the encoding rule of the first test code addition circuit. A verification circuit, 25 is a second signal selection circuit for selecting the input of the first error verification circuit or the input of the second error verification circuit according to the outputs of the first error verification circuit and the second error verification circuit, 26 Is a digital-analog conversion circuit (D / A).

In the transmitter, the voice is digitized and supplied to the first verification code addition circuit and the error correction encoder. The first verification code addition circuit adds redundant information (first error verification information) for error detection to the original information and sends it. On the other hand, in the error correction encoder, redundant information (error correction information) for correcting the error is added to the original information, and further, redundant information for detecting an error in the second verification code addition circuit (second Error verification information) is added and sent. The first signal selection circuit selects one of the output of the first test code addition circuit and the output of the second test code addition circuit according to the output of the transmission state determination circuit. According to the conventional technique, the transmission state determination circuit determines the quality of the transmission state based on the code error rate detected in the receiving device of the partner station and the number of retransmission requests made in association with it. As a result, when the transmission state is good, the output of the first test code addition circuit is selected, and when the transmission state is bad, the output of the second test code addition circuit is selected, modulated and transmitted. It

When the transmission condition is good, the format is A
The first verification code adding circuit adds error verification information to the digital signal output by / D. On the other hand, when the transmission state is poor, the error correction encoder adds error correction information to the digital signal output from the A / D,
The second verification code adding circuit adds error verification information to the entire digital signal output by D and the error correction information. Therefore, if the receiving device can perform the receiving process even if the transmitting device selects the encoding method according to the transmission state and sends it without adding the information indicating which one is selected, the transmission is performed according to the ratio of the quality of the transmission state. The efficiency can be improved.

In the receiver, the received signal is demodulated, converted into a digital signal, and supplied to the first error checking circuit and the error correction encoder. The first error checking circuit attempts error checking on the assumption that the supplied signal is the output of the first checking code adding circuit. If the supplied signal is not the information to which the error correction information is added by the transmitter, the first error verification circuit outputs an output that the verification result is correct, and the supplied signal has the error correction information added. If so, the first error checking circuit outputs an output indicating that the checking result is incorrect. On the other hand, the error correction encoder attempts error correction decoding by assuming that the supplied signal is a signal that has been error correction coded by the transmission device, and supplies the output to the second error verification circuit.
The second error checking circuit attempts error checking on the supplied signal. If the output of the demodulator is a signal with error correction information added, the second error test circuit outputs a signal that the test result is correct, and the output of the demodulator is a signal with no error correction information added. If there is, the second error verification circuit outputs an output that the verification result is incorrect. Depending on the outputs of the first and second error checking circuits, if the input of the first error checking circuit or the input of the second error checking circuit is selected in the second signal selection circuit, the transmitter selects. The signal of the one transmitted can be obtained.

Therefore, according to the configuration of FIG. 1, even if the transmitting apparatus selects an error processing method according to the transmission state and transmits without adding the error processing method selection information, the receiving apparatus has the same error processing method as the selected error processing method. It is possible to autonomously select an error processing method and perform reception processing. Even if the error correction code is not added in the format of the transmission signal and the transmission efficiency looks good, the transmission state is poor and the error rate is high, the quality of the received signal is degraded, and many retransmission requests must be made. Then the actual transmission efficiency is low. Further, in the format of the transmission signal adapted to the case where the transmission state is bad, when the transmission state is good, it means that the transmission is performed with low efficiency from the beginning. On the other hand, if communication is performed with the configuration of FIG. 1, communication can be performed with the highest transmission efficiency obtained at that time according to the ratio of the quality of the transmission state.

FIG. 2 shows the second principle of the present invention. FIG.
In the above, 1a is a second transmitter of the own station, and 2a is a second receiver of the partner station.

In the second transmitter, 11 is an analog / digital conversion circuit (A / D), 12 is a first test code addition circuit, 13 is an error correction encoder, 14 is a second test code addition circuit, Reference numeral 15 is a transmission state judging circuit for judging the quality of the transmission state based on the signal received by the receiving device, and 16a is for supplying the output of A / D to the first verification code adding circuit or for the error correction encoder and the second circuit. A third signal selection circuit for selecting whether to supply an A / D output to the error checking circuit and outputting one of the outputs of the first and second error checking circuits, 17 is a digital signal selected for transmission Is a modulator that converts the signal into a signal in the radio frequency band.

In the second receiving device, 21 is a demodulator for converting a signal in the radio frequency band into a digital signal, and 22 is a first error test corresponding to the coding rule of the first test code adding circuit. Error check circuit 23, an error correction decoder 23 for decoding in accordance with the coding rule of the error correction encoder, 2
Reference numeral 4 denotes a second error checking circuit which performs an error check corresponding to the coding rule of the first check code adding circuit, and 25a denotes a first error check circuit according to the outputs of the first error check circuit and the second error check circuit. A fourth that supplies the output of the demodulator to one of the error test circuit or the error correction decoder and the second error test circuit and outputs one of the outputs of the first error test circuit or the second error test circuit. Is a digital / analog conversion circuit (D / A).

2 is characterized in that in the transmitting device,
A point that decides whether to output the A / D output to the first test code addition circuit or the A / D output to the error correction encoder and the second test code addition circuit according to the output of the transmission state determination circuit It is in. That is, the logic circuit of the transmitter is CMOS
In the case of an LSI, power consumption can be reduced by operating only one of the necessary circuits. or,
Also in the receiving device, it is determined whether the output of the demodulator is supplied to the first error checking circuit or the error correction decoder and the second error checking circuit according to the outputs of the first and second error checking circuits. . Therefore, the logic circuit of the receiver is CMOS
It is possible to reduce power consumption when it is configured by an LSI.

Also, when processing by program control,
Since the processing target is first determined and one of the processings is performed, the number of steps in actual operation is reduced and power consumption can be reduced.
Since the other operations are the same as those in the configuration of FIG. 1, detailed description thereof will be omitted here.

[0020]

1 and 2, a transmitter and a receiver are shown as a pair for easy understanding of the entire operation of the communication device. However, the transmitter and the receiver are paired. Is not limited to FIGS. 1 and 2. In any of the transmitters, the signal selected according to the transmission state is one of the same signals, and any of the receivers can receive and process any signal. Therefore, there are the following four types of pairs of transmitters and receivers. (1) The transmitter of FIG. 1 and the receiver of FIG. 1 (2) The second transmitter of FIG. 2 and the second receiver of FIG. 2 (3) The transmitter of FIG. 1 and the second receiver of FIG. Device (4) Second Transmitting Device of FIG. 2 and Receiving Device of FIG. 1 Therefore, hereinafter, the transmitting device and the receiving device will be described independently.

FIG. 3 shows an embodiment of the main part of the transmitter. In FIG. 3, 121 is a first CRC encoder that constitutes a first test code addition circuit, 131 is a BHC encoder that constitutes an error correction encoder, and 141 is a second CRC code that constitutes a second test code addition circuit. CRC encoder, and 15 is a transmission state determination circuit. Reference numeral 16 is a first signal selection circuit, which includes a logical product circuit 161, a second logical product circuit 162 in which one input is inverted, and a logical sum circuit 163.

In the configuration of FIG. 3, the digital signal from the A / D is supplied to the first CRC encoder and the error correction encoder. The first CRC encoder will add CR to this digital signal.
The C operation is performed and the CRC bit is added and output. BC
The H encoder adds and outputs a bit for error correction, and the second CRC encoder outputs a CRC to the entire signal in which the error correction bit is added to the digital signal from the A / D.
The calculation is performed and the CRC bit is added and output.

The first signal selection circuit selects the output of the first CRC encoder or the output of the second CRC encoder according to the output of the transmission state determination circuit. The output of the transmission state determination circuit is supplied to one input terminal of the logical product circuit 161 and is also supplied to the inverting input terminal of the second logical product circuit 162. Now, assuming that the transmission state determination circuit outputs "1" when the transmission state is good and outputs "0" when the transmission state is bad, the output of the second CRC encoder is when the transmission state is good. The output of the first CRC encoder is masked by the second AND circuit 162, while the output of the first CRC encoder is
Can pass 1. On the other hand, when the transmission state is poor, the output of the first CRC encoder is masked by the logical product circuit 161, while the output of the second CRC encoder is masked by the second logical product circuit 162. Can pass The logical sum circuit 163 is
Since the logical sum of the outputs of the logical product circuit 161 and the second logical product circuit 162 is output, the logical sum circuit 163 outputs an output signal of the logical product circuit 161 when the transmission state is good and when the transmission state is bad. The output signal of the second AND circuit 162 is output to. That is, depending on the transmission state, either the signal with the error verification bit added without error correction or the signal with the error verification bit added after error correction is selected and transmitted.

FIG. 4 is a flow chart showing a signal selection procedure in the transmitter having the configuration of FIG. Or later,
The signal selection procedure will be described with reference to the reference numerals in FIG. T1. First CRC for digital signal from A / D
A CRC operation is performed by the encoder and a CRC bit is added (operation of CRC1). T2. Error correction bits are added in the BCH encoder to the digital signal from the same A / D (BCH encoding). T3. The second CRC encoder performs a CRC operation on the signal to which the error correction bits have been added by the BCH encoder to add a CRC bit (operation of CRC2). T4. It is determined whether the transmission state determination circuit outputs the output indicating that the transmission state is good or the output indicating that the transmission state is bad. T5. When the transmission state determination circuit outputs the output indicating that the transmission state is good (Yes), the first signal selection circuit selects the input of the first CRC encoder and outputs it (CRC
Select 1.). T6. When the transmission state determination circuit outputs an output indicating that the transmission state is bad (No), the first signal selection circuit selects the input of the second CRC encoder and outputs it (CRC2
choose).

FIG. 5 shows an embodiment of the main part of the receiving apparatus. In FIG. 5, 221 is a first CRC decoder that constitutes a first error check circuit, 231 is a BCH decoder that constitutes an error correction decoder, and 241 is a second CRC that constitutes a second error check circuit. It is a decoder. A second signal selection circuit 25 includes an OR circuit 251, an AND circuit 252, a first flip-flop (FF) 253, and a second FF2.
53a, a selector 254 that selects the input of the first CRC decoder or the input of the second CRC decoder by the outputs of the first FF and the second FF, the AND circuit 252a, and the second logic of the output inversion. The product circuit 255 is provided. A synchronous circuit 27 supplies a clock to the AND circuit 252.

In the configuration of FIG. 5, the output signal of the demodulator is supplied to the first CRC decoder and BCH decoder. The first CRC decoder performs a CRC operation on the signal and outputs "1" if the operation result is correct and "0" if the operation result is not correct. The fact that the operation result is correct means that the transmission device does not add CRC to the signal to which the error correction bit is added.
It indicates that a signal with a bit added is being transmitted, and the fact that the signal is incorrect indicates that a signal with a CRC bit added to the signal with an error correction bit added is being transmitted by the transmitting device. The BCH decoder also performs error correction on the output signal of the demodulator. If the transmitter is transmitting a signal to which an error correction bit is added, the signal output as a result of error correction is the same signal output from the BCH encoder of the transmitter. This is C in the second CRC decoder
Since the RC calculation is performed, a correct calculation result is output. On the other hand, if the transmitter transmits the signal without error correction with CRC bits added, the output of the BCH decoder becomes a signal different from the signal output by the BCH encoder on the transmission side.
If this is CRC-calculated by the second CRC decoder, an incorrect result will be obtained.

Since the outputs of the first and second CRC decoders are contrary to each other in principle, they are supplied to the selector,
When the output of the first CRC decoder is “1” and the output of the second CRC decoder is “0”, the input of the first CRC decoder is selected, and conversely, the output of the first CRC decoder is selected. The second CRC if the output is "0" and the output of the second CRC decoder is "1".
Selecting the input of the decoder will correctly select the signal transmitted by the transmitter.

However, depending on the transmission state, there is a probability that the two CRC decoders will both output "0" or both "1". In such a case, the receiving device cannot perform the receiving process. Therefore, in order to avoid this, the logical sum circuit 251, the logical product circuits 252 and 252a, the first FF 253 and the second FF 253a, and the second FF 253a. A circuit based on the logical product circuit 255 is added.

The OR circuit 251 outputs "0" only when the second CRC decoder outputs "0". This "0"
Is supplied to one input terminal of the logical product circuit 252, so that the clock supplied from the synchronizing circuit to the other input terminal of the logical product circuit 252 is masked. For this reason, the state of both FFs is held in the previous selected state, so that the receiving apparatus can continue the receiving process even if the two CRC decoders both output "0".

On the other hand, when the outputs of the two CRC decoders output "1" at the same time, the logical sum circuit 251 outputs "1", but the logical product circuit is output by "0" output from the second logical product circuit 255. Since it is masked to "0" in 252a, the clock is masked in the logic circuit 252 in this case as well, and the previous selected state is held. As a matter of course, when the normal reception is possible and the two CRC decoders output mutually contradictory outputs, the OR circuit 251,
Since the second AND circuit 255 outputs "1", the clock is not masked by the AND circuit 252,
Since the output of each CRC decoder at that time is held in each FF, selecting the two signals with the outputs of the two FFs also selects the two signals with the output of the two CRC decoders. Is also equivalent.

FIG. 6 is a flow chart showing an error processing procedure in the receiver having the configuration of FIG. Less than,
The procedure will be described with reference to the reference numerals in FIG. R1. The first CRC decoder performs CRC calculation on the output signal of the demodulator to obtain the calculation result. R2. The output signal of the same demodulator is decoded in the first BCH decoder to perform error correction. R3. The second CRC decoder performs a CRC operation on the output signal of the BCH decoder to obtain the operation result. R4. It is determined whether or not the calculation result in the first CRC decoder is correct. R5, R6. Regardless of the determination result in step R4, it is determined whether the calculation result in the second CRC decoder is correct. R7. Incorrect judgment result in step R5 (No)
Input signal of the first CRC decoder (data 1), if
Select R8. If the determination result in step R6 is correct (Yes), the input signal (data 2) of the second CRC decoder is selected. R9. If the determination result in step R5 is correct (Yes), and the determination result in step R6 is incorrect (N
In the case of o), since the same test result is output from the two CRC decoders, the previous state is retained.

In FIG. 6, the expression is such that the processing is ended, but this means the end of the processing of one cycle, and in reality, it is returned from R7, R8, R9 to R1 and endless. Is being processed.

FIG. 7 shows the format of the transmission signal.
(A) is a format when the transmission state is good, FIG.
(B) is a format when the transmission state is bad. The format when the transmission state is good is that the first CRC encoder adds CRC bits to the digital signal output from the A / D. On the other hand, when the transmission condition is bad, the error correction bit is added to the digital signal output by the A / D, and the second CRC encoder applies the CRC to the entire digital signal and error correction bit output by the A / D. Bits are added.

Now, assuming that the first CRC encoder and the second CRC encoder are CRC16, the first and second CRC encoders are
Encoder has 16-bit CR for 150-bit signal
Add C bit. Since error correction is not performed when the transmission state is good, all of these 150 bits are signals output by the A / D [Fig. 7 (a)]. If the error correction encoder is a BCH (15, 10) encoder, 5 correction bits are added to 10 bits of the input signal.
The 50 bits are composed of 100 bits of the A / D output signal and 50 bits of error correction bits [FIG. 7 (b)]. Note that FIG. 7B shows a format in which the A / D output signal and the error correction bits are separately collected. However, a block including 10 bits of the A / D output and 5 bits of the error correction bits is divided into 10 blocks. There may be a format for arranging them individually.

Since the frame signal and other service signals must be transmitted regardless of the transmission state, if the transmission state is good, the transmission efficiency [(number of bits of input signal / error processing The number of bits of the entire received signal) × 100%. ] Is about 90%, and about 60% when the transmission condition is poor. If the BCH (15, 10) code is used assuming that the transmission condition is always bad, the transmission efficiency is about 60% even when the transmission condition is good, and conversely, the error correction is performed assuming that the transmission condition is good. If the transmission condition is bad unless you do so, 60% due to a retransmission request etc.
It is expected that the transmission efficiency will be lower. On the other hand, according to the present invention, since it is possible to communicate at a transmission efficiency of 60 to 90% according to the ratio of the quality of the transmission state, it is possible to substantially improve the transmission efficiency.

FIG. 8 shows a second embodiment of the main part of the transmitter. In FIG. 8, 121 is a first CRC encoder that constitutes a first test code addition circuit, 131 is a BHC encoder that constitutes an error correction encoder, and 141 is a second CRC code that constitutes a second test code addition circuit. CRC encoder, and 15 is a transmission state determination circuit. A third signal selection circuit 16a includes a logical product circuit 161, a second logical product circuit 162 in which one input is inverted, and a logical sum circuit 163.

In the configuration of FIG. 8, the output of the transmission state determination circuit is supplied to one input terminal of the AND circuit 161 and the inverting input terminal of the second AND circuit 162. Therefore, when the transmission condition is good, the A / D output signal is supplied only to the first CRC encoder and not to the BCH encoder. On the contrary, when the transmission condition is bad, the output signal of the A / D is supplied only to the BCH encoder and not to the first CRC encoder. Normally, the logic circuit is C
Since it is formed by the IC by the MOS process, the circuit to which the input signal is not supplied consumes no power. Of course, reduction of power consumption is an important factor in designing information communication devices, but especially in portable communication devices, it is very important for saving battery power. The feature of the configuration of FIG. 8 is that power can be saved while performing the same function as in FIG.

FIG. 9 is a flow chart showing the second signal selection procedure in the transmitter. Hereinafter, the signal selection procedure will be described with reference to the reference numerals in FIG. T4. The transmission state determination circuit determines whether the transmission state is good or bad. T7. When the transmission condition is good (Yes), the first C
The A / D output signal is supplied to the RC encoder. At this time, the BCH encoder and the second CRC encoder consume no power. T8. When the transmission state is poor (No), the output signal of A / D is supplied to the BCH encoder. At this time the second C
The RC coder works with the BCH coder. On the other hand, the first CRC encoder does not operate and therefore does not consume power.

Comparing the flowchart of FIG. 9 with the flowchart of FIG. 4, even in the case where the signal selection in the transmitter is performed by program control, the coding method to be selected from the beginning should be determined according to the transmission state, and only that is executed. Since this is good, the load on the CPU is reduced and at the same time the processing speed is improved.

FIG. 10 shows a second embodiment of the main part of the receiving device. In FIG. 10, 221 is a first CRC decoder that constitutes a first error checking circuit, 231 is a BCH decoder that constitutes an error correcting decoder, and 241 is a second CRC that constitutes a second error checking circuit. It is a decoder. 25a
Is a fourth signal selection circuit, which is included in the second signal selection circuit of FIG. 5 and includes an OR circuit 251, an AND circuit 252, a first flip-flop (FF) 253, and a second FF 253.
a, the logical product circuit 252a, and the second logical product circuit 255, the logical product circuits 252b, 252c, 252d, and 252.
e and an OR circuit 251a are also provided. 27 is a synchronizing circuit, which supplies a clock to the AND circuit 252 and
The synchronization establishment signal is supplied to the AND circuits 252b and 252c.

Also in the configuration of FIG. 10, the operation of generating the signal for selecting the data 1 or the signal for selecting the data 2 by the outputs of the first and second CRC decoders is exactly the same as in the case of FIG. The feature of the configuration of FIG. 10 is that a signal for selecting data 1 or a signal for selecting data 2 which depends on the outputs of the first and second CRC decoders causes the first C
The point is to try to mask the input signal of the RC decoder or the input signal of the BCH decoder. However, if the input signal of the first CRC decoder or the input signal of the BCH decoder is directly masked by the output signal of the second FF, the data 1 or the data 2 is erroneously masked while synchronization is not established in the receiving device. Therefore, in order to avoid this, the logical product circuit 252b, the logical product circuit 252d, and the logical product circuit 252c are provided.
And a logical product circuit 252e are provided so that each of the output signals of the two FFs and the synchronization establishment signal are logically producted and masked.

Since the input side of the first CRC decoder and the BCH decoder selects which of the demodulator outputs is to be supplied, the selector used in the configuration of FIG. 5 has the configuration of FIG. Instead, an OR circuit 251a which can output either the input of the first or second CRC decoder is used instead.

In the configuration of FIG. 10, the demodulated signal is supplied to the first CRC decoder and BCH decoder at the beginning of reception by the receiving device, and the first CRC decoder, BCH decoder and second The CRC decoder operates, but once the signal for signal selection is output from the first or second CRC decoder, the decoding system corresponding to the signal not transmitted by the transmitter supplies the demodulated signal. Stop for not being done. Therefore, when the configuration of FIG. 10 is formed by the CMOS LSI, there is an advantage that the power consumption can be reduced.

FIG. 11 is a flow chart showing a second error processing procedure in the receiving device. The error processing procedure will be described below with reference to the reference numerals in FIG. R1. The first CRC decoder performs CRC calculation on the output signal of the demodulator to obtain the calculation result. R2. The output signal of the same demodulator is decoded in the first BCH decoder to perform error correction. R3. The second CRC decoder performs a CRC operation on the output signal of the BCH decoder to obtain the operation result. R4. It is determined whether or not the calculation result in the first CRC decoder is correct. R5, R6. Regardless of the determination result in step R4, it is determined whether the calculation result in the second CRC decoder is correct. R10. The judgment result in step R5 is incorrect (N
In the case of o), the input signal (data 1) of the first CRC decoder is supplied to operate the first CRC decoder. At this time, the BCH decoder and the second CRC decoder consume no power. R11. The determination result in step R6 is correct (Yes)
In this case, the demodulated signal is supplied to the BCH decoder to
Select At this time, the BCH decoder and the second CRC decoder operate, and the first CRC decoder consumes no power. R12. The judgment result in step R5 is correct (Yes)
If, and if the determination result in step R6 is incorrect (No), the same test result is output from the two CRC decoders, and the previous state is retained.

According to the flowchart of FIG. 11, once the decoding system to be operated is determined, only one operation needs to be performed. Therefore, even if the operation described above is executed by program processing, unnecessary operation is performed. Because you don't have to
The load on the CPU can be reduced and at the same time the processing speed can be improved.

FIG. 12 shows a third embodiment of the main part of the receiving apparatus. In FIG. 12, 221 is a first CRC decoder that constitutes a first error checking circuit, 231 is a BCH decoder that constitutes an error correction decoder, and 241 is a second CRC that constitutes a second error checking circuit. It is a decoder. 25b
Is a fourth signal selection circuit, which is provided in the fourth signal selection circuit of the configuration of FIG.
First flip-flop (FF) 253, second FF
253a, AND circuit 252a, second AND circuit 25
5, AND circuits 252b, 252c, 252d, 252
In addition to e and the OR circuit 251a, the first differentiating circuit 256
And a second differentiating circuit 256a, an OR circuit 251b, 2
It also comprises 51c and 251d. A synchronizing circuit 27 supplies a clock to the AND circuit 252 and a synchronization establishment signal to the AND circuits 252b and 252c.

The first differentiating circuit 256 and the second differentiating circuit 256a, and the OR circuits 251b, 251c and 251d.
Since the other parts operate exactly the same as those in FIG. 10, only the operations of the newly added parts will be described here.

Now, in the configuration of FIG. 10, the first FF is "1".
If the second FF is held at “0”, the demodulated signal to the first CRC decoder is allowed and the input of the demodulated signal to the BCH decoder is prohibited. There is. At this time, when the code transmitted by the transmitter is changed so as to perform error correction, the first CRC decoder detects it and outputs "0". Therefore, the first FF also holds "0". To do. However, since the input of the demodulated signal to the BCH decoder continues to be prohibited, the second CRC decoder cannot detect that the transmission signal has changed. With this,
Since it is not possible to receive a changed transmission signal, it is inconvenient especially when the transmission state changes from time to time. The parts of the first differentiating circuit 256 and the second differentiating circuit 256a, and the OR circuits 251b, 251c and 251d are circuits for avoiding such a situation.

The first differentiating circuit and the second differentiating circuit respectively differentiate the outputs of the first FF and the second FF, and both are FF.
It is assumed that it is set to output a positive pulse by detecting the point at which the output of 1 changes from "1" to "0".
In the configuration of FIG. 12, the transmission state changes when the first FF is held at “1” and the second FF is held at “0”, and when the transmission device changes the transmission signal, The first differentiating circuit detects the change from "1" to "0" and outputs a positive pulse, and the second differentiating circuit outputs nothing. Since the logical sum of the two is taken and supplied to the logical sum circuit 251d, the demodulated signal can pass through the logical product circuit 252e. Then, the BCH decoder performs the decoding, the second CRC decoder performs the CRC operation, and the signal indicating that the operation result is correct is output. Therefore, the second FF outputs "1".
Is held. In order to perform this operation, the pulse output from the first differentiating circuit may be continued for the time required for error correction and error verification. On the other hand, after the pulse of the first differentiating circuit disappears, the input of the demodulated signal to the first CRC decoder is prohibited, and the first FF holds “0”, so that the decoding system is autonomous in the receiving device. Can be changed. Although the case where the first FF is held at “1” has been described above, when the second FF is held at “1”, the autonomous operation is performed in the same manner in response to the change in the transmission signal. It goes without saying that the decoding system can be changed.

That is, the configuration of FIG. 10 may be applied when the transmission state is relatively stable as in fixed station communication, but when the transmission state changes frequently as in mobile communication. For this, the configuration of FIG. 12 is advantageous.

FIG. 13 is a flowchart showing a third error processing procedure in the receiving device. Hereinafter, the error processing procedure will be described with reference to the symbols in FIG. R1. The first CRC decoder performs CRC calculation on the output signal of the demodulator to obtain the calculation result. R2. The output signal of the same demodulator is decoded in the first BCH decoder to perform error correction. R3. The second CRC decoder performs a CRC operation on the output signal of the BCH decoder to obtain the operation result. R4. It is determined whether or not the calculation result in the first CRC decoder is correct. R5, R6. Regardless of the determination result in step R4, it is determined whether the calculation result in the second CRC decoder is correct. R10. The judgment result in step R5 is incorrect (N
In case o), the demodulated signal is supplied to the first CRC decoder. When the logic circuit is composed of a CMOS LSI, the first CRC decoder operates and the BCH decoder and the second CRC decoder do not operate. Therefore, the BCH decoder and the second CRC decoder consume no power. R11. The determination result in step R6 is correct (Yes)
In this case, the demodulated signal is supplied to the BCH decoder to
Select At this time, the BCH decoder and the second CRC decoder operate, and the first CRC decoder consumes no power. R12. The judgment result in step R5 is correct (Yes)
If, and if the determination result in step R6 is incorrect (No), the same test result is output from the two CRC decoders, so the previous state is selected and held. R13. While supplying the demodulated signal to the first CRC decoder, it is determined whether the output of the first CR decoder has changed from "1" to "0". If it does not change (No), nothing is done, and if it changes (Yes), the process returns to step R6. R14. While supplying the demodulated signal to the BCH decoder,
It is determined whether or not the output of the second CR decoder has changed from "1" to "0". If it does not change (No), nothing is done, and if it changes (Yes), the process returns to step R4.

Incidentally, in FIG. 13, the flow ends, but this means the end of the operation of one cycle, and in reality, each loop is made by R12, R13 and R14, and R13 Alternatively, when a change is detected in R14, it shifts to another state and moves endlessly.

By the way, in the above embodiment, the CRC test is illustrated as the error check system and the BCH code which is the block code is illustrated as the error correction system. However, the technique of the present invention is not limited to these. Absent. That is, the simplest parity check can be used for the error verification method, and the convolutional code can be used for the error correction code.

Further, in the above embodiment, one of the signal to which the error verification bit is added without error correction and the signal to which the error verification bit is added after the error correction bit is selected is transmitted. Although the method and device for selecting one of the receiving devices and performing the receiving process have been described, the present invention is not limited to the alternative. For example, a first signal to which an error verification bit is added without error correction, a second signal to which an error verification bit is added after adding an error correction bit by an error correction code capable of correcting a single error, and a burst Select one signal from the third signal with the error verification bit added after adding the error correction bit by the error correction code that can correct the error, and send it. It is also possible to perform the reception processing by selecting the input signal of the error checking circuit. In this case, the output of the transmission state determination circuit is not "0" or "1" but is output as a combination of a plurality of bits, and the first signal selection circuit may be provided with a selection circuit for performing one of the three selections. In the receiving device, a selection circuit that makes a three-way choice is applied to the selection of the signal processed for reception or the selection of the circuit that supplies the demodulated signal, and the circuit that holds the previous state when the results of the error verification are matched is In the method that the clock is stopped when the test results of the above three match with "1" and when the test results of all three match with all "0", and the circuit that supplies the demodulation signal is selected by the test result When the test result of the currently selected circuit changes from "1" to "0", the demodulated signal to the other two may be allowed to be supplied. They are,
This can be easily realized by referring to the circuits described in FIGS. 5, 10, and 12.

Further, although the options have heretofore been assumed to include a signal to which an error verification bit is added without error correction, the present invention is not limited to this. For example, the first signal has a signal added with error correction bits that can correct a single error, and the second signal has a signal added with error correction bits that can correct a burst error. Generate one with the verification bit added, select one of them according to the transmission status and send it, and the receiving device outputs the result of the error verification of the output of the first error correction decoder and the output of the second error correction decoder. It is also possible to select one of them according to the result of the error test of and to perform reception processing.

Therefore, the essence of the present invention is to determine one signal from the plurality of signals obtained by adding the error verification bit to the signal subjected to the different error correction processing, including the case where the error correction is not performed, by the transmission state determination circuit. Select and send according to the result,
The receiving device performs an error test on each signal that has undergone different error correction processing, including the case where no error correction is performed,
It can be said that this is a technique for selecting an input signal of the error detection circuit that outputs a correct result and performing reception processing.

The description so far has been made on the premise that the transmission status is determined, but the configuration of the transmission status determination circuit will now be described. FIG. 14 shows an embodiment of the transmission state determination circuit.

In FIG. 14, 151 is a differentiating circuit, and 15
Reference numeral 2 is a counter, and 153 is a comparison circuit for comparing the count value of the counter with a reference value. The differentiating circuit is, for example, the output terminal of the first CRC decoder or the second C of the configuration of FIG.
It is connected to the output terminal of the RC decoder or the output terminal of the first FF or the output terminal of the second FF and detects a change in the logic level at the connected output terminal to generate a pulse.
The pulse is supplied to the clock terminal of the counter to count for a predetermined time. The comparison circuit outputs "1" or "0" depending on whether or not the count value exceeds the reference value. That is, the feature of the present invention is that if the transmission state changes and the signal selected by the transmitting device changes, the signal that specifies the signal to be selected is detected by the receiving device and changed.
The transmission state is determined by utilizing this.

Usually, as a method of judging the transmission state,
A method of measuring the error rate by comparing the demodulated signal with a signal obtained by adding an error correction bit to a signal obtained by performing error correction on the demodulated signal is adopted. In this method, the receiving device is the same as the transmitting device. It becomes essential to provide an error correction encoder, which causes the device to be complicated. In particular, in a mobile device such as a mobile phone, considering that the complexity of the device affects the life of the battery, it is necessary to realize the device with a simple structure. In this sense, the transmission state determination circuit of the present invention is advantageous when mounted in a mobile station. If a base station is provided with a transmission state determination circuit for measuring an ordinary error rate, the transmission state can be determined in a stable manner.

In the above description, the case where the transmission state is distinguished by binary value has been described. However, the comparison circuit excluding the comparison circuit that supplies the count value of the counter to a plurality of comparison circuits and determines the highest and lowest transmission states is described. If a so-called window comparator is used, it is possible to realize a transmission state determination circuit capable of outputting a determination signal by distinguishing between three or more transmission states.

Further, in the above, the transmission state is judged by the frequency of change of the transmission signal of the partner station (base station) detected by the reception device of the own station (mobile station), and the transmission signal of the transmission device of the own station is selected accordingly. The transmission state determination circuit has been described as performing the above.The output of the transmission state determination circuit described above is multiplexed with the transmission signal and sent to the partner station, and the partner station outputs the transmission signal according to the output of the transmission state determination circuit. It is also possible to select, and receive the output of the normal transmission state determination circuit of the partner station to select the transmission signal of the own station. Even in such usage, the advantage of the simplicity of the configuration of the transmission state determination circuit according to the present invention does not change.

Finally, although the present invention was invented as an effective technique in wireless communication, especially mobile communication, it can be naturally applied to other systems having a poor error rate. For example, it is still effective even in a LAN or the like to which a metallic transmission line is applied, which is used in a noisy factory premises.

[0063]

As described above in detail, according to the present invention, the transmitting apparatus transmits the error processing according to the transmission state, and the receiving apparatus autonomously selects the error processing performed by the transmitting apparatus to perform the receiving processing. A communication method can be realized.

As for the transmitting device, both a transmitting device which performs error processing and then selects one of the transmitting devices according to the transmission state to transmit, and a transmitting device which performs error processing preselected according to the transmission state and transmits.

Further, regarding the receiving device, the receiving device that selects the received signal to be selected based on the result of the error test on the received signal, and the receiving device that selects the error processing to be executed based on the result of the error test on the received signal. Both are realized, and it is possible to cope with all the expected situations in any receiving device.

In addition, a simple transmission state judging circuit is also provided.

[Brief description of drawings]

FIG. 1 illustrates the principle of the present invention.

FIG. 2 shows the second principle of the present invention.

FIG. 3 is an embodiment of a main part of a transmission device.

FIG. 4 is a signal selection procedure in a transmitter.

FIG. 5 is an embodiment of a main part of a receiving device.

FIG. 6 shows an error processing procedure in the receiving device.

FIG. 7 is a format of a transmission signal.

FIG. 8 is a second embodiment of the main part of the transmission device.

FIG. 9 is a second signal selection procedure in the transmission device.

FIG. 10 shows a second embodiment of the main part of the receiving device.

FIG. 11 is a second error processing procedure in the receiving device.

FIG. 12 shows a third embodiment of the main part of the receiving device.

FIG. 13 shows a third error processing procedure in the receiving device.

FIG. 14 is an embodiment of a transmission state determination circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 transmitter 2 receiver 11 analog / digital conversion circuit (A / D) 12 first verification code addition circuit 13 error correction encoder 14 second verification code addition circuit 15 transmission state determination circuit 16 first signal selection circuit 17 modulator 21 demodulator 22 first error test circuit 23 error correction decoder 24 second error test circuit 25 second signal selection circuit 26 digital-analog conversion circuit (D / A)

Claims (9)

[Claims] 1. A transmission apparatus, wherein one of a plurality of signals in which a transmission state is determined and an error verification bit is added to a signal obtained by adding a different error correction bit to an input signal according to the determination result Then, the receiving device performs an error correction process on the input signal corresponding to the signal to which all the error correction bits in the transmitting device are added, and performs an error test on the corrected signal to obtain a correct error. A communication method for autonomously selecting an error processing function, characterized by selecting an input signal of an error verification circuit that outputs a verification result and performing reception processing. 2. A transmission device, which determines a transmission state and, in accordance with a result of the determination, a signal obtained by adding an error verification bit to an input signal without adding an error correction bit,
One signal of a plurality of signals consisting of a plurality of signals with different error correction bits added to the input signal and a plurality of signals with error verification bits is transmitted, and at the receiving device, with respect to the input signal, Performing error correction processing corresponding to a signal obtained by performing error verification without performing error correction processing and a signal to which all error correction bits are added in the transmission device, and performing error verification on the corrected signal. A communication method for autonomously selecting an error processing function, characterized in that a plurality of performed error test results are obtained, and an input signal of an error test circuit that outputs a correct error test result is selected and reception processing is performed. 3. A transmission device applied to the communication method for autonomously selecting an error processing function according to claim 1 or 2, wherein the input signal includes a case where no error correction processing is performed. A plurality of error correction encoders that add different error correction bits, a plurality of verification code addition circuits that add error verification bits to the output of each error correction encoder, and a transmission state is monitored to determine the degree A transmission comprising: a transmission state determination circuit; and a signal selection circuit that selects the output signal of one of the test code addition circuits from the output signals of the plurality of test code addition circuits based on the output of the transmission state determination circuit. apparatus. 4. A transmission apparatus applied to the communication method for autonomously selecting an error processing function according to claim 1 or 2, wherein the input signal includes an error correction processing. A plurality of error correction encoders that add different error correction bits, a plurality of verification code addition circuits that add error verification bits to the output of each error correction encoder, and a transmission state is monitored to determine the degree A signal for supplying a signal to be input by selecting one error correction encoder from among the plurality of error correction encoders, including the case where no error correction processing is performed, by the transmission condition determination circuit and the output of the transmission state determination circuit. And a selection circuit. 5. A receiver applied to the communication method for autonomously selecting an error processing function according to claim 1 or 2, wherein the demodulated signal is included in the case where no error correction is performed. A plurality of error correction decoders that respectively perform different error corrections, a plurality of error test circuits that perform error tests on the output signals of the respective error correction decoders, and a correct error test of the plurality of error test circuits And a signal selection circuit that selects an input signal of one error detection circuit that outputs the result. 6. A receiving apparatus applied to the communication method according to claim 1 or 2 that autonomously selects an error processing function, wherein the receiving apparatus applies to a demodulated signal including a case where error correction is not performed. A plurality of error correction decoders that respectively perform different error corrections, a plurality of error test circuits that perform error tests on the output signals of the respective error correction decoders, and a correct error test of the plurality of error test circuits And a signal selection circuit that supplies an demodulated signal by selecting an error correction decoder that receives the signal and outputs the result. 7. The receiving device according to claim 5, wherein at least two error checking circuits of the plurality of error checking circuits simultaneously output correct checking results to the signal selection circuit, And a receiving device having a configuration for holding the previous signal selection state when all the error test circuits output incorrect test results. 8. The receiving apparatus according to claim 6, wherein the signal selection circuit is currently selected when the error selection circuit associated with the error correction decoder outputs an incorrect decision result to the signal selection circuit. A receiver comprising a structure for forcibly supplying a demodulated signal to an error correction decoder which is not provided. 9. The transmission state determination circuit in the transmission device according to claim 3 or 4, wherein the output signals or the signals of the plurality of error detection circuits according to any one of claims 4 to 7. A change in the logic level of at least one of the plurality of selection signals generated in the selection circuit is detected, the number of times the change is detected is counted, and the count result is compared with a preset reference value. A transmission state determination circuit characterized by comprising a configuration for outputting a determination result according to the above.