JP2003134092A - Communication system, transmitter, receiver, error detection encoding circuit, and error detection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To distinguish a state of no signal and all '0' data in a frame transmitted by CRC check. SOLUTION: A transmitter 1 inverts the logic of respective bits of CRC bits generated by a CRC generation part 11a by a bit inversion part 11b and transmits the inverted bits. A receiver 2 performs CRC detection processing for a bit train obtained by inverting the logic of respective bits corresponding to the CRC bits out of reproduced bit train by a CRC check part 26d.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication system, a transmission device, a reception device, an error detection coding circuit and an error detection circuit which use an error detection code such as a cyclic code.

[0002]

2. Description of the Related Art In wireless communication and the like, a cyclic code (CRC) is widely used to detect the presence or absence of a transmission error on the receiving side.

A communication system using this CRC is shown in FIG.
As shown in, the CRC is based on the transmission data string at the transmission side.
Generate a bit and add this CRC bit to the end of the transmitted data string. Then, a bit string formed by adding CRC bits to the transmission data string is encoded by, for example, a convolutional encoding method, and the encoded bit string obtained by this is used for transmission.

On the other hand, on the receiving side, after the transmitted encoded bit string is decoded by Viterbi decoding or the like, true transmission data (data excluding CRC bits) is extracted, and this is used as a reception data string.

In parallel with this, C related to the received data string
RC check is performed based on the CRC code, and the check result is obtained as the CRC detection result.

By the way, in such a communication system, in general, the time during transmission is divided into frames, and data is inserted into the frame for communication. It suffices that the data to be constantly communicated is inserted in all the frames, but in some frames, the data may not be inserted.

Therefore, it is conceivable that a receiving side can determine the presence or absence of data by adding a special frame content instruction bit (instructing the frame format or the presence or absence of data). In the system that does not adopt the method, the receiving side determines the presence or absence of data based on the state of the received data, and the CRC check is used.

The method for judging the presence / absence of the data of the frame based on the CRC detection result is that the CRC judgment result is OK when there is data, and the CRC detection result is NG when noise is processed when there is no data. Is based on.

Here, normally, the bit string (0/1) of the data to be communicated is transmitted by being assigned + 1 / −1, that is, positive or negative of the signal on the transmission line, and the amplitude value of the received power is indicated on the receiving side. It is often given to the processing symbol,
Basically, the input to the Viterbi decoding unit also becomes a signal string having a code of + 1 / -1. Generally, subsequent data processing is performed with a value of ± X, which has a power amplitude value of the received symbol.

When the Viterbi decoding method is used, the ± X data string is input to the decoding unit, and the 0/1 data string is output as the output. However, when the data is not inserted in the frame, the received signal is noise and has a small random value of power (that is, signal size), and this value is input to the decoding unit.

On the other hand, in the process of demodulation processing, complicated calculations are performed, and the number of bits around the symbol of the data being processed tends to increase. For this reason, processing for reducing the number of significant digits, such as bit extraction and truncation, is performed.
If no data is inserted in the frame and noise is processed by the receiver, the input value of the decoding unit is all “0” because the power is originally small and the bits are truncated.
It may become data.

In the case of the decoding unit of the Viterbi decoding system, all
When there is a data string input of "0" (power amplitude value is 0), data of all "0" is output due to its characteristics. Also CRC
Even in the detection process, when such data of all “0” is input, the operation content of the CRC bit generation is Ex-OR of the data string, and therefore CR of all “0” is also generated.
It becomes C bits, and the CRC detection result becomes OK.

Further, when actually trying to transmit the data in which all the bits are "0" in a certain frame, the receiver is different from the case where there is no data, "+ X" corresponding to all the data bits "0". "Is sent to the subsequent processing, and all" + X "data is input to the Viterbi decoding. The decoding unit normally performs the decoding process and outputs a data string of all “0”. As a result, the CRC detection process also becomes OK.

Actually, noise on the signal on the transmission line,
The amplitude of the received symbol is not a fixed value and varies because of fading or the like, but for simplicity of description, it is set to a fixed value “X” here.

As described above, when a receiving system that outputs a bit string of all "0" even when the received signal is only noise is adopted, even if there is no signal in the frame, Even if all "0" data is transmitted, the received data sequence is all "0".
In addition, since the CRC detection result is OK, it is impossible to distinguish between the state in which there is no signal in the frame and the state in which the data of all "0" is transmitted.

[0016]

As described above, the prior art is as follows.
When a receiving system that outputs a bit string of all “0” even when the received signal is only noise is used, the CRC check transmits the state of no signal in the frame and the data of all “0”. There was a problem that it was not possible to distinguish the states that had come.

The present invention has been made in consideration of such a situation, and an object thereof is to carry out a CRC check of a state where there is no signal in a frame and a state where all "0" data is transmitted. It is to provide a communication system, a transmission device, a reception device, an error detection coding circuit, and an error detection circuit that can be distinguished.

[0018]

In order to achieve the above-mentioned object, the present invention provides, in the transmitter, a generating means for generating an error detecting code based on transmission data, and the generating means generated by the generating means. Addition means for adding an error detection code to the transmission data, first inversion means for inverting the logic of a predetermined bit including some bits forming the error detection code, and the error detection code for the transmission data And transmitting means for transmitting a bit string in which the logic of the bit at the predetermined position is inverted by the first inverting means. The receiving device further includes receiving means for receiving the bit string transmitted by the transmitting means, separating means for separating the transmission data and the error detecting code from the bit string received by the receiving means, and the predetermined bit The presence or absence of a transmission error is determined based on the transmission data and the error detection code which are separated by the separation means and which are separated by the separation means and whose logic of the predetermined bit is inverted by the second inversion means. And a determination means for doing so.

By taking such a means, the logic of at least a part of the bits of the error detection code is inverted and transmitted at the transmitting side, and at the same position as the logic is inverted at the transmitting side at the receiving side. Error detection is performed after inverting the bit logic. Therefore, since the data transmitted from the transmitting side and received by the receiving side is subjected to error detection after the logic of each bit is returned to the original state, error detection can be normally performed. When a bit string having all “0” is obtained because a frame without data is received, the logic of at least a part of the bits is inverted to make the bit string not all “0”. Since error detection is performed, it is determined that there is an error.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a block diagram of a radio communication system according to a first embodiment of the present invention.

As shown in FIG. 1, the wireless communication system of this embodiment comprises a transmitter 1 and a receiver 2. The transmitter 1 includes an error detection coding circuit 11, a convolutional coding unit 12, an interleave / framing unit 13, a transmitter 14, an RF unit 15 and an antenna 16. The receiving device 2 includes an antenna 21, an RF unit 22, a receiver 23, a deinterleaving / deframing unit 24, and a Viterbi decoding unit 25.
And an error detection circuit 26.

The transmission data string in the transmitter 1 is input to the error detection coding circuit 11.

The error detection coding circuit 11 is further provided with a CRC.
Generation unit 11a, bit inverting unit 11b, and switch 11
have c. Then, the transmission data sequence input to the error detection coding circuit 11 is input to the CRC generation unit 11a and the switch 11c, respectively. CRC generator 1
1a generates a CRC bit according to the transmission data string,
It is given to the bit inverting section 11b. Bit inversion unit 11b
Inverts the logic of all the CRC bits given from the CRC generator 11a. Then, the bit inverting unit 11b supplies the CRC bit after inverting the logic to the switch 11c. Switch 11c
Is a bit inversion unit 1 after the transmission data string in accordance with a timing signal given from a timing circuit (not shown).
The transmission data string and the bit inverting unit 11b outputs the bit string in which the CRC bit given from 1b is located.
Select the output of. Then, the bit string output from the switch 11c is given to the convolutional coding unit 12 as an output of the error detection coding circuit 11.

The bit string output from the error detection coding circuit 11 is convolutionally coded by the convolutional coding unit 12 and converted into a coded bit string. The coded bit string is rearranged (interleaved) in order to cope with a burst error in the interleave / framing unit 13, and is converted into a format of a transmission frame and added with control data and the like.

The frame data output from the interleave / framing section 13 is modulated by the transmitter 14, then up-converted to the transmission frequency by the RF section 15, and then transmitted from the antenna 16.

On the other hand, in the receiver 2, the frequency of the signal received by the antenna 21 is down-converted by the RF unit 22 and then demodulated by the receiver 23. As a result, in the frame data obtained by the receiver 23, the deinterleaving / deframing unit 24 extracts the symbol string corresponding to the bit string excluding the control data portion, and deinterleaves the encoded bit string in the original order. The symbol string corresponding to is reproduced.

The reproduced symbol string is used as a Viterbi decoding unit 2
5 is decoded and returned to a bit string in which CRC bits are added to the actual data string (data string corresponding to the transmission data string), and this bit string is input to the error detection circuit 26.

The error detecting circuit 26 further includes a data extracting section 26a, a bit inverting section 26b, a switch 26c and a C.
It has an RC check unit 26d. Then, the bit string input to the error detection circuit 26 is processed by the data extraction unit 26.
a, the bit inverting section 26b, and the switch 26c. The data extraction unit 26a extracts the actual data string from which the CRC bit part has been removed from the input bit string, and outputs this as the received data string. The bit inverting unit 26b inverts the logic of each bit forming the input bit string. Then, the bit string after the logic is inverted is applied to the switch 26c. Switch 2
6c outputs a bit string output by the Viterbi decoding unit 25 at the timing when the actual data portion is input and a bit inverting unit 26b at the timing when the CRC bit portion is input according to a timing signal given from a timing circuit (not shown). CR by selecting each bit string
It is given to the C check unit 26d. CRC check unit 26
The d performs a CRC detection process on the input bit string by a well-known arithmetic process, and outputs the detection result.

Next, the operation of the wireless communication system configured as described above will be described.

First, in the transmitter 1, the CRC generator 11a
Causes the CRC bit to be generated in the same manner as in the past. However, the CRC bit is added to the transmission data string after the logic of each bit is inverted by the bit inverting unit 11b. On the other hand, in the receiving device 2, the bit string obtained by inverting the logic of each bit of the CRC bit part in the bit string reproduced by the Viterbi decoding unit 25 by the bit inverting unit 26b is input to the CRC checking unit 26d. Therefore, at the time of input to the CRC check unit 26d, the CRC bit portion is returned to the CRC bit in the state generated by the CRC generation unit 11a, and the well-known CRC check is correctly performed.

FIG. 2 shows an operation state of the receiving device 2 when receiving an actual data string of all "0". If the actual data string is all “0” as described above, the original C
Although the RC bit is also all “0”, the CRC bit is transmitted as all “1” because the logic of each bit is inverted by the bit inverting unit 11b in the transmitter 1.

The symbol string demodulated by the receiver 23 is a mixture of positive and negative values (+ X / -X) having the amplitude value X of the received signal, as indicated by the reference numeral 101. . However, the symbol approximately corresponding to the actual data string portion shows a value of + X, and the CRC bit portion and the bit portion for convolutional coding added after the CRC portion are mixed with “+ X” and “−X”. There is.

Here, the amplitude value "X" of the signal is usually smaller than X in many cases, because the amplitude of the signal fluctuates depending on the situation such as noise and fading of the transmission line in wireless communication. However, for simplification of the description, an ideal transmission path is assumed and the amplitude is not changed, that is, the amplitude value is fixed.

Such a symbol string is processed by the deinterleave / deframing unit 24 and the Viterbi decoding unit 25, respectively, so that the actual data string portion is exactly as transmitted, as indicated by reference numeral 102. all “0”
, And the bit string whose CRC bit part is all “1” is reproduced. Then, the data extraction unit 26a extracts only the bit string of the actual data portion, so that a received data string of all "0" as indicated by reference numeral 103 is obtained.

On the other hand, the bit string output from the Viterbi decoding unit 25 is replaced by the switch 26c, and the CRC bit portion is replaced with the bit string whose logic is inverted by the bit inverting unit 26b. Since the bit string output by the bit inverting unit 26b is a bit string indicated by reference numeral 104,
From the switch 26c, all as indicated by reference numeral 105
A bit string of "0" is output. And this all
Since the bit string of "0" is input to the CRC check unit 26d and the CRC check is performed, it is determined that there is no error, and the CRC detection result is "OK".

As described above, the bit string of all "0" actually transmitted from the transmitter 1 is output as the received data string, and the CRC detection result becomes "OK".

On the other hand, the operation state of the receiving device 2 when receiving a frame without data is as shown in FIG.

In this case, the symbol sequence demodulated by the receiver 23 is, as indicated by reference numeral 101, indicated by reference numeral 201, although it depends on the conditions of noise and fading on the transmission line.
As indicated by the suffix, the data string has an electric power amplitude value of "0". In this case, due to the characteristics of the Viterbi decoding unit 25, the bit string output from the Viterbi decoding unit 25 also becomes all “0” as indicated by reference numeral 202. Therefore, by extracting only the bit string of the actual data portion by the data extracting unit 26a, a as indicated by reference numeral 203 is added.
A received data string of 11 "0" is obtained.

On the other hand, the bit string output from the Viterbi decoding unit 25 is replaced by the switch 26c, and the CRC bit portion is replaced with the bit string whose logic is inverted by the bit inverting unit 26b. Since the bit string output by the bit inverting unit 26b is a bit string indicated by reference numeral 204,
The switch 26c outputs a bit string as shown by reference numeral 205 in which the actual data portion is all "0" and the CRC bit portion is all "1".

When the actual data part is all "0",
The CRC bit is originally all “0”. Therefore, in the bit string output from the switch 26c, the correspondence between the actual data portion and the CRC bit portion is incorrect. Therefore, this bit string is input to the CRC check unit 26d and the CR
Since the C check is performed, it is determined that there is an error, and the CRC detection result is "NG".

As described above, according to this embodiment, all
The bit string of all “0” is output as the received data string both when receiving the frame of “0” and when receiving the frame without data. But C
The RC detection result is “OK” when receiving a frame of all “0”, whereas it is “NG” when receiving a frame without data, so the frame of all “0” is detected. It is possible to distinguish whether the frame is being received or a frame without data is being received based on the CRC detection result.

Moreover, in the present embodiment, since the CRC bit is only inverted, the additional circuit for that purpose may be very simple, and the increase in the circuit scale of the transmitter 1 and the receiver 2 can be suppressed to a small level. Is. Also, because it does not add extra data to the data to be transmitted,
It can be realized without increasing the load of the system.

(Second Embodiment) FIG. 4 is a block diagram of a radio communication system according to a second embodiment of the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 4, the wireless communication system of this embodiment comprises a transmitter 3 and a receiver 4. The transmitter 3 has an error detection coding circuit 31, a convolutional coding unit 12, an interleave / framing unit 13, a transmitter 14, an RF unit 15 and an antenna 16. The receiving device 4 includes an antenna 21, an RF unit 22, a receiver 23, a deinterleaving / deframing unit 24, and a Viterbi decoding unit 25.
And an error detection circuit 41.

That is, the transmitter 3 of the wireless communication system of the present embodiment is replaced with the error detection coding circuit 11 of the transmitter 1 of the first embodiment, and the error detection coding circuit 3 is used.
1 is provided. The receiving device 4 is provided with an error detecting circuit 41 instead of the error detecting circuit 26 of the receiving device 2 in the first embodiment.

The detection coding circuit 31 further has a CRC generating section 11a, a switch 11c, a bit selection inverting section 31a and an inverting position indicating section 31b.

CRC generator 11a and switch 11c
Thus, the bit string formed by adding the CRC bit to the transmission data string is input to the bit selection inverting unit 31a.
The bit selection inverting unit 31a inverts the logic of some of the bits of the input bit string. Bit selection inversion unit 3
The position of the bit to be inverted in 1a is determined by the inversion position instruction unit
Instructed from 1b. The reversal position instruction unit 31b uses the CRC
The bit selection inversion unit 31a is instructed to invert at the timing when a bit at a predetermined inversion position including at least a part of the bits is input to the bit selection inversion unit 31a. The inversion position is fixedly set by the system, but any bit position may be set as the inversion position as long as it includes at least a part of the CRC bit.

On the other hand, the error detection circuit 41 includes a data extraction section 26a, a CRC check section 26d, and a bit selection inversion section 4.
1a and the reversal position instruction | indication part 41b.

The bit string output from the Viterbi decoding unit 25 is first input to the bit selection inverting unit 41a. The bit selection inverting unit 41a inverts the logic of some of the bits of the input bit string. The position of the bit to be inverted by the bit selection and inversion unit 41a is designated by the inversion position instruction unit 41b. The inversion position instructing unit 41b determines that the bit at the inversion position determined by the system is the bit selection inverting unit 41a.
The bit selection inversion unit 41a is instructed to invert at the timing of being input to the. That is, the reversal position instruction unit 41b instructs the bit selection reversal unit 41a to invert at the same bit position as the reversal position instruction unit 31b in the transmission device 3 has instructed the reversal. Then, the bit strings after the logics of some of the bits are inverted by the bit selection inverting unit 41a are input to the data extracting unit 26a and the CRC checking unit 26d, respectively.

Thus, in this radio communication system, the bit string formed by adding the CRC bit to the actual data is transmitted from the transmitting device 3 after the logic of the bit at the predetermined inversion position is inverted. Then, in the receiving device 4, the Viterbi decoding unit 2
The logic of the bit at the predetermined inversion position of the bit string reproduced in 5 is inverted, and then the data is extracted by the data extraction unit 26a and the CRC detection is performed by the CRC check unit 26d.

Therefore, with respect to the bit string transmitted from the transmitter 3, the CRC detection processing is performed after the logic of the bit whose logic is inverted is returned in the transmitter 3.
Correct CRC detection processing can be performed.

On the other hand, in the bit string of all "0" generated by receiving the frame without data, the logic of some bits is inverted
Since the CRC detection process is performed after the bit string is not “0”, the result of the CRC detection process is “NG”.

Thus, as in the case of the above-mentioned first embodiment, it is determined whether the frame of all "0" is received or the frame of no data is received.
It is possible to make a distinction based on the C detection result.

The present invention is not limited to the above embodiments. For example, in each of the above-described embodiments, CRC bits are used for error detection processing and convolutional coding processing is used for data string coding processing. However, for error detection processing, all "0" such as cyclic codes are used. Any data that generates an error detection bit of the bit string "0" can be applied to the data. The same applies to the encoding process of the data string, and when the power amplitude value of the symbol is “0” in the decoding process on the receiving side, the output data string is all “0”.
The contents of the present invention can be applied to any encoding / decoding process that achieves the following. As such a code, a TURBO code or the like can be considered in addition to the convolutional code, and the code can be applied even when the encoding / decoding process on the data string is not performed.

Further, in each of the above-described embodiments, an example in which the present invention is applied to wireless communication is shown, but it is also possible to apply it to wired communication.

Besides, various modifications can be made without departing from the scope of the present invention.

[0058]

According to the present invention, at the transmitting side, the logic of at least a part of the bits of the error detection code is inverted and transmitted, and at the receiving side, the bit at the same position as the logic of the transmitting side is inverted. Since the error detection is performed after inverting the logic of, the data transmitted from the transmission side and received by the reception side has the logic of each bit restored to the original state before the error detection is performed. , It is possible to perform error detection normally, and if a bit string with all “0” is obtained because a frame without data is received, the logic of at least some of the bits should be inverted. Since error detection is performed after the bit string is not all “0” in the above, it is determined that there is an error.
As a result, there is no signal in the frame and all
It is possible to distinguish the state in which the data of “0” is transmitted by the CRC check.

[Brief description of drawings]

FIG. 1 is a block diagram of a wireless communication system according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an operation state of a receiving device 2 in FIG. 1 when receiving an actual data string of all “0”.

FIG. 3 is a diagram showing an operation state of the receiving device 2 in FIG. 1 when receiving a frame without data.

FIG. 4 is a block diagram of a wireless communication system according to a second embodiment of the present invention.

FIG. 5 is a diagram showing an example of a process of processing a transmission data string.

[Explanation of symbols]

1, 3 ... Transmitting device 2, 4 ... Receiving device 11a ... CRC generator 11b ... Bit inversion unit 11c ... switch 11 ... Error detection coding circuit 12 ... Convolutional coding unit 13 ... Interleave / framing section 14 ... Transmitter 15 ... RF section 16 ... Antenna 21 ... Antenna 22 ... RF section 23 ... Receiver 24 ... Deinterleave / Deframing section 25 ... Viterbi decoding unit 26 ... Error detection circuit 26a ... Data extraction unit 26b ... Bit inverting section 26c ... switch 26d ... Check section 31 ... Error detection coding circuit 31a ... Bit selection inverting section 31b ... Reversal position instruction section 41 ... Error detection circuit 41a ... Bit selection inversion unit 41b ... Reversal position instruction section

Claims (5)

[Claims] 1. A communication system comprising a transmission device and a reception device, wherein the transmission device generates an error detection code based on transmission data, and the error detection code generated by the generation device. Adding means for adding to the transmission data; first inverting means for inverting the logic of a predetermined bit including a part of the bits forming the error detecting code; and the error detecting code being added to the transmission data and the predetermined The receiving device receives the bit string transmitted by the transmitting device; and the receiving device, and the receiving device receives the bit string transmitted by the transmitting device. Separating means for separating the transmission data and the error detection code from the bit string received by the means, and inverting the logic of the predetermined bit. Second inversion means, and determination means for determining the presence or absence of a transmission error based on the transmission data and the error detection code which are separated by the separation means and in which the logic of the predetermined bit is inverted by the second inversion means. A communication system comprising: 2. Generation means for generating an error detection code based on transmission data, addition means for adding the error detection code generated by this generation means to the transmission data, and one for configuring the error detection code. First inverting means for inverting the logic of a predetermined bit including a partial bit, and a bit string formed by adding the error detection code to the transmission data and inverting the logic of the bit at the predetermined position by the first inverting means. A transmitting device comprising: a transmitting unit that transmits the. 3. Receiving means for receiving a bit string transmitted from a transmitting means for transmitting a bit string obtained by adding an error detection code to transmission data and inverting the logic of a bit at a predetermined position, and receiving by this receiving means. Separating means for separating the transmission data and the error detecting code from the generated bit string, second inverting means for inverting the logic of the predetermined bit, and the predetermined inverting means for separating by the separating means. A receiving device comprising: a determination unit that determines the presence or absence of a transmission error on the basis of the transmission data and the error detection code whose bit logic is inverted. 4. A generation means for generating an error detection code based on transmission data, an addition means for adding the error detection code generated by the generation means to the transmission data, and one forming the error detection code. And a first inverting means for inverting a logic of a predetermined bit including a partial bit. 5. A receiving means for receiving a bit string transmitted from a transmitting means for transmitting a bit string obtained by adding an error detection code to transmission data and inverting the logic of a bit at a predetermined position, and receiving by this receiving means. An error detecting circuit comprising: a separating unit that separates the transmission data and the error detecting code from the generated bit string; and a second inverting unit that inverts the logic of the predetermined bit.