JPH096476A - Peripheral equipment - Google Patents

Abstract

PURPOSE: To prevent the bypass of a power supply by avoiding latchup phenomenon with a parasitic diode parasitic to an IC of an input stage to which power is not applied when two signals with different power supplies are connected. CONSTITUTION: In the case of connecting a notebook type computer and an extension box, a protection circuit is provided in the extension box and the connection of signal lines is made via the protection circuit. The protection circuit has a detection power supplying power when power supplies VCC3, VCC of the computer or the extension box are applied and when the power supply VCC3 or VCC only is established, a tri-state buffer or an analog switch interposed to the signal lines is turned off to keep the signal line to be a high impedance state. When both the power supplies are supplied, the tri-state buffer and the analog switch provide an output of a signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a peripheral device, and more particularly to a peripheral device for processing data such as audio and video.

[0002]

2. Description of the Related Art A peripheral device of this type is connected to a computer, especially a notebook or laptop computer, and can process data such as audio and video to reproduce a still image or a moving image or display the image on a computer. An image with a larger screen than a simple image is displayed on a CRT or the like, and further, a CD is reproduced. These peripherals are
It works by connecting to an expansion bus provided by the computer.

FIG. 13 shows a connection example of such peripheral devices. As shown, a notebook type computer 10
Is connected from the expansion bus to the expansion box 25 as a peripheral device by a connection cable CC3, and at the same time, from the RGB output of the computer 10 to the connection cable CC2.
Is connected to the RGB input terminal of the extension box 25. Further, in this example, a composite signal is output from the extension box 25 to the television receiver 15 via the connection cable CC1. Of course, other types of signals such as RGB output and NTSC separate signal can be output for video signals.

[0004]

When the computer 10 and the peripheral device (expansion box) 25 are connected, it is a rule that the power of the two is turned off and the power is turned on at the same time. When only one of the power supplies is turned on, as shown in FIG. 12, it is assumed that an IC provided with an FET in the input stage is used in the circuit on the non-power-supplied side (the second system in the figure). Power is supplied to a power supply circuit on a side to which power is not supplied by a parasitic diode existing in an FET such as a CMOS, and not only the operation becomes unstable, but also other circuits may be damaged in some cases. There was a problem that there was. This problem does not occur if the computer and the peripheral device are operated by separate power supplies, and if both are turned on at the same time, it is actually difficult to turn on and off both power supplies at the same time. It is. Also, from the user's side,
If you do not use the functions of peripheral devices, it is fully possible to turn off the power of peripheral devices, and it is not convenient to use all the power supplies at the same time. It will be something like.

The peripheral device of the present invention aims to solve these problems and improve the handling of the signal lines of the peripheral device connected to the computer via the bus.
The following configuration was adopted.

[0006]

A peripheral device of the present invention is a peripheral device for exchanging signals with a computer and processing data such as audio and video, and is output from the computer. A connector for connecting a plurality of signal lines including an address signal line and a power supply signal line is connected to the power supply signal line through the connector, and the computer is powered on by operating with power from the power supply signal line. Detecting means for detecting that power is being supplied to the peripheral device, and second detecting means for detecting that power is being supplied to the peripheral device.
And a shutoff means for shutting off the electrical connection of the signal line connected to the connector when only one of the first and second detection means detects the power supply. That is the summary.

In this peripheral device, the first and second shut-off means are provided.
When only one of the detection means detects the power supply, the electrical connection of the signal line connected to the connector is cut off, so that the problem of the sneak path caused by the parasitic diode is solved, and the operation of the computer and the peripheral device is eliminated. Is kept normal.

Further, in this peripheral device, when the signal line is a signal line for exchanging signals in one direction, the interruption means is constituted by a tri-state buffer, and the signal line exchanges signals in both directions. In the case of a signal line, it is also preferable to configure it with an analog switch. In this case, it is easy to cope with whether the signal line is bidirectional or unidirectional.

[0009]

Preferred embodiments of the present invention will be described below in order to further clarify the structure and operation of the present invention described above. FIG. 1 is a block diagram schematically showing the configuration of the embodiment of the present invention, and FIG. 2 is a block diagram showing the internal configuration of an expansion box corresponding to the second system. As shown in FIG. 13, the extension box 25 of this embodiment is connected to the notebook computer 10 by connection cables CC2 and CC3.

The correspondence with FIG. 1 will be described. The first system in FIG. Although the battery 12 is shown outside in FIG. 1, the battery 12 is actually housed inside the computer 10. Although a protection circuit 30 described later is shown separately from the second system in FIG. 1 for the sake of explanation, actually,
The protection circuit 30 is housed inside the expansion box 25 together with the power supply 22, and forms the expansion box 25 together with the second system 20. The power supply 22 is actually a DC power supply generated from a commercial power supply as described later.

A basic configuration of an embodiment according to the present invention will be described first. The first system 10 and the second system 20 connect various signals such as an address signal via a connection cable CC3 from an expansion bus. These signal lines are connected on the input side as described in the section of the related art.
It is connected to a CMOS circuit element. Therefore, when the signal lines of both systems are directly connected, as shown in FIG. 12, the power supply of the signal output side is turned on, and the power supply of the signal input side is turned off. In such a case, a current flows through a parasitic diode, causing a so-called latch-up phenomenon. On the other hand, in the present embodiment, the control signals such as the address signal, the data signal, and the read / write are connected via the protection circuit 30, and unless the power supplies of both the systems 10 and 20 are both established. Has a configuration in which the signal line is not in a connected state. Hereinafter, this configuration will be specifically described.

FIG. 2 is a block diagram showing a configuration inside the extension box 25. As shown in FIG. As shown in the figure, the extension box 25 corresponds to the protection circuit 30 and the second system 20 in FIG. 1, and is connected to the host machine, the computer 10, by the host-side power supply VCC3, data D, address A, control C (input C). And output)
They are connected by a connection cable CC3.

The connection cable CC3 is connected to the extension box 25.
On the side, it is connected to connectors CN7 and CN8 provided inside through the back surface of the expansion box 25. FIGS. 8 and 9 show an example of the signal arrangement of the connectors CN7 and CN8. Each signal of the connectors CN7 and CN8 is connected to an expansion bus of the computer 10 by a connection cable CC3. 10 and 11 show the signal arrangement of the connector of the expansion bus on the computer 10 side.

In the second system 20 of the extension box 25, a gate array (G /
A) In addition to 24, a video processing circuit that handles video, CD-
A CD-ROM processing circuit for controlling the ROM, an audio processing circuit for processing audio, and a power supply circuit are housed therein. The configuration of each circuit will be described in detail.

The video processing circuit includes a VGA 26 which is an extended video control circuit for displaying a video on an external CRT, and a frame memory 2 for storing video data.
8, a synchronizing signal generator 40 for generating a synchronizing signal, an encoder 42 for converting an RGB signal into a composite signal, and a signal switch 44. These circuits can cooperate to display an image that is greater than the display capability of the computer 10 on an external CRT. As will be described later, the expansion box 25 includes a CD drive 50 capable of reproducing a CD-ROM and a music CD.
Since this can be driven and controlled, data from the CD-ROM can be displayed on an external television or monitor.
These functions are particularly effective in displaying color images when the connected computer 10 has only a monochrome display. The computer 1
0 is capable of outputting a color image signal, so that the image signal (RG
B signal), which can be switched by the switch 44 to an internally generated RGB signal and selectively output.

The CD-ROM processing circuit comprises a CD drive 50 in which necessary interface circuits and control circuits are built. The audio signal from the CD drive 50 is directly output to a headphone terminal and a direct output terminal of the CD, and a mixer 78 described later.
Is also output. The CD drive 50 is a CD-RO
All control signals and data necessary for reproduction of M and a music CD can be exchanged with the computer 10 side.

The audio processing circuit includes an FM sound source 60, a digital-analog converter 62, an attenuator (manual volume) 64, a headphone amplifier 66, a line-out amplifier 68, a PCM sound source 70, and a high cut filter for cutting aliasing noise. 72, a first mixer 74 for mixing the sound source, a digital attenuator 76 for adjusting the volume of the sound source to be mixed, and a second mixer 78 for mixing the line-in, microphone-in, FM sound source, CD sound source, etc. .

The power supply circuit is an AC / DC converter 8 for extracting DC +5 volts and 12 volts from commercial AC.
0, a DC / DC converter 82 for generating -5 volts for the circuit using the 12 VDC, and a three-terminal regulator 84 for generating another +5 volt from the 12 VDC. In the following description, +5 volts directly output from the AC / DC converter 80 of the power supply circuit is referred to as the peripheral device side power supply VCC.

The structure of the protection circuit 30 is shown in FIGS. As shown in FIGS. 4 and 5, the connection cable CC3
Among the signal lines assigned to the terminals of the connectors CN7 and CN8 to which are connected the signals except for the signal lines related to the power supply, the signals are supplied to the tri-state buffer I provided for the buffer.
C7, 8, 9, 10 (SN74HC244) or analog switch ICs 30, 31, 32 (SN74CBT)
3383). Protect signal PROTECT is connected to gate terminals 1G and 2G of tristate buffer ICs 7 to 10 and bit enable terminal BE of analog switch ICs 30 to 32. Each of these ICs 7 to 10 and ICs 30 to 32 has a detection power supply V
It is connected to operate by CC2.

The above-mentioned protection signal PROTEC
The circuit that generates T is the circuit shown in FIG. This circuit includes a reset detection element IC22 for detecting the state of the peripheral device side power supply VCC output from the power supply circuit, a reset detection element IC23 for detecting the state of the host side power supply VCC3,
It is composed of a NOR gate IC5 that receives the outputs OUT of the two detection elements IC22 and 23 and calculates a logical sum by negative logic, a gate IC5 that inverts its output, and a light emitting diode LED1 that can emit two colors. In the configuration of the NOR gate IC5 and the gate IC5 for inverting its output, one of the inputs of the subsequent gate is fixed to the ground, so that the output drops to the low level only when both inputs of the preceding NOR gate IC5 are both at the low level. OR gate I
It is functioning as C5. The outputs OUT of the reset detection elements IC22 and IC23 are connected to pull-up resistors R121 and R121 by a detection power supply VCC2 described later.
Pulled up via 122. Further, the output OUT of the host-side power supply VCC3 is output via a resistor R76.
It is output as a signal PonB.

This signal PonB is, as shown in FIG.
It is connected to the base of transistor TR1. The emitter of this transistor TR1 is connected to the host side power supply VCC3
The transistor TR1 has a collector connected to a peripheral device side power supply VC via a diode D7.
C is connected. The potential of the collector of the transistor TR1 is output as the detection power supply VCC2.

The light emitting diode LED shown in FIG.
1 indicates that the green light-emitting element is turned on by the detection power supply VCC2, and at this time, when the protect signal PROTECT is at the high level, the red light-emitting element is turned on by the other gate of the IC5, and as a result, the orange light is turned on. Light.
When the protect signal PROTECT goes low,
Since the red light emitting element is turned off, the light emitting diode LED1
Will emit light in green, and as a result, a single light-emitting diode LED1 can issue a warning that it is operating in a single power supply in orange and a notification that it is in a normal operating state in green.

The reset detection elements IC22,
The IC 23 (see FIG. 3) is an open collector output. When the power supply input terminal VCC becomes +4.25 V or more, the transistor in the output stage is turned on, and the potential of the transistor drops to the ground. The output OUT is connected to a pull-up resistor R1
21 and R122, the power supply is pulled up to the detection power supply VCC2. Therefore, when either the power supply VCC3 or VCC is established, the outputs of the reset detection ICs 22 and 23 on the side where the power supply is established become low level.
The signal PonB also goes low, and the transistor TR
1 also turns on. As a result, the host-side power supply VCC3
Alternatively, if any of the peripheral device side power supply VCCs is established, the detection power supply VCC2 is supplied via the transistor TR1 or the diode D7. As a result, since the power supply VCC2 for pulling up the pull-up resistors R121 and R122 is established, the output OUT of the reset detection elements IC22 and IC23 whose output does not fall to low level is kept at high level. As a result, the voltage of each input terminal of the IC 5 is determined to be either the ground level or the high level. In a state where one of the host-side power supply VCC3 and the peripheral device power supply VCC is established and the other power supply is not turned on, only one of the outputs of the reset detection elements IC22 and IC23 has fallen to a low level. IC5
The output of 0, that is, the protect signal PROTECT is at a high level.

When the protect signal PROTECT is at a high level, the gates 1G and 2G of the tri-state buffers IC7 to IC10 are controlled to a high level, and the output of the tri-state buffer enters a high impedance state. Also, the bit enable terminals BE of the analog switch ICs 30 to 32 also become high level,
The analog switch is turned off.

The operation states of the tristate buffer and the analog switch by the protect signal PROTECT will be described in detail with reference to FIGS. 6 and 7. FIG.
FIG. 6 is an explanatory diagram showing a relevant portion in the above-described circuit. In the protection circuit 30, the reset detection element I
The state of the peripheral device side power supply VCC and the state of the host side power supply VCC3 are detected by the C22 and the IC 23, and when at least one of the power supplies is established, the detection power supply VCC2 can be supplied. In addition, either one of the power supply VCC
3, When VCC is established and the other is not supplied,
The protect signal PROTECT is held at a high level. This state is shown in FIG. As shown, the host-side power supply VCC3 is not supplied and the peripheral device-side power supply V
In the state where the CC is established, the output of the gate 102 of the output stage OUT on the computer (first system) 10 side is in the off state. Therefore, the tri-state buffer 100 of the protection circuit 30 outputs the protection signal Even if the high impedance state is established by PROTECT, there is no difference in the effect of the extension box 25 on the gate 101 of the input stage in of the second system 20 side.

On the other hand, the second system 2 of the extension box 25
Since the output of the gate 112 of the output stage OUT on the 0 side is 0 volt or +5 volt, if the analog switch 110 provided in the protection circuit 30 is not turned off, the input stage in on the computer 10 side Gate 1
11 may be transmitted, and latch-up via a parasitic diode may occur. In this embodiment, since the analog switch 110 is kept off by the protect signal PROTECT, the output of the analog switch 110 is in a high impedance state, and the power of the computer 10 is turned off.
Has no effect on the gate 111 of the input stage in.

Further, even when the signal line is bidirectional, the buffer 122 of the second system 20 of the expansion box 25 that is powered on is provided because the analog switch 120 is interposed in the protection circuit 30. Is high (+5 volts), it has no effect on the gate 121 of the input stage of the computer 10 to which power is not supplied.

From the state shown in FIG.
Is turned on, the host-side power supply VCC3 is established. The reset detection element IC23 detects this and inverts its output to a low level, so that the output of the OR gate IC50, that is, the protect signal PROTECT is inverted to a low level. As a result, the tri-state buffers (ICs 7 to 10 in FIGS. 4 and 5 and buffer 100 in FIGS. 6 and 7) are released from the tri-state state and operate as normal buffers. Similarly, analog switch ICs (ICs 30 to 32 in FIGS. 4 and 5 and analog switches 110 and 12 in FIGS. 6 and 7)
0) is turned on, and is bidirectionally conductive. Therefore, in this state, the extension box 25 operates as it is.

According to the above-described embodiment, when the computer 10 as the first system is connected to the expansion box 25 having a built-in peripheral device as the second system, only one of the power supplies is turned on and one of the power supplies is turned on. Is not supplied, there is no problem that power is supplied via the signal line due to the parasitic diode existing in the input stage. As a result, even if the power of the computer 10 is turned on and off and the power of the expansion box 25 is turned on and off independently, no power failure occurs.
Therefore, there is no need to synchronize the turning on and off of the power supply, and the usability is improved.

The embodiments of the present invention have been described above.
The present invention is not limited to such an embodiment at all, for example, a configuration using a relay or a contactless relay instead of a tri-state buffer or an analog switch, and establishing a host-side power supply and a peripheral device-side power supply using a comparator or the like. The configuration for detection and the protection circuit 30
Side, or the protection circuit 30 is an independent device, and the protection circuit 30 is connected to the connection cable CC.
It goes without saying that the present invention can be implemented in various modes without departing from the gist of the present invention, such as the configuration provided in 3.

[0031]

As described above, according to the peripheral device of the present invention, the disconnecting means is connected to the connector when only one of the first and second detecting means detects the power supply. Since the electrical connection of the signal line is cut off, there is an excellent effect that the problem of sneaking in due to the parasitic diode due to one power source can be solved. As a result, the operations of the computer and the peripheral devices are normally maintained even when the timing of the single power supply exists. Therefore, there is no need to synchronize the turning on and off of the power of the computer and the peripheral device, and the usability is greatly improved.

Further, in this peripheral device, when the signal line is a signal line for exchanging signals in one direction, the interruption means is constituted by a tri-state buffer, and the signal line exchanges signals in both directions. If the signal line is an analog switch, it is possible to easily deal with whether the signal line is bidirectional or unidirectional.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram showing the principle of the present invention in one embodiment of the present invention.

FIG. 2 is a block diagram illustrating an internal configuration of a peripheral device according to the embodiment.

FIG. 3 is a circuit diagram showing a circuit related to power supply detection in the protection circuit 30.

FIG. 4 is a circuit diagram showing a part of the protection circuit 30.

FIG. 5 is a circuit diagram showing a part of the protection circuit 30;

FIG. 6 is an explanatory diagram schematically showing the operating principle of the protection circuit 30.

FIG. 7 is an explanatory diagram showing an operation state of the protection circuit 30;

FIG. 8 shows a connector CN7 prepared in the extension box 25.
FIG. 4 is an explanatory diagram showing a signal arrangement of FIG.

FIG. 9 is an explanatory diagram showing a signal arrangement of a connector CN8.

FIG. 10 is an explanatory diagram showing a signal arrangement of an extension bus on the computer 10 side.

FIG. 11 is an explanatory diagram showing the remaining signal arrangement of the expansion bus on the computer 10 side.

FIG. 12 is an explanatory diagram showing the occurrence of power sneak in connection between a conventional peripheral device and a computer.

FIG. 13 is a perspective view showing a state of connection between the computer 10 and the extension box 25.

[Explanation of symbols]

 1G, 2G gate terminal 10 computer (first system) 12 battery 15 television receiver 20 second system 25 expansion box 26 VGA 28 frame memory 30 protection circuit 40 synchronization signal generator 42 Encoder 44 ... Signal switch 50 ... CD drive 60 ... FM sound source 62 ... Analog converter 64 ... Attenuator 66 ... Headphone amplifier 68 ... Line out amplifier 70 ... PCM sound source 72 ... High cut filter 74 ... First mixer 76 ... Digital Attenuator 78 Second mixer 80 AC / DC converter 82 DC / DC converter 100 Tristate buffer 101 Gate 102 Gate 110 Analog switches 111 and 112 Gate 120 Analog switches 121 and 122 Buffer BE: Bit enable terminal CC1: Connection cable CC2: Connection cable CC3: Connection cable CN7: Connector CN8: Connector D7: Diode IC22: Reset detection element IC23: Reset detection element IC30, 31, 32: Analog switch IC5: NOR gate IC50: OR gate IC7, 8, 9, 10 ... tristate buffer PROTECT ... protect signal R121 ... pull-up resistor R76 ... resistor TR1 ... transistor

Claims (2)

[Claims] 1. A peripheral device for exchanging signals with a computer and processing data such as audio and video, comprising a plurality of signal lines including an address signal line and a power supply signal line output from the computer. A first connecting means for connecting the power supply signal line through the connector, and a first detecting means for detecting that the power supply of the computer is turned on by operating from the power supply signal line. When only one of the second detecting means for detecting power supply to the peripheral device and the first or second detecting means detects the power supply, the connector connected to the connector is connected. A peripheral device having a disconnecting means for disconnecting an electrical connection of a signal line. 2. The peripheral device according to claim 1, wherein the cutoff unit is a tri-state buffer when the signal line is a signal line for exchanging signals in one direction, and the signal line is a signal line. A peripheral device that is an analog switch when it is a signal line for bidirectional communication.