JPH0964348A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the breakdown of a gate insulation film when performing plasma etching by forming an opening which reaches a gate electrode on an interlayer insulation film on the gate electrode, forming a conductive coating on an upper surface including the opening, and further forming a conductive resist. SOLUTION: A LOCOS oxide film 11 and a gate insulation film 12 are formed on the surface of silicon substrate 1. Then, a gate electrode 13 is formed on the gate insulation film 12. Then, an interlayer insulation film 2 is formed and a contact hole 21 is formed on the upper portion of the gate electrode 13. Then, a barrier metal layer 31 is formed on an entire surface containing the contact hole 21 and further a metal film 32 is formed. Then, a conductive resist 41 is applied and is subjected to patterning and plasma etching. A positive ion reaching the metal film 32 by plasma etching is neutralized by an electron which moves from the conductive resist 41, prevents an electric charge within a region to be etched from being biased, and prevents the gate insulation film 12 from being broken.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention occurs during a plasma etching process in a method of manufacturing a semiconductor device, and more particularly in a process of forming various wiring layers and their interconnection openings in a process of manufacturing a semiconductor integrated circuit including a MOS transistor. The present invention relates to a method for manufacturing a semiconductor device, which is characterized by a method for forming a multi-layered wiring layer that prevents the gate insulating film from being broken due to biased charge distribution in a resist.

As the functions of semiconductor integrated circuits (VLSI) have become complicated and highly integrated, damage to semiconductor device components in the manufacturing process has become a problem. This problem,
This is due to the layout of the integrated circuit, and is particularly noticeable in a data processor in which a large number of high-performance CMOS logic gates are connected by long wiring (large antenna ratio).

[0003]

2. Description of the Related Art In the conventional plasma dry etching using a resist which is an organic polymer, there is a problem called electron blocking effect.

FIG. 6 and FIG. 7 are explanatory views of the electron shielding effect in the conventional plasma dry etching.
(E) shows each process. This figure schematically shows a cross section of a part of a semiconductor device equipped with a MOS transistor. In this figure, 1 is a silicon substrate, 10 is a MOS transistor, 11 is a LOCOS oxide film, 12 is a gate insulating film, 13 is a gate electrode, 2 is an interlayer insulating film, 2
1 is a contact hole, 3 is a metal film, 4 is a resist, 5
0 is bulk plasma, 51 is an ion sheath, 52 is electrons, 53 is positive ions, 60 is a substrate mounting electrode, and 61 is RF.
A power source and a switch 62.

First Step (See FIG. 6A) A LOCOS oxide film 11 is formed on the surface of a silicon substrate 1 to define an element forming region, a gate insulating film 12 is formed in the element forming region, and a gate insulating film is formed. Gate electrode 13 on 12
To form a MOS transistor 10, a contact hole 21 is formed on the gate electrode 13 of the interlayer insulating film 2 formed thereon, and the contact hole 21 is connected to the gate electrode 13 through the contact hole (opening) 21. Metal film 3
Is formed, and the resist 4, which is an organic polymer, is patterned thereon to form a mask for etching.

The resist 4 which is an organic polymer is usually an insulator, and its sheet resistance is 10 ¹² Ω / □ to 1
It is in the range of about 0 ¹⁵ Ω / □. MOS transistor 1
The silicon substrate 1 on which 0 is formed is placed on the substrate placing electrode 60, which is connected to the RF power source 61 via the switch 62 between the silicon substrate 1 and GND. In this state, the switch 62 remains open.

Second step (see FIG. 6B) When the switch 62 is closed and plasma etching is started, an ion sheath 51 is formed between the silicon substrate 1 and the bulk plasma 50. The substrate mounting electrode 60 on which the silicon substrate 1 is mounted is connected to the RF power source 61 as described above, and a potential difference is generated due to the mobility difference between the electron 52 and the positive ion 53. To satisfy the sex rule,
The self-bias is formed so that the substrate mounting electrode 60 has a negative potential with respect to the bulk plasma 50.

Third step (see FIG. 6C) When positive ions 53 and electrons 52 fly toward the silicon substrate 1 in the ion sheath 51, the self-bias is
It acts as a deceleration electric field for the electrons 52 and as an acceleration electric field for the positive ions 53. Therefore, the silicon substrate 1
The electrons 52 whose kinetic energy has been reduced when reaching the are easily trapped by the resist 4 on the uppermost layer of the silicon substrate 1, but the positive ions 53 are accelerated and the metal film which is the film to be etched is accelerated. It is driven into 3, and is gradually accumulated.

Further, since the electrons 52 are captured by the upper layer portion of the resist 4, the electric field above the narrow wiring space is disturbed, and the electric field in the direction of the silicon substrate 1 is generated by the electrons 52 flying in the ion sheath 51. The deceleration electric field becomes more and more. That is, since the electrons 52 in the ion sheath are shielded by the negatively charged resist 4, positive and negative charges are separated via the resist 4.

Fourth Step (See FIG. 7D) This charge imbalance is caused by the silicon substrate 1 exposed to the plasma.
While the metal film 3 is amplified, the dielectric relaxation of charges is performed to some extent while the metal film 3 is entirely connected in the silicon substrate 1, but all the etched regions of the metal film 3 are etched. Immediately after that, the accumulated charges flow into the gate electrode 13.

Fifth Step (See FIG. 7E) In the MOS transistor 10, the thin gate insulating film 12 is formed between the gate electrode 13 and the channel controlled by the gate electrode 13, but the accumulated charge amount is equal to or higher than the gate breakdown voltage. In many cases, the gate insulating film 12 is destroyed.

[0012]

The problem in conventional plasma etching is that the imbalance between electrons and positive ions for etching is polarized by the resist, and the imbalance is amplified more and more as the etching progresses. It may end up.

The present invention was carried out in order to avoid the accumulation of polarized charges in the resist as described above, and neutralizes the accumulated electrons above the resist and the positive ions that are polarized and accumulated by the accumulated electrons. Even if plasma etching is performed on a long wiring layer having a large ratio, the MOS transistor 1
It is an object of the present invention to provide a method for manufacturing a semiconductor device which does not damage the 0 gate insulating film.

[0014]

MOS according to the present invention
Forming a gate electrode on the gate insulating film of the transistor; forming an opening reaching the gate electrode in the interlayer insulating film deposited on the gate electrode; and forming a conductive film on the upper surface including the opening. And the step of depositing the conductive coating, and by selectively dry etching the conductive coating with the resist formed on the conductive coating as an etching mask, a wiring made of the conductive coating connected to the gate electrode is formed. The method of manufacturing a semiconductor device to be formed is characterized in that the resist is a conductive resist.

In this case, the conductive resist has a sheet resistance of 1 × 10 ¹⁰ Ω / □ or less, and in particular, an aniline polymer can be used.

Further, in this case, the conductive resist is formed by patterning the photoresist formed on the conductive polymer by selective exposure and development, and transferring the pattern of the photoresist to the conductive film. be able to.

1 and 2 are explanatory views of the principle of the method for manufacturing a semiconductor device according to the present invention, wherein (A) to (D) show respective steps. In this figure, 1 is a silicon substrate, 10 is M
OS transistor, 11 is a LOCOS oxide film, 12 is a gate insulating film, 13 is a gate electrode, 2 is an interlayer insulating film, 21
Is a contact hole, 3 is a metal film, 41 is a conductive resist, 50 is bulk plasma, 51 is an ion sheath, and 52 is
Is an electron, 53 is a positive ion, 60 is a substrate mounting electrode, 61 is an RF power source, and 62 is a switch.

First Step (See FIG. 1A) A LOCOS oxide film 11 is formed on the surface of a silicon substrate 1 to define an element formation region, a gate insulating film 12 is formed in the element formation region, and a gate insulating film is formed. Gate electrode 13 on 12
To form a MOS transistor 10, a contact hole 21 is formed on the gate electrode 13 of the interlayer insulating film 2 formed thereon, and a metal film connected to the gate electrode 13 via the contact hole 21. 3 has a sheet resistance lower than that of the conventional one, for example, 10 ⁷ Ω /
The conductive polymer 41 of □ is formed by patterning.

The silicon substrate 1 on which the MOS transistor 10 is formed is connected to the GND via a switch 62 and R
The F power source 61 is mounted on the substrate mounting electrode 60 connected thereto, but the switch 62 remains open in this state.

Second step (see FIG. 1B) When the switch 62 is closed and plasma etching is started, a self-bias is formed so that the substrate mounting electrode 60 produces a negative potential with respect to the bulk plasma. The electrons 52 are captured in the upper layer portion of the conductive resist 41 due to the electron blocking effect, but the electrons 52 move toward the metal film 3 on the surface of the conductive resist 41 because the conductivity of the conductive resist 41 is high. I will do it.

Third step (see FIG. 2C) On the other hand, since the positive ions 53 reaching the metal film 3 are widely distributed in the metal film, the electrons 52 moving from the conductive resist 41 are positive. Neutralize with ion 53.

Fourth step (see FIG. 2D) Therefore, no positive or negative charge is polarized through the conductive resist 41, and electrons are not accumulated in the uppermost layer of the conductive resist 41. The electron shielding effect is extremely small, and sufficient electrons necessary to neutralize the implanted positive ions are supplied.

Therefore, there is no bias of the charges in the substrate 1 to be etched exposed to the plasma, and even if all the regions to be etched are etched, the accumulated charges are extremely small. The quantity is also extremely small. That is, the electric charge polarized in the gate insulating film 12 of the MOS transistor 10 is very small, and the gate insulating film 12 is not destroyed.

The material of the conductive resist 41 used in the present invention is not particularly limited, but as will be described later, a sheet resistance of 10 ¹⁰ Ω / □ or less, preferably 10 ⁷ Ω.
The following can be used. As the conductive resist, substituted and unsubstituted conductive polymers, specifically, polyanilines, polyparaphenylene vinylenes, polythiophene vinylenes, polyfuran vinylenes, polypyrrole vinylenes, polythiophenes, polymazines, polyfurans, poly Selenophenones, polypyrroles, poly-p-phenylene sulfides, polystyrene having halogenated alkyl groups, polyacetylene formed from soluble precursors, quaternary ammonium ion type polymers and their derivatives, and low molecular charges Examples thereof include a transfer complex and a binder polymer mixture, and in particular, an aniline-based polymer having excellent conductivity and film forming property can be recommended as an optimum material.

Organic acids [monocarboxylic acids (formic acid, acetic acid, glycolic acid, methoxyacetic acid, etc.), dicarborinic acid (phthalic acid, tetrahydrophthalic acid, quinolinic acid, maleic acid) described in JP-A-3-267941) acid,
Oxysulfonic acid, glutaric acid, phenylmalonic acid, etc.), sulfonic acid (toluenesulfonic acid, benzenesulfonic acid, methanesulfonic acid, etc.), mineral acid (hydrochloric acid, sulfuric acid, etc.), boron complex (ethylene glycol boron complex, shu) Acid boron complex etc.), a quaternary ammonium salt of a compound such as a coordinating compound (acetylacetone etc.), or Y.
Todokoro et al. IEEE, IEDM8
7, pp 753-756 (1987) and the like, it is simple and preferable in terms of steps to form a resist pattern using a conductive polymer having photosensitivity, such as an ammonium polymer (p-styrene sulfonate). However, since many of the usual conductive polymers do not have photosensitivity, a suitable conductive resist pattern can be formed by forming the photosensitive polymer on the conductive polymer as the lower layer material. .

Specifically, a conductive polymer layer is formed on a substrate to be processed, an upper resist layer having excellent oxygen plasma resistance such as photosensitive silicon is formed on the conductive polymer layer, and this is exposed and developed to be patterned. After that, a method of transferring the pattern to the conductive polymer of the lower layer by oxygen plasma etching (two-layer resist method), and an intermediate layer excellent in oxygen plasma resistance such as silicon on the conductive polymer formed in the same manner. To form a normal photoresist layer on it, or to expose and develop it to pattern the polymer in the upper layer, and then transfer the pattern to the intermediate layer by fluorine-based plasma etching, and then transfer this pattern to oxygen plasma. A suitable conductive resist is obtained by the method of transferring to the conductive polymer of the lower layer by etching (three-layer resist method). It is possible to realize a turn.

According to the present invention, since it is possible to avoid the accumulation of polarized charges in the resist, electron shielding is relaxed, the accumulated electrons above the resist and the positive ions that are polarized and accumulated thereby are neutralized, and the antenna ratio is long. Even if the wiring layer is plasma-etched, the gate insulating film is not destroyed, and as a result, a highly reliable semiconductor device manufacturing method can be provided.

[0028]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 3 is an explanatory view of a first embodiment of a method for manufacturing a semiconductor device according to the present invention.
(B) shows each process. In this figure, 1 is a silicon substrate, 10 is a MOS transistor, and 11 is a LOC.
OS oxide film, 12 is a gate insulating film, 13 is a gate electrode,
Reference numeral 2 is an interlayer insulating film, 21 is a contact hole, 31 is a barrier metal layer, 32 is a metal film, and 41 is a conductive resist.

First step (see FIG. 3A) LOCO is selectively formed on the surface of the silicon substrate 1 by thermal oxidation.
An S oxide film 11 is formed to define an element forming region, a gate insulating film 12 is formed in the element forming region by thermal oxidation, and a gate electrode 13 is formed on the gate insulating film 12 to form a MOS transistor 10. A contact hole 21 is formed on the gate electrode 13 of the inter-layer insulating film 2 made of BPSG formed on the gate electrode 13 by using a lithography means, and the entire surface including the contact hole 21 is formed. Titanium nitride (Ti
A barrier metal layer 31 made of N) is formed, and a metal film 32 made of an Al alloy is further formed thereon.

Second step (see FIG. 3B) In processing this Al / TiN laminated film as a wiring pattern, a conductive resist 41 which is an aniline polymer serving as an etching mask is formed on the Al / TiN laminated film. A predetermined shape is patterned by applying, selectively exposing and developing. Then, using this etching mask, the Al / TiN laminated film that is the film to be etched is etched using chlorine-based plasma.

By this plasma etching, the positive ions that have reached the metal film 32 are neutralized with the electrons moving from the conductive resist 41, and the positive or negative electric charge is polarized through the resist as in the prior art. In addition, since electrons are not accumulated in the uppermost layer of the resist, the electron shielding effect is extremely small, and electrons necessary for neutralizing the implanted positive ions are supplied.

Therefore, there is no bias in the charge in the etched region exposed to the plasma, and even if all the etched regions are etched, the accumulated charge is extremely small, and therefore the amount of charge flowing into the gate electrode 13 is large. Is also extremely small. That is, the electric charge polarized in the gate insulating film 12 of the MOS transistor 10 is very small, and the gate insulating film 12 is not destroyed. In this embodiment, since only one layer of conductive resist 41 is used, the number of steps is small and the throughput can be improved.

(Second Embodiment) FIG. 4 is an explanatory view of a second embodiment of a method for manufacturing a semiconductor device according to the present invention, in which (A) and (B) show respective steps. . In this figure, 1 is a silicon substrate, 10 is a MOS transistor,
11 is a LOCOS oxide film, 12 is a gate insulating film, 13 is a gate electrode, 2 is an interlayer insulating film, 21 is a contact hole, 31 is a barrier metal layer, 32 is a metal film, 411 is a sulfonated polyaniline derivative, 412 is siloxane. Polymer 413 is a novolak i-ray resist.

First step (see FIG. 4A) LOCO is formed on the surface of the silicon substrate 1 by selective thermal oxidation.
An S oxide film 11 is formed to define an element forming region, a gate insulating film 12 is formed in the element forming region by thermal oxidation, and a gate electrode 13 is formed on the gate insulating film 12 to form a MOS transistor 10. A contact hole 21 is formed on the gate electrode 13 of the inter-layer insulating film 2 made of BPSG formed on the gate electrode 13 by using a lithography means, and the entire surface including the contact hole 21 is formed. Titanium nitride (Ti
A barrier metal layer 31 made of N) is formed, and a metal film 32 made of an Al alloy is further formed thereon.

Second step (see FIG. 4B) In processing the Al / TiN laminated film as a wiring pattern, a conductive resist serving as an etching mask is formed on the Al / TiN laminated film. In the above form, a three-layer resist is used. That is, a sulfonated polyaniline derivative (aquaSAVE manufactured by Nitto Kagaku Kogyo Co., Ltd.) 411 which is a conductive polymer is used as the lower layer, a siloxane polymer 412 is used as the intermediate layer, and a novolac i-line resist 413 is used as the uppermost layer.

These polymers are coated in order from the lower layer, and the uppermost novolak-based i-line resist 41 is formed.
3 is exposed by an i-line exposure device, developed, and patterned into a predetermined shape. Then, using the patterned uppermost novolak i-ray resist 413 as an etching mask, the intermediate layer siloxane polymer 412 is etched using fluorine plasma, and the uppermost novolac i-ray resist 413 is etched. Is transferred to the siloxane-based polymer 412 of the intermediate layer. Furthermore, the sulfonated polyaniline derivative 41 of the lower layer
1 is etched using oxygen plasma, and the pattern of the siloxane-based polymer 412 in the intermediate layer is transferred to the sulfonated polyaniline-based derivative 411 in the lower layer.

Finally, the remaining intermediate layer siloxane polymer 412 is removed by etching using fluorine plasma to complete the etching mask of the lower layer sulfonated polyaniline derivative 411 which is a conductive polymer. Using this etching mask, the Al / TiN laminated film that is the film to be etched is etched using chlorine-based plasma.

By this plasma etching, the positive ions that have reached the metal film 32 are neutralized with the electrons moving from the sulfonated polyaniline derivative 411 which is a conductive polymer, and the positive and negative ions are passed through the resist as in the prior art. Charge does not polarize, and electrons do not accumulate in the uppermost layer of the resist, so the electron blocking effect is extremely small, and the electrons necessary to neutralize the implanted positive ions are supplied. .

Therefore, there is no bias in the charge in the etched region exposed to the plasma, and even if all the etched regions are etched, the accumulated charge is extremely small, and therefore the amount of charge flowing into the gate electrode 13 is large. Is also extremely small. That is, the electric charge polarized in the gate insulating film 12 of the MOS transistor 10 is very small, and the gate insulating film 12 is not destroyed.

In this embodiment, the sulfonated polyaniline derivative 41, which is the conductive polymer in the lower layer, is used.
1. Since a conductive resist including a siloxane-based polymer 412 for the intermediate layer and a novolac-based i-line resist 413 for the uppermost layer is used, a photoresist having a high resolution for exposure and development and a polymer having a high etching resistance for dry etching The conductive polymers can be combined so as to satisfy the optimum conditions depending on the exposure and development method used, the etching method used, the desired conductivity and the like.

FIG. 5 is an explanatory view of the relationship between the good rate of the MOS capacitor and the antenna ratio when resists having different sheet resistances are used. The sheet resistance of the conductive resist evaluated was 3 × 10 ⁷ Ω / □ and 1 × 10 ¹⁰ Ω / □, and a novolac-based single-layer resist (1 × 10 ¹² Ω / □ was used as a reference).
Ω / □) was used.

As a sample structure, a MOS capacitor having a gate oxide film with a thickness of 80 nm was prepared, and the presence or absence of damage when forming an Al wiring connected to the MOS capacitor having a predetermined antenna ratio was checked for I- of the MOS capacitor. It was judged from the V characteristic. The antenna wiring structure has an Al wiring thickness of 0.7 nm and a resist pattern of 0.59 μ space.
m, and the height was 1.7 μm. The aspect ratio when the wiring is formed by etching is due to the reduction of the resist film.
It is 4.

An ECR (bias frequency 13.56 MHz) was used for the etching device. This figure shows the MO of a sample using a conductive resist having three types of sheet resistance.
The results of actually measuring the survival rate of the S capacitor by changing the antenna ratio (wiring area / gate area) are shown. When the survival rate was calculated, the breakdown at Vg ≦ 5V was regarded as the gate breakdown, and the breakdown at this voltage was regarded as being alive. From the results shown in this figure, it was found that the effect is obtained even when the sheet resistance is 1 × 10 ¹⁰ Ω / □.

[0044]

As described above, according to the present invention,
Accumulation of polarization charges in the resist can be avoided, electron shielding, which has been a problem in the past, is mitigated, and the accumulated electrons above the resist and the positive ions that are polarized and accumulated are neutralized. Even if plasma etching is performed, the gate insulating film is not destroyed,
It greatly contributes to the provision of a highly reliable semiconductor device manufacturing method.

[Brief description of drawings]

FIG. 1 is an explanatory view (1) of the principle of a method for manufacturing a semiconductor device of the present invention, in which (A) and (B) show respective steps.

FIG. 2 is an explanatory view (2) of the principle of the method for manufacturing a semiconductor device of the present invention, in which (C) and (D) show respective steps.

FIG. 3 is an explanatory diagram of the first embodiment of the method for manufacturing a semiconductor device of the present invention, in which (A) and (B) show respective steps.

FIG. 4 is an explanatory diagram of the second embodiment of the method for manufacturing a semiconductor device of the present invention, in which (A) and (B) show respective steps.

FIG. 5 shows M when resists having different sheet resistances are used.
It is an explanatory view of the relationship between the OS capacitor non-defective rate and the antenna ratio.

FIG. 6 is an explanatory diagram (1) of an electron blocking effect in conventional plasma dry etching, and (A) to (C) show respective steps.

FIG. 7 is an explanatory view (2) of the electron blocking effect in the conventional plasma dry etching, and (D) and (E) show respective steps.

[Explanation of symbols]

 1 Silicon Substrate 10 MOS Transistor 11 LOCOS Oxide Film 12 Gate Insulating Film 13 Gate Electrode 2 Interlayer Insulating Film 21 Contact Hole 3 Metal Film 31 Barrier Metal Layer 32 Metal Film 4 Resist 41 Conductive Resist 411 Sulfonated Polyaniline Derivative 412 Siloxane Polymer 413 Novolak-based i-line resist 50 Bulk plasma 51 Ion sheath 52 Electrons 53 Positive ions 60 Substrate mounting electrode 61 RF power supply 62 Switch

Claims (4)

[Claims] 1. A step of forming a gate electrode on a gate insulating film of a MOS transistor, a step of providing an opening reaching the gate electrode in an interlayer insulating film deposited on the gate electrode, and a step of forming the opening. The step of depositing a conductive film on the upper surface including the conductive film connected to the gate electrode by selectively dry etching the conductive film using the resist formed on the conductive film as an etching mask. A method of manufacturing a semiconductor device for forming a wiring formed of a conductive film, wherein the resist is a conductive resist. 2. The sheet resistance of the conductive resist is 1 × 10.
^The method for manufacturing a semiconductor device according to claim 1, wherein the resistance is ¹⁰ Ω / □ or less. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the conductive resist is an aniline-based polymer. 4. A conductive resist is formed by patterning a photoresist formed on a conductive polymer by selective exposure and development, and transferring the pattern of the photoresist to the conductive film. The method for manufacturing a semiconductor device according to claim 1.