JP2003324198A - Inverter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that integration is difficult. <P>SOLUTION: A source electrode layer, a semiconductor layer, and a drain electrode layer are successively laminated, and a gate insulating layer and a gate electrode layer are successively disposed so as to be vertically erected in contact with one-sidewalls of the layers. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inverter which is a basic constituent element of various integrated circuits and the like.

[0002]

2. Description of the Related Art A field effect transistor using an amorphous Si semiconductor material for an active layer has been known in the past and manufactured as an industrial product. In a typical structure of this field effect transistor, as shown in FIGS. 11 and 12, it is arranged horizontally with respect to the substrate. Figure 11
Is DB Thomasson & al., IEEE El. Dev. Lett., Vo
1 shows the device structure of a field effect transistor using hydrogenated amorphous Si described in L. 18, p. 117; March 1997. In FIG. 11, 11 is a substrate, 12 is a source electrode made of aluminum, 13 is a drain electrode made of aluminum, 14 is a gate electrode, 15 is a gate insulating layer,
16 is a semiconductor channel part.

FIG. 12 shows A. Dodabalapur & al., Appl. Ph.
1 shows the structure of a field effect transistor using an organic compound shown in ys. Lett., Vol. 69, pp. 4227-29, December 1996. In FIG. 12, 17 is a substrate, 18 and 19 are drain and source electrodes, 20 is a gate electrode, 21
Is an insulating layer, and 22 is a semiconductor channel portion. In these field effect transistors, the source region and the drain region are separated by a channel region which is electrically neutral. In addition, the gate electrode is electrically separated by the gate insulating film and is arranged above the channel region in the active layer.

In these field effect transistors, an inorganic amorphous material, an inorganic polycrystal material, a π-conjugated polymer as an organic material, an aromatic molecule or the like is used as a semiconductor material forming an active layer. In these typical field effect transistor structures, the electric field applied from the gate electrodes 14 and 20 through the gate insulating films 15 and 21 acts on the semiconductor channel portions 16 and 22, and the source electrodes 12 and
A transistor operation is realized by passing a current through the semiconductor channel portions 16 and 22 between the drain electrode 18 and the drain electrodes 13 and 19.

A thin film transistor using an organic semiconductor material has been vigorously studied in recent years because of its simple manufacturing method, and is characterized by an element manufacturing process that does not use a vacuum as compared with a Si-based material. In addition, it is characterized in that it is inexpensive due to a simple process and a simple manufacturing method, such as a large area and uniform device fabrication, and electrode wiring without forming a source region / drain region. On the other hand, a thin film transistor using an organic semiconductor material has a lower carrier mobility (showing transistor performance) than a thin film transistor using a Si-based material, and has problems in terms of large current and high speed operation.

The solution to this problem found in most publications has been the development of organic materials. For example, in order to realize high carrier mobility, one in which the conjugated state of a π-conjugated polymer is controlled, one in which molecular electrical conduction anisotropy is used by using a molecular orientation technique, and an organic molecular film is formed by a vapor deposition method. For example, it is one that achieves high crystallinity when obtained.

The operation of the field effect transistor shown in FIGS. 11 and 12 is performed by the source electrodes 12 and 18 and the drain electrode 1.
With the voltage applied between the gate electrode 1 and the gate electrode 3,
A voltage is applied to 4 and 20 to induce a channel at the interface between the gate insulating films 15 and 21 and the semiconductors 16 and 22, and the source electrodes 12 and 18 and the drain electrode 1 are passed through this channel.
An electric current is passed between 3 and 19. Here, the current Id between the source electrodes 12 and 18 and the drain electrodes 13 and 19 can be generally expressed by the following equation (1).

[0008]

[Equation 1]

The improvement of transistor performance is to realize a higher Id value within a limited transistor size (W: gate width, L: gate length). From the equation (1), there is an increase in Cox and μ as a factor (other than W and L) that improves Id. Japanese Unexamined Patent Publication No. 10-270712 describes a thin film transistor device structure in which effective Cox is improved by using a material having a high relative dielectric constant.
A thin film transistor whose μ has been improved by the development of a conjugated polymer material is described, and Japanese Patent Laid-Open No. 2001-94107 describes an organic semiconductor device whose μ is improved by an organic molecule vapor deposition method. These were all transistors having the structures shown in FIGS. 11 and 12.

In the equation (1), it is a good idea to reduce L in particular in order to obtain a high Id. This corresponds to the transition of shrinking the gate length in Si technology. S
In i-technology, the gate length of 10 μm width was initially reduced to about 0.1 μm. This is C
It produces 100 times increase in Id value without development of ox and μ. This tendency of the short gate length mainly depends on the improvement of the lithography processing limit. Transistors using organic semiconductors have a prototype gate width of 10 to 5 μm.

The characteristic of the organic semiconductor is low manufacturing cost, and the use of the lithographic processing developed by Si technology for manufacturing the organic semiconductor is contrary to the concept of the low manufacturing cost which is the characteristic of the organic transistor. The adoption of lithographic processing technology that is active in manufacturing is impossible. As a method for manufacturing an organic transistor, a method of concept called soft lithography has been proposed,
When this method is used, it is the current situation that only the above-mentioned gate length of 10 μm to 5 μm can be manufactured. Therefore, it is difficult to quickly reduce the gate length.

In view of such a background, the present inventors have found that a source electrode layer, a semiconductor layer, and a drain electrode layer are sequentially stacked, and a gate is provided upright in a vertical direction so as to be in contact with one side wall of these layers. A so-called vertical type field effect transistor, which has an insulating layer and a gate electrode layer in sequence, was proposed, and the characteristics were dramatically improved.

On the other hand, the field effect transistor uses Si as an active layer and is practically used as a semiconductor device.
Specifically, in addition to being used as an individual semiconductor element, I
Assembled as a C element to realize various functions. However, the transistors using the organic semiconductor in the active layer are not made up of the following two or three other than the individual transistors, and can be realized only by the individual transistors, so that the function is limited and the application is extremely difficult. It was limited.

Japanese Patent Laid-Open Nos. 5-152560 and 9-199732 disclose only proposals relating to a device in which a plurality of transistors are combined. Type transistor is not.
FIG. 13 shows an inverter circuit, and FIG. 4 is for explaining the operation thereof. The inverter responds to the input signal
It is an element that generates a reverse signal as an output signal. In the inverter, when 5V is applied as the power supply voltage and 5V is input as the input signal, 0V is output, and when the input signal is 0V, 5V is output.

This inverter, as shown in FIG.
The configuration is such that one switching transistor 23 and a load resistor (load element) 24 are connected. As shown in FIG. 14A, when the input signal is 0V, the switching transistor 23 is turned off and the power supply voltage of 5V is output to the output side, and as shown in FIG. 14B, the input signal is 5V. At this time, the switching transistor 23 is turned on,
The power supply voltage of 5V causes a current to flow to the ground, and as a result, the output terminal becomes 0V. Although the n-type switching transistor 23 has been described in the above description, it goes without saying that the same inverter operation is exhibited when a p-type transistor is used and -5 V is supplied as the power supply voltage.

FIG. 15 shows an inverter using a conventionally proposed lateral field effect transistor described in Japanese Patent Laid-Open No. 5-15256. In FIG. 15, reference numeral 1 is a switching element that electrically opens and closes, and 2 is a load element that is connected in series to the switching element 1 and acts as an electrical load. 3 is an input terminal of the inverter, 4 is an output terminal of the inverter, and 5 is a constant voltage terminal connected to the power supply V _DD . Reference numerals 6, 7, and 8 denote a drain electrode, a source electrode, and a gate electrode of the switching element 1, respectively, and the drain electrode 6 and the source electrode 7 are arranged to face the gate electrode 8 with a gap between them. Drain electrode 6
Is connected to the output terminal 4, the source electrode 7 is connected to the ground, and the gate electrode 8 is connected to the input terminal 3.

When an inverter is designed by using the organic semiconductor performance described in Science 290, No. 15 (2000), page 2123, the transistor on resistance is set to 40 MΩ and the load resistance value is set to a value sufficiently larger than this. For example, if the value is 10 times 400 MΩ and a design rule of 5 μm is used, the required transistor occupation area is 200 μm × 2.
On the other hand, when the load resistance part uses a polyethylenedioxythiophene (PEDOT) -based conductive polymer,
Since this material has a relatively high resistivity of 10 ³ Ωcm, it can be relatively downsized to 30 μm × 30 μm. That is, the integration of the elements may be achieved by downsizing the switching transistor.

[0018]

A conventional semiconductor device using an organic semiconductor as an active layer can be realized only as an individual transistor and is difficult to integrate. Therefore, its function is limited and its application is limited. There is a problem that It is an object of the present invention to provide an inverter that is easy to integrate.

[0019]

In order to achieve the above object, the invention according to claim 1 has a switching element and a load element electrically connected to the switching element, and is a vertical field effect transistor. In the inverter using as a switching element, a source electrode layer, a semiconductor layer, and a drain electrode layer are sequentially stacked, and the gate insulating layer and the gate electrode layer are erected vertically so as to be in contact with one side wall of these layers. They are provided in sequence.

According to a second aspect of the present invention, in the inverter according to the first aspect, the load element is electrically connected to the vertical field effect transistor as a load resistance element. According to a third aspect of the present invention, in the inverter according to the first aspect, the vertical field effect transistor is a vertical field effect transistor in which the semiconductor layer is made of an organic semiconductor material.

According to a fourth aspect of the present invention, in the inverter according to the second aspect, the load element is made of an organic compound having electric conduction characteristics. According to a fifth aspect of the present invention, in the inverter according to the second aspect, the load element has a sandwich structure of a lower electrode film, a resistance film, and an upper electrode film.

The invention according to claim 6 is the inverter according to any one of claims 1 to 5, which is formed on an insulating substrate. According to a seventh aspect of the present invention, in the inverter according to the first to sixth aspects, a source electrode, a drain electrode, a gate electrode, a load resistance element, and an electrode of a wiring electrode for electrically connecting the switching element and the load resistance element. The film is made of a conductive material group including organic substances.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention is an inverter which is a basic constituent element such as a logic gate, a memory IC, a switching element and an amplifying element, and uses a vertical organic transistor. The characteristics of the vertical transistor are that the operating current is dramatically improved and the area occupied by one element is very small. Therefore, when a plurality of transistors are combined to form a logical operation element, Compared with this, there is a point that it becomes easy to make a dramatic integration.

The embodiment of the present invention is a field-effect transistor formed on a substrate, in which a source electrode, a semiconductor layer, and a drain electrode are laminated, and an insulating region and a gate electrode region are formed in a portion different from the semiconductor region. In the vertical field effect transistor in which the current flowing between the source electrode and the drain electrode flows in a direction substantially perpendicular to the substrate surface, each electrode is formed in a polygonal prism shape. Therefore, the integration of the device becomes easy. The embodiment of the present invention can be partially or entirely made of an organic material.

1 and 2 show an example of the present invention. Figure 1
2 does not show the gate insulating film and the inter-element insulating film for simplification of the drawing, and FIG. 2B shows the respective parts 34, 35, 37, 38 of this example separately and arranged vertically. There is. The inverter of this example includes an active layer portion 34 in which a drain electrode 31, a semiconductor layer 32 (having a thickness of this channel), and a source electrode 33 are sequentially stacked, and a vertical direction so as to contact one side wall of these layers 31 to 33. A vertical field effect transistor 36 made of an organic semiconductor material as a switching element is formed by a gate portion 35 in which a gate insulating layer and a gate electrode layer are sequentially provided in a vertical direction.

Further, this inverter is composed of a lower electrode film, a resistance film, an organic compound having an electric conduction characteristic,
A load resistance layer (load element) portion 37 having a sandwich structure of an upper electrode film, an input portion 38 and an output portion 39 made of a conductive member are provided, and each portion 36 to 39 is an insulating substrate 4.
0 is formed in a polygonal column shape, for example, a regular hexagonal column shape, and the active layer portion 34, the load resistance layer portion 37, the input portion 38, the output portion 39
Are both patterned electrodes 4 on the insulating substrate 40.
Connected by 1.

A load resistance layer portion 37 is electrically connected to the vertical field effect transistor 36, and a drain electrode 31 of the active layer portion 34 is grounded via a lead wire. Active layer part 3
4 is the patterning electrode 4 on the substrate 40.
1 connects to the load resistance layer section 37 and the output section 39. The gate electrode layer of the gate portion 35 is connected to the input signal source via the patterning electrode 41 on the substrate 40, the input portion 38, and the lead wire, and the load resistance layer portion 37 is opposite to the end portion connected to the source electrode 33. The voltage of the power supply V _DD is applied to the end portion on the side through the lead wire, and the output portion 39 is connected to the source electrode 3
An output signal is output from the end opposite to the end connected to 3 via the lead wire.

The vertical field effect transistor 36 formed by the active layer portion 34 and the gate portion 35 is turned off when the input signal applied to the gate electrode layer is 0 V, and the output portion 39.
The power supply voltage is output from. In the vertical field effect transistor 36 formed by the active layer portion 34 and the gate portion 35, the input signal applied to the gate electrode layer is, for example, 5
When it is V, it is in the ON state, and a current flows to the ground due to the power supply voltage, and as a result, the output signal of the output unit 39 is 0V.
become.

Thus, the vertical field effect transistor 3
By using No. 6, the element can be downsized, and since each electrode is a polygonal column, it is suitable for integration, and the electrode leads are connected only on the upper surface (the lead wire is active). By being connected only to the upper surfaces of the layer portion 34, the load resistance layer 37, and the output portion 39), it becomes suitable for electrical connection.

A vertical field effect transistor that constitutes an inverter according to an embodiment of the present invention will be described below with reference to the drawings. In the drawing, only the minimum unit that constitutes the vertical field effect transistor is shown. FIG. 3 shows a vertical field effect transistor device structure according to an embodiment of the present invention. In FIG. 3, reference numeral 51 denotes an insulating substrate, which is preferably an insulating material such as glass or a polymer sheet. The active layer region 52 has a structure in which a source region 53, a semiconductor region 54, and a drain region 55 are sequentially laminated in a film shape. The gate electrode 56 is arranged in a region different from the active layer region 52, and has a structure for applying an electric field to the active layer region 52 via the gate insulating film 57.

A source region, a channel region (semiconductor region), and a drain region are generally defined as an active layer region in the transistor structure of a Si semiconductor element, and the vertical field effect transistor according to the embodiment of the present invention also follows this classification. There is. For Si semiconductor elements, Si material and Al
In order to ensure good electrical continuity in the wiring (to obtain ohmic contact), impurity diffusion processing is performed, and this portion, the electrode contact portion, and the electrode are used as the source region and the drain region.

Therefore, the source electrode or the source region of the vertical field effect transistor according to the embodiment of the present invention refers to a portion including the electrode film, the buffer film for obtaining good electrical contact with the semiconductor element, and the like. . The organic semiconductor material described later may include both the charge transfer layer and the electrode film that serve to transfer charges. On the other hand, some materials of the organic semiconductor material may form good electrical contact with the metal film without passing through the buffer film. In that case, in the vertical field effect transistor of the embodiment of the present invention, The source electrode or the source region simply means an electrode film.

4 and 5 show the classification of these vertical field effect transistors. In the vertical field effect transistor shown in FIG. 4, the active layer region 52 includes the semiconductor layer 54,
The first electrode film 58, the buffer films 59 and 60, and the second electrode film 61 are laminated. In the vertical field effect transistor shown in FIG. 5, the active layer region 52 includes the semiconductor layer 5
4, a first electrode film 58, and a second electrode film 61.

Further, the vertical field effect transistor may have a function of reducing the OFF current of the field effect transistor as another buffer layer function. There are two members, electrons and holes, in the conduction carriers that contribute to electric conduction. A material having an electron transport function is used as the buffer layer of the hole transport type semiconductor material, and a buffer film of the electron transport type semiconductor material is used. A material having a hole transport function may be used. In the device configured as described above, since the conduction carriers conduct over the slight potential barrier formed at the interface between the semiconductor layer and the buffer layer, the conduction carriers particularly effectively act to reduce the off current of the field effect transistor. To do.

FIG. 6 shows connections for applying a gate voltage and a source-drain voltage when operating the field effect transistor. Source region 53 and drain region 55
When the current I _d flowing between the source region 53 and drain region 55 by the source-drain voltage V _DS that is applied to the application of a gate voltage V _G to the gate electrode 56 between,
An electric field acting on the active layer region 52 via the gate insulating film 57 forms a channel at the interface between the semiconductor region 54 and the gate insulating film 57, and I _d flows. This I _d flows through the arranged source region 53 and drain region 55, so that the current I _d flows so as to be orthogonal to the surface of the substrate 51. It can be seen from FIG. 6 that the film thickness of the semiconductor layer 54 corresponds to L in the equation (1), and a dramatic short channel length can be realized without using photolithography.

Next, a preferable method for manufacturing a field effect transistor will be described with reference to FIG. Au is deposited as the first electrode film 53 on the insulating glass substrate 51 by a well-known thin film forming method such as vapor deposition. In general, since the glass substrate and the Au film have poor adhesion, it is preferable to dispose a Cr, Ti, Ta film or the like as an adhesion layer between the glass substrate 53 and the Au film.

When an Au film is used as the first electrode film 53, the alkanethiol-based organic material forms a self-regulating monomolecular adsorption film on the Au surface. Alkanethiol is transferred, Au is removed by wet etching, and the first electrode pattern 53 is formed.

In the microcontact printing method, as shown in FIGS. 8A to 8D, a negative pattern having a desired pattern shape is formed on a master (base material, mainly a Si substrate is used) 63. In this case, the negative pattern is produced by photolithography etching.
That is, as shown in FIG. 8B, a photoresist 64 is coated on the master 63, and after exposing and developing a desired pattern shape as shown in FIG. Etch as shown to form a negative pattern.

Next, as shown in FIG. 8 (e), the master 6
After pouring polydimethylsiloxane 65 into 3 and heat-treating it, a plate 66 is produced by peeling it off from the master 63 as shown in FIG. Polydimethylsiloxane is a flexible resin, and transfer from the master pattern has a resolution of about 5 μm under proper conditions. As shown in FIG. 8 (g), the alkanethiol ink 67 is attached to the plate 66 thus formed, and as shown in FIG. 8 (h).
By transferring to the Au vapor-deposited film on the Au vapor-deposited film substrate 68, an alkanethiol self-controlled textured film is formed. In this textured film, since Au and a thiol group are bonded and the alkyl groups are exposed on both surfaces, when the Au vapor deposition film substrate 68 is immersed in a polar solvent etching solution such as an aqueous solution of iodine / ammonium iodide, Only the site without alkanethiol is etched (see FIG. 7 (a)).

As compared with the conventional photolithography / etching method, each time compared with the step of obtaining a pattern film by resist coating, exposure, development, etching, and resist stripping, once using the above method, A large amount of film can be processed only by producing a plate, which is suitable for reducing the manufacturing cost.

After the first electrode pattern 53 is formed on the substrate 51 in this way, the gate insulating film 57 is processed. As the material of the gate insulating film 57, a material having a high relative dielectric constant is preferable in order to enhance Cox represented by the formula (1). In addition, organic materials are particularly suitable because they are excellent in various processability. A so-called positive photoresist in which a naphthoquinonediazide UV photosensitive group is introduced into a novolak resin is preferable because it has a relatively high relative dielectric constant among organic substances.

A photoresist is coated on the above-mentioned substrate 51 and prebaked, and then exposed by a high pressure mercury lamp.
After development and post-baking, a structure 70 including the gate insulating film 57 is formed as shown in FIG. 7B. UV curing may be performed in order to prevent alteration of the resist film in a later step.

As shown in FIG. 7C, the semiconductor material 54 formed on the first electrode pattern 53 is preferably a π-electron conjugated aromatic compound, a chain compound, an organic pigment or the like. Specifically, examples of the semiconductor material 54 include pentacene, tetracene, thiophene oligomer derivative, phenylene derivative, phthalocyanine compound, polyacetylene derivative, polythiophene derivative, cyanine dye and the like.

For the semiconductor material 54, a low molecular weight material is formed into a film by a vacuum vapor deposition method, and a high molecular weight material is dissolved in a solvent such as xylene or chloroform to obtain a coating solution, which is subjected to a printing method, an ink jet drawing method or the like. Then, a film is formed at a desired location.

In FIG. 7C, a is an active layer region, b is a gate electrode region, and the semiconductor material 54 is selectively formed in the active layer region a. The semiconductor material 54 can be formed by arranging a metal mask by a vacuum vapor deposition method to shield the gate electrode region B part. The metal mask is suitable because it can process a pattern with an opening of about 30 μm. Similar resolution is obtained in drawing by the inkjet method. Furthermore, 10μ for gravure printing, etc.
A pattern of about m can be formed.

When the vacuum film formation method is used, an inorganic semiconductor material made of a metal oxide such as zinc oxide or tin oxide or a composite oxide such as strontium titanate can be formed. As shown in FIG. 7C, the gate electrode 56 is arranged in the gate electrode region B. As the material of the gate electrode 56, a conductive polymer material such as polyaniline or polydioxythiophene that can be formed by a printing method or an inkjet method is selected in addition to a metal material that can be vacuum-deposited.

As shown in FIG. 7D, a vertical field effect transistor element is formed by forming an electrode film on the semiconductor material 54 as a second electrode film 55 by the same method. Further, it is also preferable to form a conductive material matching the work function of the semiconductor material 54 as a buffer film between the first electrode film 53 and the semiconductor film 54 as a buffer film for facilitating charge transfer. . In addition to a conductive polymer material that can be formed by a printing method or an inkjet method, polyaniline, polydioxythiophene, or the like, a charge transfer material that is well known as an organic EL material is used as an intermediate between the first electrode film 53 and the semiconductor film 54. Alternatively, the buffer film may be formed by a vacuum deposition method.

Although the vertical transistor is manufactured in this manner, the load resistance portion 37 and the input voltage V which form the inverter are formed.
_The electrode parts (input part 38, output part 39) for inputting / outputting _in and the output voltage V _out may be respectively formed in other parts as described above at the time of forming the gate electrode described in FIG. 7D. .

Next, an embodiment of the present invention will be described. In this example, a vacuum deposition method was used on a glass substrate to deposit Cr in the adhesion film to 30 nm (nanometer) and Au to 70 nm.
A film was formed to form a first electrode film. Microcontact printing transfer of decanethiol was performed on the first electrode film to etch Au with an aqueous solution of iodine and ammonium iodide, and then a chromium film was etched with an aqueous nitric acid solution containing cerium ammonium nitrate.
A T-type electrode 41 as shown in FIG. 1 (b) was formed.

Next, a photoresist (OFPR800) manufactured by Tokyo Ohka Kogyo Co., Ltd. was spin-coated on the glass substrate to a thickness of 1 μm, and a regular hexagonal shape was exposed and developed, and post-baking and UV curing were performed to perform gate insulation. A film was formed. This gate insulating film can be processed to a finer dimension than lithography processing by isotropically etching a resist pattern having a thickness of 1 μm to a thickness of 0.5 μm by ashing treatment with oxygen plasma. Here, the channel width as the transistor operating portion was set to 20 μm.

Next, with respect to this element, P manufactured by Bayer
EDOT Conductive polymer solution is used for the first drain electrode
After being formed on the electrode film of 1. by an inkjet method, a commercially available polyhexylthiophene as a p-type semiconductor material was purified and dissolved in chloroform to form a semiconductor layer by an inkjet method. The organic semiconductor concentration should be 0.5 wt% or less,
As a result, it became possible to form a semiconductor layer of about 100 nm or less.

Subsequently, a source electrode layer is formed on the semiconductor layer by an ink jet method, and a gate electrode is formed on the side wall of the gate insulating film by an ink jet method. As shown in FIG. 9, a regular hexagonal column-shaped vertical field effect transistor is formed. Element 71 was produced. Further, on the glass substrate, adjacent to the vertical field effect transistor element 71, a regular hexagonal prism shaped load resistance layer portion 7 is provided.
2. A vertical field effect transistor element 71, a load resistance layer portion 72, and an input portion 73 are formed by forming an input portion 73 made of a regular hexagonal columnar conductive member and an output portion 74 made of a regular hexagonal columnar conductive member in parallel. , The output unit 74 is T on the glass substrate.
It was connected by a mold electrode. Vertical field effect transistor 7
1, a load resistance layer portion 72 is electrically connected, and the drain electrode of the vertical field effect transistor 71 is grounded via a lead wire. The source electrode of the vertical field effect transistor element 71 is connected to the load resistance layer portion 72 and the output portion 74 by the T-shaped electrode on the glass substrate. An input signal is applied to the gate electrode of the vertical field effect transistor 71 through the T-shaped electrode on the glass substrate, the input portion 73, and the lead wire, and the load resistance layer portion 72 is opposite to the end portion connected to the source electrode. The voltage of the power supply V _DD is applied to the upper end portion on the side through the lead wire, and the output portion 74 outputs the output signal from the upper end portion on the side opposite to the end portion connected to the source electrode through the lead wire.

In another embodiment of the present invention, in the above embodiment, as shown in FIG. 10, the vertical field effect transistor element 75 is a regular triangular prism having a side of 20 μm, and the load resistance layer portion is a regular triangular prism having a side of 20 μm. 76, an input part 77 made of a regular triangular pole-shaped conductive member having a side of 20 μm, and a side of 20 μm
An output unit 78 made of a regular triangular prism-shaped conductive member of m is formed in parallel on an insulating substrate to form an inverter. The occupied area of this embodiment is 40 μm × 60 μm. This is an area occupied by the lateral transistor of 330 μm ×
330 μm (switching transistor 200 μm x 2
00 μm, load resistance part 30 μm × 30 μm, wiring part 1
The size was reduced to about 1/35 of (00 μm × 100 μm).

[0054]

As described above, according to the present invention, by using the vertical field effect transistor, it is possible to reduce the size of the element, and since each electrode is a polygonal column, it is integrated. It is also suitable for electrical connection because the electrode leads are connected only on the upper surface.

[Brief description of drawings]

FIG. 1 is a perspective view showing an example of the present invention and a part thereof.

FIG. 2 is a perspective view showing an active layer portion of the same example, and a plan view showing the respective portions of the same example arranged vertically.

FIG. 3 is a cross-sectional view showing a vertical field effect transistor element structure according to an embodiment of the present invention.

FIG. 4 is a diagram showing an example of classification of vertical field effect transistors.

FIG. 5 is a diagram showing another example of classification of vertical field effect transistors.

FIG. 6 is a diagram showing connections for applying a gate voltage and a source-drain voltage when operating the field effect transistor in the above embodiment.

FIG. 7 is a diagram for explaining an example of the method for manufacturing the field effect transistor of the above embodiment.

FIG. 8 is a diagram for explaining a microcontact printing method.

FIG. 9 is a top view showing an embodiment of the present invention.

FIG. 10 is a top view showing another embodiment of the present invention.

FIG. 11 is a cross-sectional view showing a conventional lateral field effect transistor.

FIG. 12 is a cross-sectional view showing another conventional lateral field effect transistor.

FIG. 13 is a circuit diagram showing an example of an inverter circuit.

FIG. 14 is a diagram for explaining the operation of the inverter circuit.

FIG. 15 is a plan view showing an inverter using a conventional lateral field effect transistor.

[Explanation of symbols]

31 drain electrode 32 semiconductor layer 33 source electrode 34 Active layer 35 Gate 36 Vertical field effect transistor 37 Load resistance layer 38 Input section 39 Output section 40 Insulating substrate 41 electrodes

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 29/78 H01L 29/78 658F 653 29/28 51/00 27/06 102A 29/78 613Z F term ( Reference) 5F048 AA01 AB04 AC10 BA16 BD00 BD07 5F110 AA04 BB03 BB05 CC09 DD01 DD02 EE01 EE02 EE42 EE43 EE43 FF01 FF36 GG01 GG05 GG42 HK02 HK04 HK21 HK32 HL02 HL04 HL11 HL22 NN71 QQ02

Claims (7)

[Claims] 1. A source electrode layer, a semiconductor layer, and a drain electrode in an inverter having a switching element and a load element electrically connected to the switching element, the vertical field effect transistor being used as the switching element. An inverter characterized in that layers are sequentially stacked, and a gate insulating layer and a gate electrode layer are sequentially provided so as to stand in a vertical direction so as to be in contact with one sidewall of these layers. 2. The inverter according to claim 1, wherein the load element is electrically connected to the vertical field effect transistor as a load resistance element. 3. The inverter according to claim 1, wherein the vertical field effect transistor is a vertical field effect transistor in which the semiconductor layer is made of an organic semiconductor material. 4. The inverter according to claim 2, wherein the load element is made of an organic compound having electric conductivity. 5. The inverter according to claim 2, wherein the load element has a sandwich structure of a lower electrode film, a resistance film and an upper electrode film. 6. The inverter according to claim 1, wherein:
An inverter formed on an insulating substrate. 7. The inverter according to claim 1, wherein:
An inverter characterized in that a source electrode, a drain electrode, a gate electrode, a load resistance element, and an electrode film of a wiring electrode for electrically connecting a switching element and a load resistance element is made of a conductive material group including an organic substance. .