JPH0964204A - Nonvolatile semiconductor memory and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory having a source region which is formed intentionally away from an isolated impurity region to improve the dielectric strength of the source region whereby the endurance characteristic is prevented from deteriorating to provide a high reliability. SOLUTION: A nonvolatile semiconductor memory comprises a p-type well region 1, isolated impurity region 6, isolation insulation films 5, source regions 57 and control gate electrodes 55. The region 6 is of p-type and distributed from a major surface of the region 1 to a specified depth. The films 5 are formed mutually separated with spacings on the region 6 laid on the region 1. The source regions 57 are of n-type and formed in the well region 1 between the films 5 above the region 6. The electrodes 55 are formed on the film 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a nonvolatile semiconductor memory device capable of electrically writing and erasing, and a method of manufacturing the same, and more particularly to a structure of a flash memory and a method of manufacturing the same. Is.

[0002]

2. Description of the Related Art A flash memory is known as a memory device capable of freely writing data and electrically erasing written information charges.

FIG. 32 is a block diagram showing a general structure of a flash memory. In the figure, the flash memory is a memory cell matrix 100 arranged in a matrix.
An X address decoder 200, a Y gate 300,
Y address decoder 400 and address buffer 500
A write circuit 600, a sense amplifier 700, an input / output buffer 800, and a control logic 900.

The memory cell matrix 100 has a plurality of memory transistors arranged in a matrix therein. An X address decoder 200 and a Y gate 3 for selecting rows and columns of the memory cell matrix 100.
00 is connected. The Y-gate 300 is connected to a Y-address decoder 400 which gives column selection information. An address buffer 500 for temporarily storing address information is connected to each of the X address decoder 200 and the Y address decoder 400. Y gate 30
A write circuit 600 for performing a write operation at the time of data input and a sense amplifier 700 for determining “0” or “1” from the value of a current flowing at the time of data output are connected to 0. Each of the write circuit 600 and the sense amplifier 700 has an input / output buffer 800 for temporarily storing input / output data.
Is connected. A control logic 900 for controlling the operation of the flash memory is connected to the address buffer 500 and the input / output buffer 800. The control logic 900 performs control based on the chip enable signal, the output enable signal and the program signal.

FIG. 33 is an equivalent circuit diagram showing a schematic structure of the memory cell matrix 100 shown in FIG. In FIG. 33, a plurality of word lines W extending in the row direction
_{L 1, WL 2, ...,} WL i and, a plurality of the bit lines BL ₁ extending in the column direction, BL _2, ..., are arranged such that the BL _j are orthogonal to each other to constitute a matrix. Memory transistors Q ₁₁ , Q ₁₂ , ..., Q each having a floating gate are provided at the intersections of the word lines and the bit lines.
_ij is located. The drain of each memory transistor is connected to each bit line. The sources of the memory transistors are connected to the respective source lines S ₁ , S ₂ , ...
The sources of the memory transistors belonging to the same row are connected to each other as shown in the figure.

FIG. 34 is a partial cross-sectional view showing the cross-sectional structure of one memory transistor constituting the above flash memory. The transistor of the flash memory shown in FIG. 34 is called a stacked gate type.

FIG. 35 is a schematic sectional view showing a planar arrangement of a conventional stacked gate type flash memory. 36 is a partial cross-sectional view taken along line XXXVI-XXXVI of FIG. The structure of the conventional flash memory will be described with reference to these drawings.

Referring to FIG. 36, p type well region 113 is formed.
A p-type isolation impurity region 156 is formed therein. An n-type impurity region, for example, n ⁺ drain region 184 and n ⁺ source region 185, is formed at a main surface of p-type well region 113 of the silicon substrate with a space therebetween. In the region sandwiched between the n ⁺ drain region 184 and the n ⁺ source region 185, the control gate 186 and the floating gate 1 are formed so that a channel region is formed.
87 is formed. The floating gate 187 is formed on the p-type well region 113 with a thin gate oxide film 190 having a film thickness of about 100 Å interposed. The control gate 186 is electrically isolated from the floating gate 187 so that the floating gate 187 is
Is formed on the above with an interlayer insulating film 188 interposed. The floating gate 187 is formed of a polycrystalline silicon layer. The control gate 186 is formed of a polycrystalline silicon layer or a laminated film of a polycrystalline silicon layer and a refractory metal. The insulating film 189 is formed on the silicon substrate and the floating gate 187 and the control gate 186.
It is formed by depositing it by the CVD method (chemical vapor deposition method) on the polycrystalline silicon layer constituting the. Further, the smooth coat film 19 is formed so as to cover the floating gate 187 and the control gate 186.
5 are formed.

As shown in FIG. 35, control gates 186 are formed as word lines connected to each other and extending in the horizontal direction (row direction). Bit line 191 is arranged orthogonal to word line 186 and connects n ⁺ drain regions 184 arranged in the vertical direction (column direction) to each other. Bit line 191 is electrically connected to each n ⁺ drain region 184 through drain contact 196. FIG.
As shown in FIG. 6, the bit line 191 has a smooth coat film 1
It is formed on 95. As shown in FIG. 35, n ⁺
The source region 185 extends along the direction in which the word line 186 extends, and the word line 186 and the field oxide film 192 are formed.
It is formed in the area surrounded by. Each n ⁺ drain region 184 also includes the word line 186 and the field oxide film 19.
It is formed in a region surrounded by 2 and.

The operation of the flash memory configured as described above will be described with reference to FIG.

First, in the write operation, n⁺drain
The voltage V of about 6 to 8 V is applied to the region 184. _D, Control
The voltage V of about 10 to 15V is applied to the gate 186._GIs applied
You. Furthermore, n⁺Source region 185 and p-type well region 1
13 is kept at ground potential. At this time, the memory transition
A current of several hundred μA flows through the channel of the star. Source
Of the electrons that flowed to the drain from the
The electrons that have high energy in this vicinity are,
It will be a loose channel hot electron. This electron
Voltage V applied to control gate 186_Gby
Floating by electric field, as shown by the arrow
It is injected into the gate 187. In this way, the float
Electrons are accumulated in the swing gate 187, and
Transistor threshold voltage V_thWill be higher. This threshold
Value voltage V_thIs written higher than the specified value
The state is called "0".

Next, in the erase operation, a voltage V _{S of} about 10 to 12 V is applied to the n ⁺ source region 185, and the control gate 186 and the p-type well region 113 are held at the ground potential. Further, the n ⁺ drain region 184 is opened. The voltage V applied to the n ⁺ source region 185
Due to the electric field due to _S , the electrons in the floating gate 187 become thin gate oxide film 1 as shown by the arrow.
Pass 90 by tunneling. In this way, the electrons are extracted into the floating gate 187, so that the threshold voltage V _{th of the} memory transistor is increased.
Becomes lower. A state in which the threshold voltage V _th is lower than a predetermined value is called an erased state, “1”. Since the sources of the memory transistors are connected as shown in FIG. 33, all the memory cells can be collectively erased by this erase operation.

Further, in the read operation, a voltage V _G ′ of about 5 V is applied to the control gate 186 and a voltage V _D ′ of about 1 to 2 V is applied to the n ⁺ drain region 184. At this time, the determination of "1" or "0" is made depending on whether or not a current flows in the channel region of the memory transistor, that is, whether the memory transistor is in the on state or the off state.

FIG. 37 is a block diagram of XXXVII-XXX of FIG.
It is a fragmentary sectional view which follows the VII line. Referring to FIG. 37,
A p-type isolation impurity region 156 is formed in the p-type well region 113 of the silicon substrate. On the p-type isolation impurity region 156, an n-type impurity region, that is, n ⁺
Source regions 185 are formed at intervals. A film thickness of 6000 to 700 is formed on the main surface of the p-type silicon substrate 113.
A 0Å isolation insulating film 105 is formed. The isolation insulating film 105 is formed between the source regions 185. A control gate 186 is formed on the isolation insulating film 105 with an interlayer insulating film 188 interposed. The control gate 186 is formed of a polycrystalline silicon layer or a laminated film of a polycrystalline silicon layer and a refractory metal. The insulating film 189 is formed by depositing by CVD on the surfaces of the silicon substrate and the polycrystalline silicon layer forming the control gate 186. Source area 1
A conductive layer 165 made of polysilicon electrically connected to the source region 185 or a composite film in which a refractory metal is laminated on the polysilicon is provided on the layer 85.
Further, a smooth coat film 195 is formed so as to cover the floating gate 187, the control gate 186 and the conductive layer 165. Smooth coat film 19
5 is an oxide film 195c, a nitride film 195b, an interlayer insulating layer 19
5a has a three-layer structure.

Next, referring to FIGS. 38 to 40, FIG.
The manufacturing process along the cross section shown in FIG.

First, referring to FIG. 38, p-type well region 113 is formed on the upper surface of a p-type silicon substrate. And
The isolation insulating film 105 is formed for each column. Boron is implanted into only the p-type well region 113 at an energy (about 250 KeV) having a range approximately equal to the thickness of the oxide film of the isolation insulating film 105 to form the isolation impurity region 156.

Next, after forming the floating gate, referring to FIG. 39, a control gate 186 having a predetermined shape is formed on interlayer insulating film 188.

Referring to FIG. 40, control gate 1
After forming the insulating film 189 on the film 86, the isolation insulating film 105 is formed.
And patterned on the insulating film 189 at a predetermined pitch.
A resist film 173 is formed. The resist film 173 and
Dry etching using the control gate 186 as a mask
Insulation film with a thickness of 6000-7000Å
105 is removed to expose the isolation impurity region 156.
Next, the resist film 173 and the control gate 186 are formed.
Arsenic (As) 35 KeV in a self-aligned manner as a mask,
5 × 10^Fifteen/ Cm²Ion implantation is performed under the conditions of. Soshi
Immediately after implanting arsenic, phosphorus is further added to the substrate.
50 KeV, 5 × 10 vertically¹⁴/ Cm ²Under the conditions of
Ion implantation and concentration of 1 × 10 in subsequent heat treatment^{twenty one}/ Cm^Three,
Source consisting of n-type impurity region with seed resistance of 50Ω / □
A region 185 is formed.

After that, the resist film 173 is removed, and an insulating film 189 is formed so as to cover the control gate 186 and the isolation insulating film 105. Next, the source region 18
5, a conductive layer 165 is formed along the sidewall of the insulating film 189. The conductive layer 165 is formed of polysilicon to which an n-type impurity such as phosphorus is added, or a composite film in which a refractory metal layer is laminated on polysilicon to which an n-type impurity is added. Finally, the smooth coat film 19 is formed on the insulating film 189 so as to cover the conductive layer 165.
5 is formed. Through the above steps, the cross section shown in FIG. 37 is formed.

[0020]

A problem that occurs in the step of forming the region shown in FIG. 37 will be described.

First, in the step shown in FIG.
In order to remove the isolation insulating film 105 having a thickness of 000 to 7,000 Å, etching for a long time is required. At this time, there is a problem that the control gate 186 used as a mask is easily damaged by etching for a long time.

Further, the isolation impurity region 156 located under the isolation insulating film 105 is also etched by the etching for a long time. Therefore, the isolation impurity region 156
Was susceptible to damage and had reliability problems.

Further, the source region is the isolation impurity region 1
It is formed by implanting ions into 56. Therefore, the isolation impurity region and the source region overlap with each other. Therefore, since the conductive layers that are opposite to each other overlap,
There is a problem that the breakdown voltage of the source region is lowered. If the withstand voltage of the source region is lowered, the endurance characteristic is deteriorated.

FIG. 41 is a sectional structural view for explaining the deterioration of the endurance characteristic which occurs when erasing data. Referring to FIG. 41, in the conventional flash memory,
In the erase operation, a voltage of 0 V is applied to the control gate 186 and a voltage of about 10 to 12 V is applied to the source region 185.
At this time, in the vicinity of the source region 185, band-to-band tunneling occurs due to the high electric field, and holes are generated. The generated holes are trapped in the oxide film 190 located on the floating gate electrode 187, and the film quality of the oxide film 190 deteriorates. When the quality of the oxide film 190 deteriorates in this way, there is a problem that it becomes difficult to extract electrons from the floating gate 187 at the time of erasing data. Such a phenomenon is called "endurance characteristic deterioration". For example, IEEE ELE
CTRON DEVICE LETTERS, VOL.10, No.3, March 1989, PP1
17-119.

Therefore, an object of the present invention is to provide a highly reliable nonvolatile semiconductor memory device in which the source region and the isolation impurity region are separated from each other, the withstand voltage of the source region is improved, the endurance characteristic is prevented from being deteriorated. is there.

Another object of the present invention is to provide a method for manufacturing a nonvolatile semiconductor memory device in which the control gate is not damaged.

Another object of the present invention is to provide a method for manufacturing a non-volatile semiconductor memory device in which an isolation impurity region is not damaged.

Another object of the present invention is to provide a method for manufacturing a non-volatile semiconductor memory device which can easily improve the breakdown voltage of the source region of the non-volatile semiconductor memory device.

[0029]

A nonvolatile semiconductor memory device of the present invention includes a semiconductor substrate, an isolation impurity region, an isolation insulating film, a source region, and a control gate electrode. The semiconductor substrate is of the first conductivity type and has a main surface. The isolation impurity region is of the first conductivity type and is formed so as to be distributed at a predetermined depth from the main surface of the semiconductor substrate. A plurality of isolation insulating films are formed on the isolation impurity region on the semiconductor substrate at a distance from each other. The source region is of the second conductivity type and is formed on the isolation impurity region in the semiconductor substrate between the isolation insulating films and apart from the isolation impurity region. The control gate electrode is
It is formed on the isolation insulating film.

The source region may be formed separately from the isolation insulating film. A nonvolatile semiconductor memory device according to another aspect of the present invention includes a semiconductor substrate,
The charge storage electrode, the element isolation insulating film, the isolation impurity region, the word line, the drain region, and the source region are provided. The semiconductor substrate is of the first conductivity type and has a main surface. (M × n) charge storage electrodes are m rows and n
They are arranged in a matrix of columns, and are formed on the main surface of the semiconductor substrate with a first insulating film interposed. The element isolation insulating film extends over two rows of the charge storage electrodes, and a plurality of element isolation insulating films are formed on each column of the semiconductor substrate. The isolation impurity region is of the first conductivity type and is distributed under the element isolation insulating film to a predetermined depth from the main surface of the semiconductor substrate. M word lines are formed on the element isolation insulating film for each row by interposing a second insulating film on the charge storage electrodes.
The drain region is of the second conductivity type, is surrounded by the element isolation insulating film and the word line, and is formed on the main surface of the semiconductor substrate. The source region is of the second conductivity type and is formed on the isolation impurity region in the semiconductor substrate between the element isolation insulating films and apart from the isolation impurity region.

In the nonvolatile semiconductor memory device having the above structure, the first conductivity type isolation impurity region and the second conductivity type isolation impurity region are formed.
The conductive source regions do not overlap. As a result, the breakdown voltage of the source region is improved and the deterioration of the endurance characteristic can be prevented.

Further, in the method for manufacturing a nonvolatile semiconductor memory device of the present invention, a step of forming an insulating film, a step of forming an isolation impurity region, a step of forming a control gate electrode, and a source region are formed. And a process. In the step of forming the insulating film, the first insulating film including a first insulating film portion having a first thickness and a second insulating film portion having a second thickness larger than the first thickness is formed. It is formed on the main surface of a conductive type semiconductor substrate. In the step of forming the isolation impurity region, a region of the semiconductor substrate that is separated from the first insulating film portion under the first insulating film portion by implanting impurity ions of the first conductivity type into the semiconductor substrate through the insulating film. Then, an isolation impurity region is formed in the region of the semiconductor substrate below the insulating film so as to extend continuously to the region of the semiconductor substrate below the second insulating film portion and close to the second insulating film portion. In the step of forming the isolation insulating film,
By removing the first insulating film portion, a plurality of isolation insulating films spaced apart from each other are formed on the isolation impurity region. In the step of forming the control gate electrode, the control gate electrode is formed on the isolation insulating film. In the step of forming the source region, impurity ions of the second conductivity type are implanted into the isolation impurity region in the semiconductor substrate between the isolation impurity regions to form the source region separately from the isolation impurity region.

In the step of forming the source region, the source region may be formed separately from the isolation impurity region.

In the method of manufacturing a non-volatile semiconductor memory device including the above steps, the isolation insulating film is formed by removing the first insulating film portion having the first thickness smaller than the second thickness. To do. Therefore, it is not necessary to perform etching for a long time and the quality of the control gate used as a mask is not deteriorated. Further, since the etching is not performed for a long time, the isolation impurity region is not etched. As a result, the reliability of the isolation impurity region is not deteriorated. Further, the first conductivity type isolation impurity region is formed apart from the second conductivity type source region. Therefore, it is possible to prevent the breakdown voltage of the source region from decreasing and prevent the deterioration of the endurance characteristic.

[0035]

A non-volatile semiconductor memory device according to the present invention and a method of manufacturing the same will be described below with reference to the drawings.

FIG. 1 shows a flash according to an embodiment of the present invention.
It is a schematic plan view which shows the planar arrangement of a memory. Figure 1
For reference, the control gates 55 are connected to each other.
Formed as word lines so as to extend in the horizontal direction (row direction)
Have been. Bit line 62 should be orthogonal to word line 55
N arranged in the vertical direction (column direction)⁺Drain region
56 are connected to each other. Bit line 62 is a drain contact
Each n through Kuto 60 ⁺Electrically connected to the drain region 56
Continue. n⁺Source region 57 is one in which word line 55 extends
The word line 55 and the isolation insulating film 5
It is formed in the area surrounded by. Each n⁺Drain territory
The region 56 is also surrounded by the word line 55 and the isolation insulating film 5.
Are formed in the area.

FIG. 2 shows a cross section taken along line II-II of this flash memory. Referring to FIG. 2, a p-type isolation impurity region 6 is formed in a p-type well region 1 of a silicon substrate. Isolation insulating films 5 are formed on the main surface of p type well region 1 of the silicon substrate at a distance from each other. On the main surface of p-type well region 1 between isolation insulating films 5, n-type source regions 57 are formed on isolation impurity region 6 at a distance from isolation impurity region 6. A control gate 55 is formed on the isolation insulating film 5 with a second insulating film 54 interposed. The third layer is formed so as to cover the control gate 55 and the isolation insulating film 5.
Insulating film 58 is formed. An oxide film 81 is formed so as to cover the third insulating film 58 and the first conductive layer 59. A nitride film 82 is formed on the oxide film 81. An interlayer insulating film 61 is formed on the nitride film 82.

FIG. 3 is a partial sectional view taken along the line III-III in FIG. Referring to FIG. 3, p-type isolation impurity region 6 is formed in p-type well region 1. Also, p
An n-type drain region 56 is formed on the p-type isolation impurity region 6 at a predetermined depth from the main surface of the type well region 1 and apart from it. An n-type source region 57 is formed on the p-type isolation impurity region 6 at a predetermined depth from the main surface of the p-type well region 1 at a predetermined distance from the drain region 56, and at a distance from the n-type source region 57. There is. Floating gate 52 is formed on the main surface of p type well region 1 with first insulating film 51 interposed. A control gate 55 is formed on the floating gate 52 with a second insulating film 54 of three layers interposed. Further, a third insulating film 58 is formed so as to cover the floating gate 52 and the control gate 55.

On the drain region 56, a polysilicon film or a composite film in which a refractory metal is laminated on the polysilicon, which is electrically connected to the drain region 56 along the side wall of the third insulating film 58, is formed. The first conductive layer 59 is formed. A second conductive layer 60 made of a refractory metal such as tungsten (W) is electrically connected to the first conductive layer 59 so as to extend further upward. The second conductive layer 60 is connected to the bit line 62.

Next, the manufacturing process of this embodiment will be described with reference to FIGS. 4 to 1
0, FIGS. 13 to 20 are regions (hereinafter referred to as element isolation regions) along the cross section of FIG. 2, and FIGS. 21 to 31 are regions (hereinafter referred to as active regions) along the cross section of FIG. It shows a process. 11 and 12 are diagrams showing both the element isolation region and the active region.

First, referring to FIG. 4, p-type well region 1
Oxide film 2 with a thickness of 100-200Å on the main surface of
Is deposited at.

Referring to FIG. 5, on the silicon oxide film 2,
A silicon nitride film 3 is deposited with a thickness of 1000 to 1500 Å. A resist 4 is applied on the silicon nitride film 3, and the resist 4 is patterned into a predetermined shape.

Referring to FIG. 6, silicon nitride film 3 is removed using resist 4 as a mask. Top views of the shape of the resist 4 are shown in FIGS. The shape of the resist 4 may be any of those shown in FIGS. The resist 4 is mainly deposited on the source region.

Referring to FIG. 8, 1 by wet oxidation method
The silicon oxide film 2 is grown under the conditions of 100 ° C. for 1 hour and 20 minutes to form the isolation insulating film 5. At this time, the maximum thickness of the isolation insulating film 5 is about 7,000Å and the minimum thickness is about 300Å.
Is preferred.

Referring to FIG. 9, p-type well region 1 is used for the purpose of channel-cutting boron with energy (250 KeV) having a range approximately equal to the maximum film thickness of isolation insulating film 5.
To form an isolation impurity region 6.

At the same time, referring to FIG. 21, isolation impurity region 6 is also formed in the active region. Next, a first insulating film 51 made of an oxide film having a thickness of about 100Å is formed on the active region.
To form Here, the first insulating film 51 has a thickness of 1
An oxide film having a thickness of about 00Å may be subjected to nitriding treatment, or may be subjected to nitriding treatment and further subjected to oxidization treatment. Next, a polysilicon layer (floating gate layer) 99 having a film thickness of about 1000 Å is deposited on the upper surfaces of the isolation insulating film 5 in the element isolation region and the first insulating film 51 on the active region. A resist film 70 patterned at a predetermined pitch is formed on the upper surface of the polysilicon layer 99.
To form Then, anisotropic etching is performed using the resist film 70 as a mask to pattern the polysilicon layer 99 to have a predetermined pitch.

As a result, the plane arrangement shown in FIG. 11 is completed. FIG. 12 is a view showing a cross section taken along line XII-XII in FIG. 9 and 21 are IX of FIG.
It is a figure which shows the cross section along each line of -IX line and XXI-XXI line. Also, FIGS. 9 and 21 show IX of FIG.
It is a figure which shows the cross section along the -IX line and the XXI-XXI line. It should be noted that, instead of the polysilicon layer 52, phosphorus is deposited on the amorphous silicon layer or on the polysilicon or amorphous silicon layer to which no impurity is added, and polysilicon or amorphous silicon exhibiting a low resistance effect is obtained by high-temperature diffusion. May be used. Alternatively, so-called doped polysilicon may be used in which impurities are already added at the time of deposition by flowing a gas containing impurities such as phosphorus and arsenic at the time of depositing using the CVD method.

Next, referring to FIGS. 10 and 22, the register
Film 70 is removed, and a second insulating film is formed on the entire surface of the silicon substrate.
The film 54 is formed. This second insulating film 54 is a product of three layers.
It is a layered film and has an oxide film 54a with a film thickness of about 100Å
And a film thickness of 100Å formed on it by the CVD method
On the nitride film 53b, and further on the nitride film 54b.
The formed oxide film 54c having a film thickness of about 100Å
Be composed. The second insulating film 54 is a peripheral circuit (not shown).
Of the oxide film 54c and the nitride film 54b on the upper surface.
Remove the specified part. Then, the MO that constitutes the peripheral circuit
V of S transistor _thInject boron for control
U. After that, the oxide film 54a in the peripheral circuit region is removed.
The above-mentioned process is carried out by using two or more types of MO existing in the peripheral circuit.
This is repeated when forming the S transistor. Injection
As ions to be used, arsenic may be used together with boron.
After that, the gate oxide film of the peripheral MOS transistor (illustration
Only the required type of film thickness (for example, 300Å
Forming a gate electrode and a 150Å gate oxide film)
I do.

Next, the second polysilicon having a film thickness of about 2000Å to 3000Å is formed on the second insulating film 54 and on the gate oxide film (not shown) of the MOS transistor of the peripheral circuit in the same step. Form layer 62. A third insulating film 58 is formed on the second polysilicon layer 62. The second polysilicon layer 62 may be formed of polysilicon doped with an n-type impurity such as phosphorus, or a composite film in which a refractory metal layer is laminated on polysilicon doped with an n-type impurity. . After that, the MOS that constitutes the peripheral circuit
A patterned resist (not shown) is formed in a region where a gate electrode of the transistor is formed. Anisotropic etching is performed using this resist as a mask to sequentially pattern the third insulating film 58 and the second polysilicon layer 55. As a result, the gate electrode (not shown) of the peripheral MOS transistor is formed. Next, impurities are implanted in a self-aligned manner using the resist and the gate electrode, which are opened only in the necessary portions for forming the low concentration region of the LDD structure of the MOS transistor of the peripheral circuit, as a mask. If there are two types of MOS transistors in the peripheral circuit area, the above steps are repeated.

After that, in the memory cell, a patterned resist 71 for forming a control gate and a floating gate is formed. In this way, the structure shown in FIG. 10 or FIG. 22 is formed. In the state of FIG. 22, the peripheral circuit region is entirely covered with the resist film 71.

Referring to FIGS. 13 and 23, resist film 7
1 is used as a mask to perform anisotropic etching, thereby removing the third insulating film 58, the second polysilicon layer 55 and the second insulating film 58.
The insulating film 54, the first polysilicon layer 52, and the first insulating film 51 are sequentially etched. As a result, the control gate 55 shown in FIGS. 13 and 23 and the floating gate 52 shown in FIG. 23 are formed. After this, isotropic etching may be performed to slightly etch the side surface portion of the floating gate 52. After that, the resist film 71 is removed.

Referring to FIG. 23, a resist film 72 is formed on the substrate which will be the source region. Arsenic (As) is self-aligned with 35 KeV using the resist film 72, the control gate 55 and the floating gate 52 as a mask,
Ions are implanted perpendicularly to the substrate under the condition of 5 × 10 ¹⁴ / cm ² . Immediately after the implantation of arsenic, boron is completely perpendicular to the substrate or at an angle of 40 ° or less from the vertical line of 50 KeV, 3 × 10 ¹³ / cm ^2.
The ion implantation is performed under the following conditions. Then, by a subsequent heat treatment, a drain region 56 formed of an n-type impurity region having a concentration of 5 × 10 ¹⁹ / cm ³ and a seed resistance of 80Ω / □ is formed.
Immediately after injecting boron, BF ₂ is added to about 30 Ke.
Ions may be implanted under the condition of V, 1 × 10 ¹³ / cm ² . After that, the resist film 72 is removed.

Referring to FIG. 14, the drain region and the peripheral circuit region are covered with a resist film 73, and the isolation insulating film 5 in the source region is anisotropically etched in a self-aligned manner. Here, if the isolation insulating film 5 is particularly thin, the etching may not be performed. Further, an insulating film of several hundred liters may be formed as a protective film so that the side wall of the control gate is not damaged when the isolation insulating film 5 is etched.

With reference to FIGS. 15 and 24, the drain region
Is covered with a resist film 73. Resist film 73,
Arsenic in a self-aligned manner using the troll gate 55 as a mask
(As) 35 KeV, 5 × 10^Fifteen/ Cm²Under the conditions of
Ions are implanted. Immediately after implanting arsenic,
Phosphorus is completely vertical to the substrate, 50 KeV, 5 × 10
¹⁴/ Cm²Ion implantation under the conditions of
1 × 10^{twenty one}/ Cm^Three, Seed resistance 50Ω / □ n-type impurity
A source region 57 composed of an object region is formed. After this,
The distant film 73 is removed. And the temperature condition of 950 ° C
Dry the substrate surface for about 10 minutes while supplying oxygen underneath.
Oxidize.

Next, referring to FIGS. 16 and 25, an oxide film 63 is formed on the entire surface of the substrate. Then, the oxide film 63 is etched by anisotropic etching. As a result, the third insulating film 58 shown in FIGS. 17 and 26 is completed.

Next, referring to FIGS. 18 and 27, polysilicon 64 is deposited on the entire surface of the silicon substrate. A resist film 74 patterned into a predetermined shape is formed on the upper surface of the polysilicon 64. Where polysilicon 6
4 uses polysilicon to which an n-type impurity such as phosphorus is added. In this case, it may be formed by a composite film in which a refractory metal layer is laminated on polysilicon added with an n-type impurity instead of polysilicon. Next, the resist film 7
Using the mask 4 as a mask, the polysilicon 64 is etched by anisotropic etching.

Then, as shown in FIGS. 19 and 28, the drain region 56 and the source region 57 are formed at the bottom.
Are electrically connected to each other to form a first conductive layer 59 along the side surface of the third insulating film 58. The first conductive layer 59 may be connected only to the drain region 56.

Next, referring to FIGS. 2 and 29, oxide film 8 is formed.
1 is formed with a thickness of about 1500Å. Then, a nitride film 82 is formed on the oxide film 81 with a thickness of about 500 Å.
An interlayer insulating film 61 made of a BPSG film or the like is formed on the entire surface of the nitride film 82. After performing wet or dry reflow at about 900 ° C. for 30 minutes, etch back is performed. As a result, the interlayer insulating film 61 having the shape shown in FIGS. 2 and 30 is formed.

Then, referring to FIG. 31, a resist film 74 having a hole pattern is formed above drain region 56 on interlayer insulating film 61 on the active region. The contact hole 65 is formed by anisotropically etching using the resist film 74 as a mask.

Finally, inside the contact hole 65,
For example, the second conductive layer 60 made of a refractory metal such as tungsten is formed. Then, a bit line 62 made of aluminum or aluminum containing silicon, copper, or the like.
To form

Through the above steps, the nonvolatile semiconductor memory device according to the present invention is completed. Here, the second conductive layer 60 formed inside the contact hole 65 is CV
It may be used as a bit line by patterning after being formed on the entire surface by the D method. Further, a passivation film may be formed thereabove.

In the step of forming the source region 57 shown in FIG. 15, the source region 57 may be formed separately from the isolation insulating film 5. At this time, the nonvolatile semiconductor memory device of the present invention is as shown in FIG.

The embodiments disclosed this time are to be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[Brief description of drawings]

FIG. 1 is a schematic plan view showing a planar arrangement of a nonvolatile semiconductor memory device of the present invention.

2 is a cross-sectional view taken along line II-II of FIG.
1 is a cross-sectional view showing a first embodiment of a nonvolatile semiconductor memory device of the present invention.

FIG. 3 is a cross-sectional view taken along the line III-III of FIG. 1, showing the first embodiment of the nonvolatile semiconductor memory device of the present invention.

FIG. 4 is a cross-sectional view showing a first step along the cross section of FIG. 2 as a method for manufacturing a nonvolatile semiconductor memory device of the present invention.

FIG. 5 is a cross-sectional view showing a second step along the cross section of FIG. 2 as a method for manufacturing a nonvolatile semiconductor memory device of the present invention.

FIG. 6 is a cross-sectional view showing a third step along the cross section of FIG. 2 as a method for manufacturing a nonvolatile semiconductor memory device of the present invention.

FIG. 7 is a top view corresponding to FIG.

FIG. 8 is a sectional view showing a fourth step along the section of FIG. 2 as a method for manufacturing a nonvolatile semiconductor memory device according to the present invention.

FIG. 9 is a cross-sectional view showing a fifth step along the cross section of FIG. 2 as a method for manufacturing a nonvolatile semiconductor memory device of the present invention.

FIG. 10 is a sectional view showing a sixth step along the section of FIG. 2 as a method for manufacturing a nonvolatile semiconductor memory device according to the present invention.

11 is a top view corresponding to FIG. 9. FIG.

FIG. 12 is a sectional view taken along the line XII-XII in FIG. 11;

FIG. 13 is a cross-sectional view showing a seventh step along the cross section of FIG. 2 as a method for manufacturing a nonvolatile semiconductor memory device of the present invention.

FIG. 14 is a cross-sectional view showing an eighth step along the cross section of FIG. 2 as a method for manufacturing a nonvolatile semiconductor memory device of the present invention.

FIG. 15 is a cross-sectional view showing a ninth step along the cross section of FIG. 2 as a method for manufacturing a nonvolatile semiconductor memory device of the present invention.

16 is a cross sectional view showing a tenth step along the cross section of FIG. 2 as a method for manufacturing a nonvolatile semiconductor memory device according to the present invention. FIG.

FIG. 17 is a cross-sectional view showing an eleventh step along the cross section of FIG. 2 as a method for manufacturing a nonvolatile semiconductor memory device of the present invention.

FIG. 18 is a sectional view showing a twelfth step along the section of FIG. 2 as a method for manufacturing a nonvolatile semiconductor memory device according to the present invention.

FIG. 19 is a sectional view showing a thirteenth step along the section of FIG. 2 as a method for manufacturing a nonvolatile semiconductor memory device according to the present invention.

20 is a sectional view taken along the line II-II in FIG. 1, showing a second embodiment of the nonvolatile semiconductor memory device of the present invention. FIG.

21 is a cross-sectional view taken along line XXI-XXI of FIGS. 11 and 12, showing a first step along the cross-section of FIG. 3 as a method for manufacturing a nonvolatile semiconductor memory device of the present invention. .

22 is a sectional view showing a second step along the section of FIG. 3 as a method for manufacturing a nonvolatile semiconductor memory device of the present invention. FIG.

23 is a cross-sectional view showing a third step along the cross section of FIG. 3 as a method for manufacturing a nonvolatile semiconductor memory device of the present invention. FIG.

FIG. 24 is a cross-sectional view showing a fourth step along the cross section of FIG. 3 as a method for manufacturing a nonvolatile semiconductor memory device of the present invention.

FIG. 25 is a cross-sectional view showing a fifth step along the cross section of FIG. 3 as a method for manufacturing a nonvolatile semiconductor memory device of the present invention.

FIG. 26 is a sectional view showing a sixth step along the section of FIG. 3 as a method for manufacturing a nonvolatile semiconductor memory device according to the present invention.

FIG. 27 is a cross-sectional view showing a seventh step along the cross section of FIG. 3 as a method for manufacturing a nonvolatile semiconductor memory device of the present invention.

FIG. 28 is a sectional view showing an eighth step along the section of FIG. 3 as a method for manufacturing a nonvolatile semiconductor memory device according to the present invention.

FIG. 29 is a cross-sectional view showing a ninth step along the cross section of FIG. 3 as a method for manufacturing a nonvolatile semiconductor memory device of the present invention.

30 is a sectional view showing a tenth step along the section of FIG. 3 as a method for manufacturing a nonvolatile semiconductor memory device according to the present invention. FIG.

FIG. 31 is a cross-sectional view showing an eleventh step along the cross section of FIG. 3 as a method for manufacturing a nonvolatile semiconductor memory device of the present invention.

FIG. 32 is a block diagram showing a general configuration of a flash memory.

FIG. 33 is an equivalent circuit diagram showing a schematic configuration of the memory cell matrix shown in FIG. 32.

FIG. 34 is a partial cross-sectional view showing the cross-sectional structure of one memory transistor forming the flash memory.

FIG. 35 is a schematic plan view showing a planar arrangement of a conventional flash memory.

36 is a cross-sectional view taken along the line XXXVI-XXXVI of FIG. 35.

FIG. 37 is a cross-sectional view taken along the line XXXVII-XXXVII of FIG. 35.

FIG. 38 is a cross-sectional view showing a first step along the cross section of FIG. 37 as a method for manufacturing a conventional flash memory.

FIG. 39 is a cross-sectional view showing a second step along the cross section of FIG. 37 as a method for manufacturing a conventional flash memory.

FIG. 40 is a cross-sectional view showing a third step along the cross section of FIG. 37 as a method for manufacturing a conventional flash memory.

FIG. 41 is a cross-sectional structural diagram for explaining deterioration of endurance characteristics that occurs when data is erased.

[Explanation of symbols]

1 p-type well region, 5 isolation insulating film, 6 isolation impurity region, 55 control gate electrode, 57 n-type source region.

Claims (5)

[Claims] 1. A first-conductivity-type semiconductor substrate having a main surface, a first-conductivity-type isolation impurity region distributed at a predetermined depth from the main surface of the semiconductor substrate, and on the isolation-impurity region. A plurality of isolation insulating films formed on the semiconductor substrate at a distance from each other, and formed on the isolation impurity region in the semiconductor substrate between the isolation insulating films and spaced apart from the isolation impurity region. A non-volatile semiconductor memory device comprising a second conductivity type source region and a control gate electrode formed on the isolation insulating film. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the source region is formed apart from the isolation insulating film. 3. A first conductivity type semiconductor substrate having a main surface, and a first insulating film disposed on the main surface of the semiconductor substrate in a matrix of m rows and n columns (m × n). ) A plurality of charge storage electrodes, a plurality of device isolation insulating films formed on the semiconductor substrate in each column, extending over two rows of the charge storage electrodes, and a plurality of device isolation insulating films below the device isolation insulating film. An isolation impurity region of the first conductivity type distributed to a predetermined depth from the main surface, and a second insulating film interposed on the charge storage electrode and formed on the element isolation insulating film for each row. A word line, a drain region of the second conductivity type surrounded by the element isolation insulating film and the word line and formed on the main surface of the semiconductor substrate, and inside the semiconductor substrate between the element isolation insulating films. Above the isolation impurity region and away from the isolation impurity region. And with the source region of the second conductivity type formed, nonvolatile semiconductor memory device. 4. A first insulating film portion having a first thickness and a second insulating film portion having a second thickness larger than the first thickness.
Forming an insulating film composed of the insulating film portion on the main surface of the semiconductor substrate of the first conductivity type, and implanting impurity ions of the first conductivity type into the semiconductor substrate through the insulating film, From a region of the semiconductor substrate that is separated from the first insulating film portion below the second insulating film portion to a region of the semiconductor substrate that is close to the second insulating film portion below the second insulating film portion. Forming an isolation impurity region in a region of the semiconductor substrate below the insulating film so as to extend continuously; forming a control gate electrode on the insulating film; and using the control gate electrode as a mask Forming a plurality of isolation insulating films spaced apart from each other on the isolation impurity region by removing the first insulating film portion using the semiconductor between the isolation insulating films. A step of implanting a second conductivity type impurity ion on the isolation impurity region in a substrate to form a source region separated from the isolation impurity region. . 5. The method of manufacturing a nonvolatile semiconductor memory device according to claim 4, wherein the step of forming the source region includes forming the source region apart from the isolation insulating film.