JPH0962226A - Driving circuit of display panel - Google Patents
Driving circuit of display panelInfo
- Publication number
- JPH0962226A JPH0962226A JP21841695A JP21841695A JPH0962226A JP H0962226 A JPH0962226 A JP H0962226A JP 21841695 A JP21841695 A JP 21841695A JP 21841695 A JP21841695 A JP 21841695A JP H0962226 A JPH0962226 A JP H0962226A
- Authority
- JP
- Japan
- Prior art keywords
- display panel
- panel
- capacitance
- electrode
- fet switch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、パーソナルコンピ
ュータやオフィスワークステーションあるいは壁掛けテ
レビ等に用いられる平面型の表示パネルの駆動回路に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive circuit for a flat type display panel used in personal computers, office workstations, wall-mounted televisions and the like.
【０００２】[0002]
【従来の技術】本発明は、ＥＬ（エレクトロルミネツセ
ンス）パネルやＤＣ型ないしＡＣ型プラズマディスプレ
イパネルの駆動に用いることができる。ここでは、ＡＣ
型プラズマディスプレイパネルを例にとり説明する。The present invention can be used for driving an EL (electroluminescence) panel or a DC type or AC type plasma display panel. Here, AC
The plasma display panel will be described as an example.
【０００３】従来、かかるプラズマディスプレイパネル
は、絶縁基板間に走査電極や列電極等を格子状に配置
し、各交点に画素領域を形成することにより構成され
る。Conventionally, such a plasma display panel is constructed by arranging scanning electrodes, column electrodes, etc. in a grid pattern between insulating substrates and forming pixel regions at each intersection.
【０００４】図４（ａ）、（ｂ）はそれぞれかかる従来
の一例を説明するためのプラズマディスプレイパネルの
平面図およびＸ−Ｘ′線断面図である。図４（ａ）、
（ｂ）に示すように、従来のプラズマディスプレイパネ
ル２０は、共にガラス材によりなる第一の絶縁基板２１
および第二の絶縁基板２２と、第一の絶縁基板２１上に
交互に形成された透明な維持電極１６ａおよび透明な走
査電極１６ｂ並びにこれら維持電極１６ａ、走査電極１
６ｂ上に形成され且つこれら両電極１６ａ，１６ｂに十
分な電流を供給するための金属電極１６ｃと、これら維
持電極１６ａ乃至金属電極１６ｃに直交配置するように
第二の絶縁基板２２上に形成された列電極１７と、維持
電極１６ａ、走査電極１６ｂおよび金属電極１６ｃを覆
う絶縁層２３ａと、列電極１７を覆う絶縁層２３ｂと、
Ｈｅ、Ｘｅ等の放電ガスを充填する放電ガス空間２６を
確保するとともに画素１９を区切る隔壁１８と、第二の
絶縁基板２２の絶縁層２３ｂ上に形成され且つ放電ガス
の放電により発生する紫外線を可視光に変換する蛍光体
２４と、第一の絶縁基板２１上の絶縁層２３ａ上に形成
され、且つこの絶縁層２３ａを放電より保護するための
ＭｇＯ等よりなる保護層２５とで構成される。このパネ
ル２０において、縦および横の隔壁１８で囲まれた区画
が画素１９となり、この画素１９毎に蛍光体２４を３色
に塗り分ければ、カラー表示のプラズマディスプレイが
得られる。尚、図５（ｂ）において、ディスプレイの表
示方向は、上面あるいは下面のいずれでも可能である
が、この例の場合は下面の方が好ましい。FIGS. 4A and 4B are a plan view and a sectional view taken along line XX 'of a plasma display panel for explaining such a conventional example. FIG. 4 (a),
As shown in (b), the conventional plasma display panel 20 has a first insulating substrate 21 made of a glass material.
And the second insulating substrate 22, and the transparent sustain electrodes 16a and the transparent scan electrodes 16b, which are alternately formed on the first insulating substrate 21, and the sustain electrodes 16a and the scan electrode 1.
6b and a metal electrode 16c for supplying a sufficient current to both electrodes 16a and 16b, and a second insulating substrate 22 so as to be orthogonal to the sustain electrodes 16a to 16c. An insulating layer 23a that covers the column electrodes 17, the sustain electrodes 16a, the scan electrodes 16b, and the metal electrodes 16c, and an insulating layer 23b that covers the column electrodes 17.
A partition wall 18 that secures a discharge gas space 26 that is filled with a discharge gas such as He or Xe and partitions the pixels 19 and ultraviolet rays that are formed on the insulating layer 23b of the second insulating substrate 22 and that are generated by the discharge of the discharge gas are generated. It is composed of a phosphor 24 for converting into visible light and a protective layer 25 formed on the insulating layer 23a on the first insulating substrate 21 and made of MgO or the like for protecting the insulating layer 23a from discharge. . In this panel 20, a section surrounded by vertical and horizontal partition walls 18 becomes a pixel 19, and a phosphor 24 is divided into three colors for each pixel 19 to obtain a color display plasma display. In FIG. 5B, the display direction of the display may be either the upper surface or the lower surface, but in this example, the lower surface is preferable.
【０００５】図５は図４（ａ）、（ｂ）における電極配
置に着目したプラズマディスプレイパネルの平面図であ
る。図５に示すように、プラズマディスプレイパネル２
０の電極のみに着目すると、第一の電極基板２１と第二
の絶縁基板２２間に維持電極（Ｃ1 ，Ｃ2 …，Ｃm ）１
６ａ、走査電極（Ｓ1 ，Ｓ2 …，Ｓm ）１６ｂと列電極
（Ｄ1 ，…，Ｃn-1 およびＤ2 ，…，Ｄn ）１７とが画
素１９を形成する位置で交叉している。しかも、これら
第一の絶縁基板２１と第二の絶縁基板２２は、張り合わ
せることによりシール部２７を形成する。このシール部
２７は内部に放電ガスを封入し、気密にシールされる。FIG. 5 is a plan view of a plasma display panel focusing on the electrode arrangement in FIGS. 4 (a) and 4 (b). As shown in FIG. 5, the plasma display panel 2
Focusing only on the 0 electrode, the sustain electrodes (C 1 , C 2, ..., C m ) 1 are provided between the first electrode substrate 21 and the second insulating substrate 22.
6a, the scanning electrodes (S 1 , S 2 ..., S m ) 16b and the column electrodes (D 1 , ..., C n-1 and D 2 , ..., D n ) 17 intersect at a position where a pixel 19 is formed. ing. Moreover, the first insulating substrate 21 and the second insulating substrate 22 form the seal portion 27 by being bonded together. The seal portion 27 has a discharge gas filled therein and is hermetically sealed.
【０００６】かかるプラズマディスプレイパネルを駆動
するときは、走査電極１６ｂに走査パルスを印加し、列
電極１７に同じタイミングでデータパルスを印加して書
き込みを放電を行わせると、その後は隣あう維持電極
（例えばＣ1 ）１６ａと走査電極（例えばＳ1 ）１６ｂ
の間に交互に印加する維持パルスにより維持放電が持続
される。このとき、放電ガスにより紫外光が放出され、
これにより蛍光体［図４（ｂ）の２４］が刺激されて可
視光を放出するので、所望の表示発光が行われる。逆
に、放電を停止するには、維持パルスよりも電圧が低い
かパルス幅の極端に狭い消去パルスを維持電極１６ａと
走査電極１６ｂの間に印加するだけでよい。When driving such a plasma display panel, a scan pulse is applied to the scan electrodes 16b and a data pulse is applied to the column electrodes 17 at the same timing to cause writing discharge, and thereafter, the sustain electrodes adjacent to each other are applied. (Eg C 1 ) 16a and scan electrode (eg S 1 ) 16b
The sustain discharge is sustained by the sustain pulses alternately applied during the period. At this time, ultraviolet light is emitted by the discharge gas,
As a result, the phosphor [24 in FIG. 4B] is stimulated to emit visible light, and desired display light emission is performed. On the contrary, in order to stop the discharge, it is only necessary to apply an erase pulse having a voltage lower than the sustain pulse or an extremely narrow pulse width between the sustain electrode 16a and the scan electrode 16b.
【０００７】しかしながら、ＡＣ型プラズマディスプレ
イパネルは、面放電電極間および対向放電電極間共に誘
電体層が存在するので、コンデンサを形成してしまう。
すなわち、かかるパネルはエレクトロルミネセンス（Ｅ
Ｌ）パネルほどではないが、大きな容量を持つことにな
る。このような電極に維持パルスを印加すると、電極間
容量を充放電させる際、パネル容量値をＣP 、電源電圧
をＶＳとしたとき、電源から供給されるエネルギーＰは
以下に示す数１のようになる。However, in the AC type plasma display panel, since the dielectric layer exists between the surface discharge electrodes and between the opposed discharge electrodes, a capacitor is formed.
That is, such a panel has electroluminescence (E
L) It has a large capacity, though not as large as a panel. When a sustain pulse is applied to such electrodes, when the inter-electrode capacitance is charged / discharged, when the panel capacitance value is C P and the power source voltage is VS, the energy P supplied from the power source is as shown in Equation 1 below. become.
【０００８】[0008]
【数１】 となる。従って、立ち上がり時に電源より供給されるエ
ネルギーＰは、抵抗での損失分［（１／２）ＣP ×ＶＳ
2 ］と、パネル容量値ＣP に充電される分の［（１／
２）ＣP ×ＶＳ2 ］との和になる。また、立ち下がり時
にパネル容量より放電されるエネルギーは、抵抗での損
失分［（１／２）ＣP ×ＶＳ2 ］となる。通常の駆動回
路では、電源から供給されたエネルギーＰは、前記数１
で表されるが、１パルス毎にすべてスイッチング素子の
抵抗分やパネルの抵抗分で消費、すなわち損失されてい
ることになり、表示のためのガス放電には全く関与して
いない。この放電に関与しないでパネル容量値ＣP の充
放電時に消費される無効電力Ｐ′は、Ｐ′＝Ｐ×ｆ＝Ｃ
P ×ＶＳ2 ×ｆとなる。尚、ここでｆは実駆動時の駆動
周波数である。[Equation 1] Becomes Therefore, the energy P supplied from the power supply at the time of rising is the loss amount in the resistor [(1/2) C P × VS
2], the amount is charged to the panel capacitance C P [(1 /
2) C P × VS 2 ]. Further, the energy discharged from the panel capacitance at the time of falling is the loss [(1/2) C P × VS 2 ] in the resistance. In a normal driving circuit, the energy P supplied from the power source is the above-mentioned equation 1
However, it is consumed or lost by the resistance of the switching element or the resistance of the panel for each pulse, and is not involved in the gas discharge for display at all. The reactive power P'consumed during the charging / discharging of the panel capacitance value C P without being involved in this discharge is P '= P × f = C
It becomes P × VS 2 × f. Here, f is a drive frequency at the time of actual drive.
【０００９】このため、大型パネルの駆動にあたって
は、パネルサイズの増加と共にパネル容量値ＣP が増加
し、駆動周波数ｆも高くなるので、無効電力損失も大き
くなる。その結果、全体の消費電力の増大が小型パネル
の場合と比較して無視できないものとなる。また、大型
パネルでは負荷容量の、より大きな電源が必要になり、
電源回路自体も大きくなってしまう。従って、大型パネ
ルになればなる程、消費電力を削減できるプラズマディ
スプレイパネル電極の駆動回路を採用すれば、その効果
が大きいことになる。Therefore, when driving a large-sized panel, the panel capacitance value C P increases with the increase in the panel size and the driving frequency f also increases, so that the reactive power loss also increases. As a result, the increase in the total power consumption is not negligible as compared with the case of a small panel. Also, a large panel requires a larger power supply with a load capacity,
The power supply circuit itself also becomes large. Therefore, the larger the panel becomes, the greater the effect will be if the driving circuit of the plasma display panel electrode that can reduce the power consumption is adopted.
【００１０】かかる消費電力を削減したプラズマディス
プレイパネル電極の駆動回路は、例えば特公昭５６−３
０７３０号公報、特開昭６２−１９２７９８号公報ある
いは特開昭６３−１０１８９７号公報等に開示されてい
る。A driving circuit for a plasma display panel electrode with reduced power consumption is disclosed in, for example, Japanese Patent Publication No. 56-3.
No. 0730, JP-A-62-192798, JP-A-63-101897 and the like.
【００１１】図６はかかる従来の一例を示すプラズマデ
ィスプレイパネルの駆動回路図である。図６に示すよう
に、この駆動回路は、走査電極側駆動回路部３７と、こ
の走査電極側駆動回路部３７と同一構成の維持電極側駆
動回路部３８とからなり、双方の回路部３７，３８はパ
ネル電極間容量３９により結合される。ここでは、走査
電極側駆動回路部３７を代表して回路構成およびその動
作を説明する。FIG. 6 is a drive circuit diagram of a plasma display panel showing such a conventional example. As shown in FIG. 6, this drive circuit includes a scan electrode side drive circuit section 37 and a sustain electrode side drive circuit section 38 having the same configuration as the scan electrode side drive circuit section 37. 38 is coupled by a capacitance 39 between panel electrodes. Here, the circuit configuration and the operation thereof will be described on behalf of the scan electrode side drive circuit section 37.
【００１２】まず、走査電極側駆動回路部３７はパネル
の走査電極［Ｃ点］（維持電極側駆動回路部３８の時は
維持電極［Ｄ点］）にコイル３４を接続し、そのコイル
３４の両端に４個のＦＥＴスイッチ３０，３２，３５，
３６を維持するとともに、２個のＦＥＴスイッチ３０，
３２の一端には電力回収用コンデンサ２９を共通接続し
た構成である。尚、２８，３１，３３は逆電流阻止用ダ
イオードであり、４５，４６はＦＥＴスイッチ３０，３
２の寄生ダイオードを表したものである。First, the scan electrode side drive circuit portion 37 connects the coil 34 to the scan electrode [point C] of the panel (the sustain electrode [point D] when the sustain electrode side drive circuit portion 38 is provided), and the coil 34 is connected. Four FET switches 30, 32, 35 at both ends
36 and two FET switches 30,
A power recovery capacitor 29 is commonly connected to one end of 32. In addition, 28, 31, 33 are reverse current blocking diodes, and 45, 46 are FET switches 30, 3.
2 represents a parasitic diode of No. 2.
【００１３】この走査電極側駆動回路部３７において
は、コイル３４とパネル容量３９とで直列共振を起こさ
せることにより共振周期の１／２の期間にパネル容量３
９の電荷を充放電させる。一方、電力回収用コンデンサ
２９にパネル容量３９が充電される電圧ＶＳの約１／２
の電圧を外部から印加して、１回の走査電極パルス（維
持電極側駆動回路部３８の時は維持電極パルス）でパネ
ル容量３９への充放電に使用したエネルギーをコンデン
サ２９に回収（電力回収）させることにより、次の走査
電極パルスでパネル容量３９の充電に使用し、電圧ＶＳ
の電源線から新たに供給される電力を削減させる。In the scan electrode side drive circuit section 37, the panel capacitance 3 is generated during a half of the resonance period by causing series resonance with the coil 34 and the panel capacitance 39.
The charge of 9 is charged / discharged. On the other hand, about half the voltage VS with which the panel capacitor 39 is charged in the power recovery capacitor 29.
Is applied from the outside by a single scan electrode pulse (sustain electrode pulse in the case of the sustain electrode side drive circuit section 38), and the energy used for charging / discharging the panel capacitance 39 is recovered in the capacitor 29 (power recovery). ) Is used to charge the panel capacitor 39 with the next scan electrode pulse, and the voltage VS
To reduce the power newly supplied from the power line.
【００１４】図７は従来のパネル駆動を説明するための
パルス波形図である。図７に示すように、波形Ｖｃｐ
（Ｃ）は前述した図６の走査電極側駆動回路部３７にお
けるＣ点での走査電極パルスであり、ＩＮ９、ＩＮ１
０、ＩＮ１１、及びＩＮ１２は、それぞれＦＥＴスイッ
チ３０、ＦＥＴスイッチ３５、ＦＥＴスイッチ３２、Ｆ
ＥＴスイッチ３６を駆動するための入力駆動パルスが入
力される入力端子である。FIG. 7 is a pulse waveform diagram for explaining conventional panel driving. As shown in FIG. 7, the waveform Vcp
(C) is the scan electrode pulse at the point C in the scan electrode side drive circuit section 37 of FIG. 6 described above, and IN9, IN1
0, IN11, and IN12 are the FET switch 30, the FET switch 35, the FET switch 32, and F, respectively.
It is an input terminal to which an input drive pulse for driving the ET switch 36 is input.
【００１５】波形Ｖｃｐ（Ｄ）は同様に図７の維持電極
側駆動回路部３８におけるＤ点での維持電極パルスを表
し、ＩＮ１３、ＩＮ１４、ＩＮ１５、及びＩＮ１６は、
それぞれ図６のＤ点側の維持電極パルスを駆動するため
の維持電極側駆動回路部３８を構成する４個のＦＥＴス
イッチを駆動するための入力駆動パルスが入力される入
力端子である。ＩＬ（Ｃ）及びＩＬ（Ｄ）はパネルを充
電する方向を正としたときにコイル３４等を流れる電流
波形である。波形Ｖｃｐ（Ｄ）−Ｖｃｐ（Ｃ）は、面放
電電極間の動作がわかりやすいように、維持電極−走査
電極の合成波形を示したものである。この波形が両電極
間でみた維持パルス波形である。Similarly, the waveform Vcp (D) represents the sustain electrode pulse at the point D in the sustain electrode side drive circuit section 38 of FIG. 7, and IN13, IN14, IN15, and IN16 are
These are input terminals to which input drive pulses for driving the four FET switches constituting the sustain electrode side drive circuit unit 38 for driving the sustain electrode pulse on the point D side of FIG. 6 are input. IL (C) and IL (D) are current waveforms that flow through the coil 34 and the like when the direction of charging the panel is positive. A waveform Vcp (D) -Vcp (C) shows a composite waveform of the sustain electrodes and the scan electrodes so that the operation between the surface discharge electrodes can be easily understood. This waveform is the sustain pulse waveform seen between both electrodes.
【００１６】上述した走査電極側駆動回路部３７のパネ
ル容量３９における１サイクルでの電力損失Ｐ″は、走
査電極パルスＣ（あるいは維持電極パルスＤ）の立ち上
がり時間をｔｒ、駆動回路３７のスイッチング素子３０
または３２の抵抗分やダイオード３１，３３の順方向降
下による抵抗分とパネルの抵抗分の直列抵抗をＲ、コイ
ル３４のインダクタンス値をＬとすると、以下に示す数
２が成り立つ。The power loss P ″ in one cycle in the panel capacitance 39 of the scan electrode side drive circuit section 37 is the rise time of the scan electrode pulse C (or sustain electrode pulse D) tr, and the switching element of the drive circuit 37. Thirty
Alternatively, if the series resistance of the resistance of 32 or the resistance due to the forward drop of the diodes 31 and 33 and the resistance of the panel is R and the inductance value of the coil 34 is L, the following equation 2 is established.
【００１７】[0017]
【数２】 このため、上述した電力回収を行わない前記数１の回路
と比較すると、（ｔｒ×Ｒ）／（４×Ｌ）分だけ電力損
失が少ないことが分かる。[Equation 2] Therefore, it can be seen that the power loss is smaller by (tr × R) / (4 × L) as compared with the circuit of the above-mentioned Equation 1 in which the power recovery is not performed.
【００１８】また、各パルスの立ち上がり時間ｔｒ、立
ち下がり時間ｔｆとコイル３４のインダクタンス値Ｌと
パネル容量３９の容量値ＣP との間には、以下の数３に
示すような関係がある。Further, the rising time tr and the falling time tf of each pulse, the inductance value L of the coil 34, and the capacitance value C P of the panel capacitance 39 have a relationship as shown in the following Expression 3.
【００１９】[0019]
【数３】 前記数３を前記数２に代入すると、以下に示す数４が得
られる。(Equation 3) By substituting the equation 3 into the equation 2, the following equation 4 is obtained.
【００２０】[0020]
【数４】 従って、コイル３４のインダクタンス値Ｌが大きい程、
また抵抗分Ｒが少ない程、損失が少ないことになる。(Equation 4) Therefore, the larger the inductance value L of the coil 34,
Also, the smaller the resistance component R, the smaller the loss.
【００２１】[0021]
【発明が解決しようとする課題】上述した従来のプラズ
マディスプレイパネルの駆動回路は、共通維持電極用と
走査電極用の２回路が必要である。このため、図６に示
すように、走査側電極パルスＣを駆動するために入力端
子ＩＮ９〜入力端子ＩＮ１２にそれぞれ入力される４個
の入力駆動パルス、共通維持電極パルスＤを駆動するた
めに、入力端子ＩＮ１３〜入力端子ＩＮ１６にそれぞれ
入力される４個の入力駆動パルスが必要である。また、
走査側電極パルスＣと共通維持電極パルスＤは互いに半
周期位相をずらせて駆動しているため、入力端子ＩＮ９
〜入力端子ＩＮ１２にそれぞれ入力される４個の入力駆
動パルスと入力端子ＩＮ１３〜入力端子ＩＮ１６に入力
される４個の入力駆動パルスは、別々の回路で作成され
ることになり、入力駆動パルス数が多かった。The conventional driving circuit for the plasma display panel described above requires two circuits for the common sustain electrode and the scan electrode. Therefore, as shown in FIG. 6, in order to drive the common sustain electrode pulse D and the four input drive pulses respectively input to the input terminals IN9 to IN12 to drive the scanning-side electrode pulse C, Four input drive pulses input to the input terminals IN13 to IN16 are required. Also,
Since the scanning-side electrode pulse C and the common sustain electrode pulse D are driven with their half-cycle phases shifted from each other, the input terminal IN9
~ The four input drive pulses input to the input terminal IN12 and the four input drive pulses input to the input terminal IN13 to the input terminal IN16 are to be created by different circuits, and the number of input drive pulses There were many
【００２２】また、この回路では、回収回路にダイオー
ド３１，３３が存在するため、前記ダイオードの順方向
降下が抵抗成分として存在し、それが上述の数４の中の
直列抵抗Ｒに加わり消費電力の損失となる。Further, in this circuit, since the diodes 31 and 33 are present in the recovery circuit, the forward drop of the diode is present as a resistance component, which is added to the series resistance R in the above-mentioned equation 4, and the power consumption is reduced. Will be lost.
【００２３】本発明の課題は、上記の問題点を解決し、
より簡単な回路構成として部品点数を減らすとともに消
費電力の損失が少ない、電力回収を行う表示パネルの駆
動回路を提供することにある。An object of the present invention is to solve the above problems,
It is an object of the present invention to provide a display panel driving circuit which has a simpler circuit configuration, reduces the number of components, and has a small power consumption loss, and which recovers power.
【００２４】[0024]
【課題を解決するための手段】本発明によれば、表示パ
ネルの電極に印加するパルスを発生すると共に、前記表
示パネルの一方の電極に接続され、前記表示パネルの電
極間静電容量に等価的に接続され、前記表示パネルの電
極間静電容量の充放電時に共振電流を発生させる第１の
充放電回路部と、前記表示パネルの他方の電極に接続さ
れ、前記表示パネルの電極間静電容量に等価的に接続さ
れ、前記表示パネルの電極間静電容量の充放電時に共振
電流を発生させる第２の充放電回路部と、前記表示パネ
ルの一方の電極および他方の電極に接続されて前記表示
パネルの電極を一定の電位に保つ電圧クランプ部と、共
通接続された前記第１の充放電回路部の他端と前記第２
の充放電回路部の他端に接続される電力回収用のコンデ
ンサとからなることを特徴とする表示装置の駆動回路が
得られる。According to the present invention, a pulse to be applied to an electrode of a display panel is generated and is connected to one electrode of the display panel and is equivalent to an inter-electrode capacitance of the display panel. And a first charging / discharging circuit portion that is connected to the other electrode of the display panel and that is connected to the other electrode of the display panel. A second charging / discharging circuit portion that is equivalently connected to the capacitance and generates a resonance current when charging / discharging the inter-electrode capacitance of the display panel, and is connected to one electrode and the other electrode of the display panel. And a second end of the commonly connected first charging / discharging circuit portion and the second clamp portion for holding the electrode of the display panel at a constant potential.
A drive circuit for a display device is obtained which comprises a power recovery capacitor connected to the other end of the charging / discharging circuit section.
【００２５】さらに、本発明によれば、前記第１の充放
電回路部が、前記表示パネルのパネル容量の充放電時に
共振電流を発生するコイルと、それぞれパネル容量の充
電時および放電時における共振電流を独立に制御するＮ
チャンネルのＦＥＴスイッチおよびＰチャンネルのＦＥ
Ｔスイッチとからなることを特徴とする表示装置の駆動
回路が得られる。Further, according to the present invention, the first charging / discharging circuit section generates a resonance current when the panel capacitance of the display panel is charged and discharged, and a resonance when the panel capacitance is charged and discharged, respectively. N that controls the current independently
Channel FET switch and P channel FE
A drive circuit for a display device is obtained, which is characterized by comprising a T switch.
【００２６】さらに、本発明によれば、前記第２の充放
電回路部が、前記表示パネルのパネル容量の充放電時に
共振電流を発生するコイルと、それぞれパネル容量の充
電時および放電時における共振電流のそれぞれを独立に
制御するＮチャンネルのＦＥＴスイッチおよびＰチャン
ネルのＦＥＴスイッチとからなることを特徴とする表示
装置の駆動回路が得られる。Further, according to the present invention, the second charging / discharging circuit section generates a resonance current when the panel capacity of the display panel is charged / discharged, and a resonance when the panel capacity is charged and discharged, respectively. A drive circuit for a display device is obtained, which is composed of an N-channel FET switch and a P-channel FET switch for independently controlling respective currents.
【００２７】さらに、本発明によれば、前記第１の充放
電回路部のＰチャンネルのＦＥＴスイッチと前記第２の
充放電回路部のＰチャンネルのＦＥＴスイッチとが共通
接続されていてこれら端子に前記電力回収用のコンデン
サが共通接続されていることを特徴とする表示装置の駆
動回路が得られる。Further, according to the present invention, the P-channel FET switch of the first charge / discharge circuit section and the P-channel FET switch of the second charge / discharge circuit section are commonly connected to these terminals. A drive circuit for a display device is obtained in which the capacitors for recovering the electric power are commonly connected.
【００２８】さらに、本発明によれば、前記電圧クラン
プ部が前記表示パネルのパネル容量の両端と電源線およ
び接地線間に接続される第１および第２のＮチャンネル
のＦＥＴスイッチ並びに第１および第２のＰチャンネル
のＦＥＴスイッチを有して構成されていることを特徴と
する表示装置の駆動回路が得られる。Further, according to the present invention, the voltage clamp section is connected between both ends of the panel capacitance of the display panel and the power supply line and the ground line, and first and second N-channel FET switches and the first and second N-channel FET switches. A drive circuit for a display device is obtained which is configured to have a second P-channel FET switch.
【００２９】[0029]
【作用】本発明は、コイルおよびＦＥＴスイッチで構成
される回路の一端をパネル容量の一端の電極に接続し
て、第１の直列共振回路を形成し、もう一つのコイルお
よびＦＥＴスイッチで構成される回路の一端をパネル容
量の他端の電極に接続して、第２の直列共振回路を形成
し、第１の直列共振回路と第２の直列共振回路のパネル
容量に接続してない両回路の他端を共通接続し、この地
点と対接地間に回収用のコンデンサを接続し、さらに、
パネル容量の両端に電源線あるいは接地線に接続された
４個のスイッチを接続する。このパネル容量の充放電の
度に第１の直列共振回路と第２の直列共振回路と４個の
スイッチの組み合わせにより共振を起こさせ、パネルの
充電に使用した電荷は、回収コンデンサに回収され、次
の充放電に使用する。このようにすると電源線から供給
されるパネルの充放電電力が減るので、駆動に要する消
費電力を少なくできる。According to the present invention, one end of a circuit composed of a coil and a FET switch is connected to an electrode at one end of a panel capacitor to form a first series resonance circuit, and another coil and a FET switch are formed. Both circuits that are connected to one electrode of the other end of the panel capacitance to form a second series resonance circuit and are not connected to the panel capacitances of the first series resonance circuit and the second series resonance circuit. The other end of is connected in common, and a recovery capacitor is connected between this point and the ground,
Connect four switches connected to the power line or ground line to both ends of the panel capacitance. Each time the panel capacitance is charged / discharged, resonance is caused by the combination of the first series resonance circuit, the second series resonance circuit, and the four switches, and the charge used to charge the panel is recovered by the recovery capacitor, Used for the next charge and discharge. In this way, the charge / discharge power of the panel supplied from the power supply line is reduced, so that the power consumption required for driving can be reduced.
【００３０】また、第１の直列共振回路を形成するコイ
ルの両端の２個のＦＥＴスイッチは同一タイミングで動
作し、第２の直列共振回路を形成するコイルの両端の２
個のＦＥＴスイッチも、同一タイミングで動作している
ので、合計６個の入力駆動パルスですむことになり、従
来の駆動回路が両電極用に計８個の入力駆動パルスが必
要であったことと比較すると２個少ないので、駆動回路
規模が小さくなる。Further, the two FET switches at both ends of the coil forming the first series resonance circuit operate at the same timing, and the two FET switches at both ends of the coil forming the second series resonance circuit are operated.
Since each FET switch is also operating at the same timing, a total of 6 input drive pulses are required, and the conventional drive circuit required a total of 8 input drive pulses for both electrodes. Since the number of driving circuits is smaller than the number of driving circuits by 2, the driving circuit scale is reduced.
【００３１】加えて、回収回路の経路にダイオードが存
在しないため、順方向降下の抵抗成分による消費電力損
失が少なくてすむ。In addition, since there is no diode in the path of the recovery circuit, power consumption loss due to the resistance component of the forward drop can be reduced.
【００３２】[0032]
【発明の実施の形態】次に、本発明の実施例について図
面を参照して説明する。図１は本発明の一実施例を示す
プラズマディスプレイパネルの駆動回路である。図１に
示すように、本実施例はプラズマディスプレイパネル１
の走査電極と維持電極間に接続されてこれら電極に印加
するパルスを発生すると共に、これら電極間の静電容量
であるパネル容量ＣＰに等価的に直列接続された第１の
充放電回路部２と第２の充放電回路部３と、走査電極お
よび維持電極に接続させてこれらの電極を一定の電位に
保つ電圧クランプ部４とを含んでいる。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a driving circuit of a plasma display panel showing an embodiment of the present invention. As shown in FIG. 1, the present embodiment is a plasma display panel 1
Is connected between the scan electrode and the sustain electrode to generate a pulse to be applied to these electrodes, and is equivalently connected in series to the panel capacitance CP which is the electrostatic capacitance between these electrodes. And a second charge / discharge circuit section 3 and a voltage clamp section 4 connected to the scan electrodes and the sustain electrodes to keep these electrodes at a constant potential.
【００３３】このうち、第１の充放電回路部２はパネル
１の電極間容量ＣＰの一端に接続され、このパネル容量
ＣＰの充放電時に共振電流を発生するコイル１０と、そ
れぞれパネル容量ＣＰの充電時または放電時における共
振電流を独立に制御するＮチャンネルのＦＥＴスイッチ
１２およびＰチャンネルのＦＥＴスイッチ１４とを直列
接続して構成されている。Of these, the first charging / discharging circuit section 2 is connected to one end of the interelectrode capacitance CP of the panel 1, and the coil 10 for generating a resonance current at the time of charging / discharging the panel capacitance CP and the panel capacitance CP respectively. An N-channel FET switch 12 and a P-channel FET switch 14 that independently control the resonance current during charging or discharging are connected in series.
【００３４】第２の充放電回路部３はパネル１の電極間
容量ＣＰの他端に接続され、このパネル容量ＣＰの充放
電時に共振電流を発生するコイル１１と、それぞれパネ
ル容量ＣＰの充電時または放電時における共振電流を独
立に制御するＮチャンネルのＦＥＴスイッチ１３および
ＰチャンネルのＦＥＴスイッチ１５とを直列接続して構
成されている。The second charging / discharging circuit section 3 is connected to the other end of the interelectrode capacitance CP of the panel 1, and generates a resonance current when the panel capacitance CP is charged / discharged, and when the panel capacitance CP is charged. Alternatively, an N-channel FET switch 13 and a P-channel FET switch 15 that independently control the resonance current during discharge are connected in series.
【００３５】ここで第１の充放電回路２のＰチャンネル
のＦＥＴスイッチ１４のソース端子と第２の充放電回路
３のＰチャンネルのＦＥＴスイッチ１５のソース端子は
共通接続されていて、またこの端子に電力回収用コンデ
ンサ５も共通接続されている。Here, the source terminal of the P-channel FET switch 14 of the first charge / discharge circuit 2 and the source terminal of the P-channel FET switch 15 of the second charge / discharge circuit 3 are commonly connected, and this terminal is also connected. An electric power recovery capacitor 5 is also commonly connected to.
【００３６】尚、ＦＥＴスイッチ１２，１３，１４，１
５のドレイン端子とソース端子の間にそれぞれ接続され
てるダイオード４１，４２，４３，４４はＦＥＴの寄生
ダイオードをあらわしている。The FET switches 12, 13, 14, 1
Diodes 41, 42, 43 and 44 respectively connected between the drain terminal and the source terminal of 5 represent FET parasitic diodes.
【００３７】一方、電圧クランプ部４は、パネル容量Ｃ
Ｐの両端と電源線（即ち、電源電圧ＶＳ）および接地線
間に接続される４つのＦＥＴスイッチ６〜９から構成さ
れている。また、ＦＥＴスイッチ６，８およびＦＥＴス
イッチ７，９は共にＣＭＯＳ型回路構成のＰチャンネル
ＦＥＴおよびＮチャンネルＦＥＴを用い、ＦＥＴスイッ
チ６〜９は、それぞれ入力端子ＩＮ１〜ＩＮ４に入力さ
れ、各ゲートに供給される異なるスイッチ駆動のための
入力駆動パルスで制御される。この電圧クランプ部４は
容量ＣＰの端子電圧を電源電圧ＶＳおよび接地線にクラ
ンプする機能を備えている。On the other hand, the voltage clamp section 4 has a panel capacitance C.
It is composed of four FET switches 6 to 9 connected between both ends of P and a power supply line (that is, power supply voltage VS) and a ground line. Further, the FET switches 6 and 8 and the FET switches 7 and 9 are both P-channel FETs and N-channel FETs having a CMOS type circuit configuration, and the FET switches 6 to 9 are input to the input terminals IN1 to IN4, respectively, and are input to their gates. It is controlled by the input drive pulses for driving different switches. The voltage clamp unit 4 has a function of clamping the terminal voltage of the capacitor CP to the power supply voltage VS and the ground line.
【００３８】図２は、この駆動回路における処理信号
（駆動電圧）およびその電流（駆動電流）の波形をタイ
ミングチャートにより示したものである。ここでは、上
述したスイッチＦＥＴ６，７，８，９のゲート入力信号
による動作を表す波形と、パネル容量ＣＰの走査電極側
の波形Ｖｃｐ（Ａ）、維持電極側の波形Ｖｃｐ（Ｂ）
と、プラズマディスプレイパネルを充電する方向を正と
した場合のコイル１０，１１に流れる電流ＩＬ１，ＩＬ
２の波形とを示している。なお、８個のスイッチを駆動
するための入力端子ＩＮ１〜ＩＮ８に入力される入力駆
動パルスについてみると、入力端子ＩＮ５に入力される
入力駆動パルス（ＩＮ５）と入力端子ＩＮ７に入力され
る入力駆動パルス（ＩＮ７）、入力端子ＩＮ６に入力さ
れる入力駆動パルス（ＩＮ６）と入力端子ＩＮ８に入力
される入力駆動パルス（ＩＮ８）は互いに反転した信号
であるため、インバータを用いることにより６種類の入
力波形があればよい。FIG. 2 is a timing chart showing the waveforms of the processing signal (driving voltage) and its current (driving current) in this driving circuit. Here, a waveform representing the operation of the switch FETs 6, 7, 8, 9 described above by the gate input signal, a waveform Vcp (A) on the scan electrode side of the panel capacitance CP, and a waveform Vcp (B) on the sustain electrode side.
And the currents IL1 and IL flowing through the coils 10 and 11 when the direction of charging the plasma display panel is positive.
2 waveforms are shown. Regarding the input drive pulses input to the input terminals IN1 to IN8 for driving the eight switches, the input drive pulse (IN5) input to the input terminal IN5 and the input drive pulse input to the input terminal IN7 will be described. Since the pulse (IN7), the input drive pulse (IN6) input to the input terminal IN6, and the input drive pulse (IN8) input to the input terminal IN8 are mutually inverted signals, six types of inputs can be obtained by using an inverter. There should be a waveform.
【００３９】具体的にいえば、入力端子ＩＮ１に入力さ
れる入力駆動パルス（ＩＮ１）がＦＥＴスイッチ６のゲ
ート・ソース間電圧として供給されると、期間ａでオン
し、その他の期間ｂ，ｃ，ｄ，ｅ，ｆでオフとなる。ま
た、入力端子ＩＮ２に入力される入力駆動パルス（ＩＮ
２）がＦＥＴスイッチ７のゲート・ソース間電圧として
供給されると、期間ｄでオンし、その他の期間ａ，ｂ，
ｃ，ｅ，ｆでオフとなる。同様に、入力端子ＩＮ３に入
力される入力駆動パルス（ＩＮ３）がＦＥＴスイッチ８
のゲート・ソース間電圧として供給されると、期間で
ｃ，ｄ，ｅオンし、その他の期間ａ，ｂ，ｆでオフとな
る。同様に、入力端子ＩＮ４に入力される入力駆動パル
ス（ＩＮ４）がＦＥＴスイッチ９のゲート・ソース間電
圧として供給されると、期間ａ，ｂ，ｆでオンし、その
他の期間ｃ，ｄ，ｅでオフとなる。一方、入力駆動パル
ス（ＩＮ５）及び入力駆動パルス（ＩＮ７）がそれぞれ
ＦＥＴスイッチ１２及びＦＥＴスイッチ１４のゲート・
ソート間電圧として供給されると、期間ｂ，ｆでオン
し、その他の期間ａ，ｃ，ｄ，ｅでオフとなり、また、
入力駆動パルス（ＩＮ６）及び入力駆動パルス（ＩＮ
８）がそれぞれＦＥＴスイッチ１３及びＦＥＴスイッチ
１５のゲート・ソート間電圧として供給されると、期間
ｃ，ｅでオンし、その他の期間ａ，ｂ，ｄ，ｆでオフと
なる。Specifically, when the input drive pulse (IN1) input to the input terminal IN1 is supplied as the gate-source voltage of the FET switch 6, the FET switch 6 turns on in the period a and the other periods b and c. , D, e, f are turned off. In addition, the input drive pulse (IN
2) is supplied as the gate-source voltage of the FET switch 7, it is turned on in the period d, and the other periods a, b,
It turns off at c, e, and f. Similarly, the input drive pulse (IN3) input to the input terminal IN3 is the FET switch 8
When it is supplied as the gate-source voltage of the above, it turns on c, d, and e during the period and turns off during the other periods a, b, and f. Similarly, when the input drive pulse (IN4) input to the input terminal IN4 is supplied as the gate-source voltage of the FET switch 9, the FET switch 9 turns on in the periods a, b, f, and the other periods c, d, e. Turns off. On the other hand, the input drive pulse (IN5) and the input drive pulse (IN7) are applied to the gates of the FET switch 12 and the FET switch 14, respectively.
When supplied as a voltage between sorts, it is turned on in the periods b and f, turned off in the other periods a, c, d, e, and
Input drive pulse (IN6) and input drive pulse (IN
When 8) is supplied as the gate-sort voltage of the FET switch 13 and the FET switch 15, respectively, it is turned on in the periods c and e, and turned off in the other periods a, b, d and f.
【００４０】このパネル駆動の１周期は、期間ａから期
間ｆまでである。以下、図３を用いてクランプ動作を具
体的に説明する。One panel driving cycle is from the period a to the period f. Hereinafter, the clamp operation will be specifically described with reference to FIG.
【００４１】図３（ａ）〜（ｆ）はそれぞれ図２におけ
る各期間の回路動作説明図である。まず、図３（ａ）に
示すように、期間ａにおいて、ＦＥＴスイッチ６，９が
閉じられているので、パネル容量ＣＰは電源（ＶＳ）と
接地間に接続されているので、図示の極性で充電電流Ｉ
ｃが流れ、パネル容量ＣＰに電荷が充電される。従っ
て、Ａ点での走査電極パルスＶｃｐ（Ａ）は、電源電圧
ＶＳにクランプされ、Ｂ点での維持電極パルスＶｃｐ
（Ｂ）は、接地されている。なお、ＦＥＴスイッチ７，
８，１２，１３，１４，１５は開放状態にあり、以下同
様に特に説明しないＦＥＴスイッチは、開放されている
ものとする。FIGS. 3 (a) to 3 (f) are diagrams for explaining the circuit operation in each period in FIG. First, as shown in FIG. 3A, since the FET switches 6 and 9 are closed in the period a, the panel capacitance CP is connected between the power supply (VS) and the ground, and therefore the polarity shown in FIG. Charging current I
c flows, and the panel capacitance CP is charged. Therefore, the scan electrode pulse Vcp (A) at the point A is clamped to the power supply voltage VS, and the sustain electrode pulse Vcp at the point B is obtained.
(B) is grounded. In addition, the FET switch 7,
It is assumed that the FET switches 8, 12, 13, 14, and 15 are in the open state, and the FET switches not specifically described below are also open.
【００４２】次に、図３（ｂ）に示すように、期間ｂで
はＦＥＴスイッチ６を開き、所定の時間の経過後にＦＥ
Ｔスイッチ１２，１４を閉じると、パネル容量ＣＰに蓄
えられた電荷はコイル１０を通り、電力回収用コンデン
サ５に向かって放電電流を流す。このとき、コイル１０
には逆起電力が発生して電流（共振電流）ＩＬ１が流
れ、電力回収用コンデンサ５に電荷が蓄えられる。Next, as shown in FIG. 3B, in the period b, the FET switch 6 is opened, and after a predetermined time has elapsed, the FE
When the T switches 12 and 14 are closed, the electric charge stored in the panel capacitance CP passes through the coil 10 and a discharge current flows toward the power recovery capacitor 5. At this time, the coil 10
A counter electromotive force is generated in the current and a current (resonance current) IL1 flows, and electric charge is stored in the power recovery capacitor 5.
【００４３】なお、パネル容量ＣＰのＡ点の電位Ｖｃｐ
（Ａ）は下がり、この後にパネル容量部を流れる電流は
零に達する。The potential Vcp at the point A of the panel capacitance CP is
(A) goes down, after which the current flowing through the panel capacitance section reaches zero.
【００４４】次に、図３（ｃ）に示すように、期間ｃで
はパネル容量ＣＰのＡ点の電位Ｖｃｐ（Ａ）が最低値に
なるときにＦＥＴスイッチ９，１２，１４を開き、ＦＥ
Ｔスイッチ８を閉じる。ＦＥＴスイッチ８を閉じること
により、パネル容量ＣＰのＡ点の電位Ｖｃｐ（Ａ）は零
電位にクランプされる。所定の時間の経過後にＦＥＴス
イッチ１３，１５を閉じると、電力回収コンデンサ５に
蓄えられた電荷はコイル１１を通してパネル容量ＣＰに
向かって流れる。このときコイル１１の逆起電力によ
り、共振電流ＩＬ２が流れ、パネル容量ＣＰが充電され
る。このとき、パネル容量ＣＰを流れる電流が零に達す
ると、パネル容量ＣＰのＢ点での電位Ｖｃｐ（Ｂ）は、
電源電圧ＶＳ付近まで上昇する。Next, as shown in FIG. 3C, in the period c, when the potential Vcp (A) at the point A of the panel capacitance CP becomes the minimum value, the FET switches 9, 12, 14 are opened and FE is set.
The T switch 8 is closed. By closing the FET switch 8, the potential Vcp (A) at the point A of the panel capacitance CP is clamped to zero potential. When the FET switches 13 and 15 are closed after the elapse of a predetermined time, the electric charge stored in the power recovery capacitor 5 flows through the coil 11 toward the panel capacitance CP. At this time, the resonance current IL2 flows due to the counter electromotive force of the coil 11, and the panel capacitance CP is charged. At this time, when the current flowing through the panel capacitance CP reaches zero, the potential Vcp (B) at the point B of the panel capacitance CP becomes
It rises to near the power supply voltage VS.
【００４５】次に、図３（ｃ）に示すように、期間ｄで
はＦＥＴスイッチ１３，１５を開き、ＦＥＴスイッチ７
が閉じられるので、パネル容量ＣＰは再び、電源（Ｖ
Ｓ）と接地間に接続されているので、図示の極性で充電
電流Ｉｃが流れ、パネル容量ＣＰに電荷が充電される。
従って、Ｂ点での走査電極パルスＶｃｐ（Ｂ）は電源電
圧ＶＳにクランプされ、Ａ点での維持電極パルスＶｃｐ
（Ａ）は、接地されている。Next, as shown in FIG. 3C, in the period d, the FET switches 13 and 15 are opened and the FET switch 7 is opened.
Is closed, the panel capacitance CP is again set to the power supply (V
Since it is connected between S) and the ground, the charging current Ic flows with the polarity shown in the figure, and the panel capacitance CP is charged with electric charges.
Therefore, the scan electrode pulse Vcp (B) at the point B is clamped to the power supply voltage VS, and the sustain electrode pulse Vcp at the point A is obtained.
(A) is grounded.
【００４６】次に、図３（ｅ）に示すように、期間ｅで
はスイッチ７を開き、所定の時間の経過後にＦＥＴスイ
ッチ１３，１５を閉じると、パネル容量ＣＰに蓄えられ
た電荷はコイル１１を通り、電力回収用コンデンサ５に
向かって放電電流を流す。このとき、コイル１１には逆
起電力が発生して電流（共振電流）ＩＬ２が流れ、電力
回収用コンデンサ５に電荷が蓄えられる。Next, as shown in FIG. 3 (e), when the switch 7 is opened in the period e and the FET switches 13 and 15 are closed after a predetermined time elapses, the electric charge accumulated in the panel capacitance CP is stored in the coil 11. A discharge current is caused to flow toward the electric power recovery capacitor 5 through. At this time, a counter electromotive force is generated in the coil 11, a current (resonance current) IL2 flows, and electric charges are stored in the power recovery capacitor 5.
【００４７】なお、パネル容量ＣＰのＢ点の電位Ｖｃｐ
（Ｂ）は下がり、この後にパネル容量部を流れる電流は
零に達する。The potential Vcp at the point B of the panel capacitance CP is
(B) goes down, after which the current flowing through the panel capacitance section reaches zero.
【００４８】最後に、図３（ｆ）に示すように、期間ｆ
ではパネル容量ＣＰのＢ点の電位Ｖｃｐ（Ｂ）が最低値
になるときにＦＥＴスイッチ８，１３，１５を開き、Ｆ
ＥＴスイッチ９を閉じる。ＦＥＴスイッチ９を閉じるこ
とにより、パネル容量ＣＰのＢ点の電位Ｖｃｐ（Ｂ）は
零電位にクランプされる。所定の時間の経過後にＦＥＴ
スイッチ１２，１４を閉じると、電力回収コンデンサ５
に蓄えられた電荷はコイル１０を通してパネル容量ＣＰ
に向かって流れる。このときコイル１０の逆起電力によ
り、共振電流ＩＬ１が流れ、パネル容量ＣＰが充電され
る。このとき、パネル容量ＣＰを流れる電流が零に達す
ると、パネル容量ＣＰのＡ点での電位Ｖｃｐ（Ａ）は、
電源電圧ＶＳ付近まで上昇する。Finally, as shown in FIG. 3 (f), the period f
Then, when the potential Vcp (B) at the point B of the panel capacitance CP becomes the minimum value, the FET switches 8, 13 and 15 are opened, and F
Close the ET switch 9. By closing the FET switch 9, the potential Vcp (B) at the point B of the panel capacitance CP is clamped to zero potential. FET after a predetermined time
When the switches 12 and 14 are closed, the power recovery capacitor 5
The electric charge stored in the
Flows towards At this time, the counter current of the coil 10 causes the resonance current IL1 to flow, and the panel capacitance CP is charged. At this time, when the current flowing through the panel capacitance CP reaches zero, the potential Vcp (A) at the point A of the panel capacitance CP becomes
It rises to near the power supply voltage VS.
【００４９】以降は期間ａからｆの繰り返し動作とな
る。このようにして、電力回収用コンデンサ５に蓄えら
れた電荷は１サイクルで２回、パネル容量ＣＰの充電に
使用される。After that, the operation is repeated from the periods a to f. In this way, the electric charge stored in the power recovery capacitor 5 is used twice to charge the panel capacitance CP in one cycle.
【００５０】上述した本実施例によれば、パネル容量Ｃ
Ｐ、コイル１０，１１、電力回収用コンデンサ５および
各ＦＥＴスイッチ６〜９および各ＦＥＴスイッチ１２〜
１５のタイミングを制御した共振動作により、パネル容
量ＣＰの充放電電力を削減し、次のサイクルまでの間
に、前のサイクルの無効電力の大部分を、少ない部品点
数で回収することができる。According to this embodiment described above, the panel capacitance C
P, coils 10, 11, power recovery capacitor 5, FET switches 6-9 and FET switches 12-
By the resonance operation in which the timing of 15 is controlled, the charge / discharge power of the panel capacitance CP can be reduced, and most of the reactive power in the previous cycle can be recovered with a small number of parts until the next cycle.
【００５１】具体的に、本実施例の消費電力の削減につ
いて検討する。まず、電源線の電圧ＶＳと流入する直流
電流との積より消費電力Ｐを求め、また従来の駆動回路
の消費電力としてのＣP ×ＶＳ2 ×ｆも求めて無効電力
の回収率ηを算出すると、回収率η（％）は以下に示す
数５にて求められる。Specifically, the reduction of power consumption of this embodiment will be examined. First, the power consumption P is obtained from the product of the voltage VS of the power supply line and the inflowing DC current, and C P × VS 2 × f as the power consumption of the conventional drive circuit is also obtained to calculate the reactive power recovery rate η. Then, the recovery rate η (%) is obtained by the following Equation 5.
【００５２】[0052]
【数５】 また、本発明回路は、図６に示す従来例の回路と比較す
ると、電力回収用コンデンサの充放電の経路にダイオー
ドが不要となるので、回収率が向上した。図６に示す従
来例の回路のダイオード３１，３３は、電力回収用コン
デンサ２９の充電経路が、ＦＥＴスイッチ３２を経由
し、放電経路がＦＥＴスイッチ３０を経由するようにな
っているため、ＦＥＴスイッチ３０，３２の内部寄生ダ
イオード４５，４６が図示の方向に存在するために、逆
電流が流れるのを阻止するためのものである。(Equation 5) Further, in the circuit of the present invention, a diode is not required in the charging / discharging path of the power recovery capacitor as compared with the circuit of the conventional example shown in FIG. 6, so the recovery rate is improved. In the diodes 31 and 33 of the circuit of the conventional example shown in FIG. 6, the charge path of the power recovery capacitor 29 passes through the FET switch 32, and the discharge path passes through the FET switch 30. Since the internal parasitic diodes 45 and 46 of 30 and 32 exist in the direction shown in the figure, the reverse current is prevented from flowing.
【００５３】本発明回路では、第１の充放電回路２にお
いて、ＦＥＴスイッチ１２としてのＮチャンネルＦＥＴ
とＦＥＴスイッチ１４としてのＰチャンネルＦＥＴを、
ＦＥＴスイッチ１２のドレイン端子側をパネル容量ＣＰ
の一端に、ＦＥＴスイッチ１４のソース端子側を電力回
収用コンデンサ５に、向けるように接続することによ
り、寄生ダイオード４１，４３が図示のように順方向が
相反する向きに接続されている。In the circuit of the present invention, the N-channel FET as the FET switch 12 in the first charge / discharge circuit 2 is used.
And a P-channel FET as the FET switch 14,
The drain terminal side of the FET switch 12 is the panel capacitance CP.
By connecting the source terminal side of the FET switch 14 to the power recovery capacitor 5 at one end thereof, the parasitic diodes 41 and 43 are connected in opposite directions as shown in the drawing.
【００５４】同様に第２の充放電回路３においても、Ｆ
ＥＴスイッチ１３としてのＮチャンネルＦＥＴとＦＥＴ
スイッチ１５としてのＰチャンネルＦＥＴを、ＦＥＴス
イッチ１３のドレイン端子側をパネル容量ＣＰの他端
に、ＦＥＴスイッチ１５のソース端子側を電力回収用コ
ンデンサ５に、向けるように接続することにより、寄生
ダイオード４２，４４が図示のように順方向が相反する
向きに接続されている。Similarly, in the second charge / discharge circuit 3, F
N-channel FET and FET as ET switch 13
By connecting the P-channel FET as the switch 15 so that the drain terminal side of the FET switch 13 faces the other end of the panel capacitance CP and the source terminal side of the FET switch 15 faces the power recovery capacitor 5, a parasitic diode is formed. 42 and 44 are connected so that the forward directions are opposite to each other as illustrated.
【００５５】従って、電力回収用コンデンサの電荷が、
期間ｂ，ｆの場合、第１の充放電回路を経由して、パネ
ル容量ＣＰとの間を流れるのが、第２の充放電回路の方
に逆電流が流れることはない。同様に、期間ｃ，ｅの場
合、第２の充放電回路を経由して、パネル容量ＣＰとの
間を流れるのが、第１の充放電回路の方に逆電流が流れ
ることはない。Therefore, the charge of the power recovery capacitor is
In the periods b and f, the reverse current does not flow in the second charge / discharge circuit though the current flows between the panel capacitance CP and the first charge / discharge circuit. Similarly, in the periods c and e, the reverse current does not flow in the first charge / discharge circuit though the current flows between the panel capacitance CP and the second charge / discharge circuit.
【００５６】すなわち、ダイオードが挿入されている
と、ＶＦによる抵抗分の電力損失が効いてくる。この抵
抗分は、順方向降下電圧ＶＦをダイオードを流れる実効
値電流値で除した値に等しい。特にプラズマディスプレ
イパネルの駆動回路では、維持パルス電圧が、２００Ｖ
近く必要なことや、パネル前面に維持パネル電圧よりも
さらに大きな電圧を印加することにより、パネル前面を
一度強制的に放電させ、書き込み放電をしやすくするた
めのプライミングパルスを用いることがある。従って、
この部品に挿入するダイオードはプライミングパルス印
加電圧より、高い４００Ｖ耐圧品が必要である。That is, when the diode is inserted, the power loss due to the resistance due to VF is effective. This resistance is equal to the forward drop voltage VF divided by the effective current value flowing through the diode. Especially, in the driving circuit of the plasma display panel, the sustain pulse voltage is 200V.
There is a case where a priming pulse is used for facilitating the writing discharge by forcibly discharging the front surface of the panel by applying a voltage higher than the sustain panel voltage to the front surface of the panel, which is necessary near. Therefore,
The diode to be inserted in this component needs to have a withstand voltage of 400 V, which is higher than the priming pulse applied voltage.
【００５７】一般に耐圧が高いダイオードほど、順方向
降下は大きい傾向があり、４００Ｖ耐圧のものでは少な
くとも１．０Ｖ以上あり、例えば１Ａｒ．ｍ．ｓ．の実
効値電流が流れるとすれば、１Ωの抵抗値があることに
なる。また、ダイオードの順方向降下による抵抗値はＦ
ＥＴスイッチ１２，１３，１４，１５のオン抵抗値と同
程度であり、コイル１０，１１自身の内部抵抗値よりは
はるかに大きいため、抵抗分Ｒが大きくなり回収率の低
下を招くことになる。Generally, a diode having a higher breakdown voltage tends to have a larger forward drop, and a diode having a breakdown voltage of 400 V has at least 1.0 V or more. m. s. If an effective value current of 1 flows, there is a resistance value of 1Ω. The resistance value due to the forward drop of the diode is F
Since the on-resistance values of the ET switches 12, 13, 14, 15 are substantially the same as the on-resistance values of the ET switches 12, 13, 14, 15 and much larger than the internal resistance values of the coils 10, 11 themselves, the resistance component R becomes large and the recovery rate decreases. .
【００５８】また、図６に示す従来例の回路では、パネ
ルの両電極の部品点数でみると、ダイオード４個全てが
不必要であり、電力回収用コンデンサも１個ですみ、部
品点数の削減が可能であり、ＦＥＴスイッチの入力端子
に加える信号数を、ロジック信号でみると、８個から、
６個に削減できる。従って、駆動回路を少ない部品点数
で実現できるという効果もある。Further, in the conventional circuit shown in FIG. 6, in terms of the number of parts of both electrodes of the panel, all four diodes are unnecessary, and only one power recovery capacitor is required, reducing the number of parts. The number of signals applied to the input terminal of the FET switch can be calculated from 8 logic signals,
It can be reduced to six. Therefore, there is an effect that the drive circuit can be realized with a small number of parts.
【００５９】[0059]
【発明の効果】以上説明したように、本発明のプラズマ
ディスプレイパネルの駆動回路は、パネル容量の両端に
直列に接続される２つの充放電回路部と、４個のスイッ
チを備えた電圧クランプとを有し、パネル容量および２
つの充放電回路部で直列共振回路を形成することによ
り、維持パルスを印加した時に、パネル容量の充放電に
おいて発光に寄与しない無効電力の発生を抑え、パネル
容量とコイルの共振現象で誘起された電圧による電荷を
回収コンデンサに蓄積し、次の維持パルスのサイクルで
パネル容量の再充電に使用することができるので、パネ
ルの充放電に要する消費電力を低減できるという効果が
ある。すなわち無効電力を削減することができる。As described above, the driving circuit of the plasma display panel according to the present invention comprises two charging / discharging circuit parts connected in series at both ends of the panel capacitance, and a voltage clamp having four switches. With a panel capacity and 2
By forming a series resonance circuit with two charging / discharging circuit parts, when a sustain pulse is applied, the generation of reactive power that does not contribute to light emission during charging / discharging of the panel capacitance is suppressed, and it is induced by the resonance phenomenon of the panel capacitance and the coil. Since the charge due to the voltage is stored in the recovery capacitor and can be used for recharging the panel capacitance in the next sustain pulse cycle, there is an effect that the power consumption required for charging and discharging the panel can be reduced. That is, the reactive power can be reduced.
【００６０】また、本発明の駆動回路は、パネルの走査
電極および維持電極それぞれに共通駆動とし、スイッチ
駆動のための入力駆動パルスの数が６個でよいため、少
ない部品点数で実現できるという効果もある。In addition, the drive circuit of the present invention is commonly driven by the scan electrodes and the sustain electrodes of the panel, and the number of input drive pulses for driving the switches is only six. Therefore, the number of parts can be reduced. There is also.
【００６１】加えて、充放電回路の経路に消費電力損失
の大きいダイオードがないので、回路全体の消費電力も
少なくてすむという効果もある。In addition, since there is no diode with a large power consumption loss in the path of the charge / discharge circuit, there is an effect that the power consumption of the entire circuit can be reduced.
【図１】本発明の一実施の形態を示すプラズマディスプ
レイパネルの駆動回路図である。FIG. 1 is a drive circuit diagram of a plasma display panel showing an embodiment of the present invention.
【図２】図１におけるパネルの駆動電圧および駆動電流
波形特性図である。FIG. 2 is a drive voltage and drive current waveform characteristic diagram of the panel in FIG.
【図３】図２における各期間の回収動作説明図である。FIG. 3 is an explanatory diagram of a collecting operation in each period in FIG.
【図４】従来の一実施例を説明するためのプラズマディ
スプレイパネルの平面およびＸ−Ｘ′線断面を示した図
である。FIG. 4 is a view showing a plane and a cross section taken along line XX ′ of a plasma display panel for explaining a conventional example.
【図５】図４の電極配置に着目したプラズマディスプレ
イパネルの平面図である。FIG. 5 is a plan view of a plasma display panel focusing on the electrode arrangement of FIG.
【図６】従来の一実施例を示すプラズマディスプレイパ
ネルの駆動回路図である。FIG. 6 is a drive circuit diagram of a plasma display panel showing a conventional example.
【図７】従来のパネル駆動を説明するためのパルス波形
図である。FIG. 7 is a pulse waveform diagram for explaining conventional panel driving.
１ パネル ２ 第１の充放電回路部 ３ 第２の充放電回路部 ４ 電圧クランプ部 ５ 電力回収用コンデンサ ６，７，８，９，１２，１３，１４，１５ ＦＥＴス
イッチ １０，１１ コイル ４１，４２，４３，４４ ＦＥＴ寄生ダイオード ＩＮ１〜ＩＮ８ 入力端子 ＣＰ パネル容量1 Panel 2 First Charge / Discharge Circuit Section 3 Second Charge / Discharge Circuit Section 4 Voltage Clamp Section 5 Power Recovery Capacitor 6,7,8,9,12,13,14,15 FET Switch 10,11 Coil 41, 42,43,44 FET parasitic diode IN1 to IN8 input terminal CP panel capacitance
Claims (5)
生すると共に、前記表示パネルの一方の電極に接続さ
れ、前記表示パネルの電極間静電容量に等価的に接続さ
れ、前記表示パネルの電極間静電容量の充放電時に共振
電流を発生させる第１の充放電回路部と、前記表示パネ
ルの他方の電極に接続され、前記表示パネルの電極間静
電容量に等価的に接続され、前記表示パネルの電極間静
電容量の充放電時に共振電流を発生させる第２の充放電
回路部と、前記表示パネルの一方の電極および他方の電
極に接続されて前記表示パネルの電極を一定の電位に保
つ電圧クランプ部と、共通接続された前記第１の充放電
回路部の他端と前記第２の充放電回路部の他端に接続さ
れる電力回収用のコンデンサとからなることを特徴とす
る表示パネルの駆動回路。1. An electrode of the display panel, which generates a pulse to be applied to an electrode of the display panel, is connected to one electrode of the display panel, and is equivalently connected to an inter-electrode capacitance of the display panel. A first charging / discharging circuit portion that generates a resonance current when charging / discharging the inter-capacitance, and is connected to the other electrode of the display panel and is equivalently connected to the inter-electrode capacitance of the display panel, A second charging / discharging circuit unit that generates a resonance current when charging / discharging the inter-electrode capacitance of the display panel, and one electrode and the other electrode of the display panel to connect the electrodes of the display panel to a constant potential. And a capacitor for power recovery connected to the other end of the first charge / discharge circuit unit and the other end of the second charge / discharge circuit unit that are commonly connected. Driving time of display panel Road.
ネルのパネル容量の充放電時に共振電流を発生するコイ
ルと、それぞれパネル容量の充電時および放電時におけ
る共振電流を独立に制御するＮチャンネルのＦＥＴスイ
ッチおよびＰチャンネルのＦＥＴスイッチとからなるこ
とを特徴とする請求項１記載の表示パネルの駆動回路。2. The first charging / discharging circuit section independently controls a coil that generates a resonance current when the panel capacitance of the display panel is charged and discharged, and a resonance current when the panel capacitance is charged and discharged, respectively. 2. The display panel drive circuit according to claim 1, comprising an N-channel FET switch and a P-channel FET switch.
ネルのパネル容量の充放電時に共振電流を発生するコイ
ルと、それぞれパネル容量の充電時および放電時におけ
る共振電流のそれぞれを独立に制御するＮチャンネルの
ＦＥＴスイッチおよびＰチャンネルのＦＥＴスイッチと
からなることを特徴とする請求項２記載の表示パネルの
駆動回路。3. The second charging / discharging circuit section independently supplies a coil that generates a resonance current when the panel capacitance of the display panel is charged and discharged, and a resonance current when the panel capacitance is charged and discharged, respectively. 3. The display panel driving circuit according to claim 2, comprising an N-channel FET switch and a P-channel FET switch for controlling.
のＦＥＴスイッチと前記第２の充放電回路部のＰチャン
ネルのＦＥＴスイッチとが共通接続されていてこれら端
子に前記電力回収用のコンデンサが共通接続されている
ことを特徴とする請求項３記載の表示パネルの駆動回
路。4. The P-channel FET switch of the first charge / discharge circuit section and the P-channel FET switch of the second charge / discharge circuit section are commonly connected, and the power recovery capacitor is connected to these terminals. 4. The display panel drive circuit according to claim 3, wherein the display circuits are commonly connected.
パネル容量の両端と電源線および接地線間に接続される
第１および第２のＮチャンネルのＦＥＴスイッチ並びに
第１および第２のＰチャンネルのＦＥＴスイッチを有し
て構成されていることを特徴とする請求項１乃至４記載
の表示パネルの駆動回路。5. The first and second N-channel FET switches, and the first and second P-channel FET switches, wherein the voltage clamp section is connected between both ends of the panel capacitance of the display panel and a power supply line and a ground line. 5. The display panel drive circuit according to claim 1, wherein the display panel drive circuit comprises an FET switch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21841695A JP2751951B2 (en) | 1995-08-28 | 1995-08-28 | Display panel drive circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21841695A JP2751951B2 (en) | 1995-08-28 | 1995-08-28 | Display panel drive circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0962226A true JPH0962226A (en) | 1997-03-07 |
| JP2751951B2 JP2751951B2 (en) | 1998-05-18 |
Family
ID=16719577
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21841695A Expired - Fee Related JP2751951B2 (en) | 1995-08-28 | 1995-08-28 | Display panel drive circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2751951B2 (en) |
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| US6046614A (en) * | 1997-03-31 | 2000-04-04 | Nec Corporation | Drive circuit having a power recovery system |
| US6072447A (en) * | 1997-11-28 | 2000-06-06 | Nec Corporation | Plasma display panel drive circuit provided with series resonant circuits |
| KR20010098117A (en) * | 2000-04-28 | 2001-11-08 | 김순택 | Apparatus for driving plasma display panel |
| JP2002116731A (en) * | 2000-09-26 | 2002-04-19 | Samsung Electronics Co Ltd | Sustained discharge circuit for ac plasma display panel |
| EP1215649A2 (en) * | 2000-12-12 | 2002-06-19 | Philips Corporate Intellectual Property GmbH | Plasma display panel |
| KR20030003564A (en) * | 2001-07-03 | 2003-01-10 | 주식회사 유피디 | Energy recovery circuit of sustain driver in AC-type plasma display panel |
| KR100377404B1 (en) * | 2001-03-16 | 2003-03-26 | 삼성에스디아이 주식회사 | Apparatus for driving plasma display panel, which comprising energy recovery circuit |
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|---|---|---|---|---|
| US6046614A (en) * | 1997-03-31 | 2000-04-04 | Nec Corporation | Drive circuit having a power recovery system |
| US6072447A (en) * | 1997-11-28 | 2000-06-06 | Nec Corporation | Plasma display panel drive circuit provided with series resonant circuits |
| KR100548240B1 (en) * | 1999-06-12 | 2006-02-02 | 엘지전자 주식회사 | Energy Recovering Circuit Of Multistep-Type |
| KR100462778B1 (en) * | 2000-02-09 | 2004-12-20 | 삼성에스디아이 주식회사 | Circuit for driving a plasma display panel |
| KR20010098117A (en) * | 2000-04-28 | 2001-11-08 | 김순택 | Apparatus for driving plasma display panel |
| JP2002116731A (en) * | 2000-09-26 | 2002-04-19 | Samsung Electronics Co Ltd | Sustained discharge circuit for ac plasma display panel |
| EP1215649A2 (en) * | 2000-12-12 | 2002-06-19 | Philips Corporate Intellectual Property GmbH | Plasma display panel |
| EP1215649A3 (en) * | 2000-12-12 | 2002-11-27 | Philips Corporate Intellectual Property GmbH | Plasma display panel |
| US6753653B2 (en) | 2000-12-12 | 2004-06-22 | Koninklijke Philips Electronics N.V. | Plasma display screen |
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| KR100432891B1 (en) * | 2001-08-22 | 2004-05-24 | 주식회사 유피디 | Sustain driver in AC-type plasma display panel having energy recovery circuit |
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| JP2751951B2 (en) | 1998-05-18 |
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