JPH0961478A - Electric charge detection circuit - Google Patents
Electric charge detection circuitInfo
- Publication number
- JPH0961478A JPH0961478A JP21176295A JP21176295A JPH0961478A JP H0961478 A JPH0961478 A JP H0961478A JP 21176295 A JP21176295 A JP 21176295A JP 21176295 A JP21176295 A JP 21176295A JP H0961478 A JPH0961478 A JP H0961478A
- Authority
- JP
- Japan
- Prior art keywords
- differential amplifier
- capacitance
- electric charge
- switching element
- detection circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Measurement Of Current Or Voltage (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は信号電荷の検出を行
う電荷検出回路に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge detection circuit for detecting signal charges.
【0002】[0002]
【従来の技術】光センサは光強度の計測に、またロボッ
ト、各種オートメーションシステムにおける位置センサ
として、また情報通信、情報処理における画像情報の読
み取りなどに広く用いられている。特に画像情報処理の
技術、能力の進歩した今日、高性能な画像情報の入力装
置としてのイメージセンサの進歩が強く望まれている。
ファクシミリ、ワードプロセッサ、電子ファイルシステ
ムなどは画像入力装置を必要とする代表的な装置であ
る。2. Description of the Related Art Optical sensors are widely used for measuring light intensity, as position sensors in robots and various automation systems, and for reading image information in information communication and information processing. In particular, with the recent advances in image information processing technology and capabilities, there is a strong demand for advances in image sensors as high-performance image information input devices.
Facsimile machines, word processors, electronic file systems, etc. are typical devices that require an image input device.
【0003】このような入力装置としては、ビデオカメ
ラのような二次元情報を取り出すものと、ラインセンサ
を利用して画像をスキャンして読み出すイメージスキャ
ナーが考えられるが、通常十分な解像力(画素数)を得
るためにラインセンサを使用したイメージスキャナが使
用されている。ラインセンサとしては、結晶シリコンを
使用した電荷結合素子(CCD)が代表的であるが、素
子の大きさに限界があって、大きな面積の画像を読み取
るには縮小光学系を使用するか、素子を多数高精度に並
べる必要がある。それに対して硫化カドミウム、アモル
ファスシリコンを光導電面としたセンサは比較的大きな
面積が可能であり、ロッドレンズアレイを併用した等倍
密着型のラインセンサが一部実用化されている。As such an input device, a device for taking out two-dimensional information such as a video camera and an image scanner for scanning and reading an image by using a line sensor can be considered, but usually a sufficient resolving power (number of pixels) is used. Image scanner using a line sensor is used to obtain a). As a line sensor, a charge coupled device (CCD) using crystalline silicon is typical, but there is a limit to the size of the device, and a reduction optical system is used to read an image of a large area. It is necessary to arrange a large number of high precision. On the other hand, a sensor having a photoconductive surface made of cadmium sulfide or amorphous silicon can have a relatively large area, and a unit-size contact type line sensor that also uses a rod lens array has been put into practical use.
【0004】このような画像読み取り装置において、各
画素の出力電流は一定時間、容量に蓄積し、蓄積された
電荷を電荷検出回路で検出する方法が一般的である。図
3は従来用いられている電荷検出回路の一例である。ス
イッチング素子S1がOFF状態の間、C1に蓄積され
た信号電荷Qは、S1をON状態にすることによって検
出回路に流れ、差動増幅器3(通常、オペアンプが使用
される。)の出力端子に次式(1)で表わされる電圧V
outlが発生する。この後、出力端子の電圧は式
(2)で表わされる時定数t1で減少する。In such an image reading apparatus, a method is generally used in which the output current of each pixel is accumulated in a capacitor for a fixed time and the accumulated charge is detected by a charge detection circuit. FIG. 3 shows an example of a charge detection circuit used conventionally. While the switching element S1 is in the OFF state, the signal charge Q accumulated in C1 flows into the detection circuit by turning S1 in the ON state, and is output to the output terminal of the differential amplifier 3 (usually an operational amplifier is used). The voltage V expressed by the following equation (1)
outl occurs. After that, the voltage at the output terminal decreases at the time constant t1 represented by the equation (2).
【0005】[0005]
【数1】Vout1=Q/C3 (1) t1=R3×C3 (2)## EQU1 ## Vout1 = Q / C3 (1) t1 = R3 × C3 (2)
【0006】[0006]
【発明が解決しようとする課題】しかしながら、スイッ
チング素子(S1)の出力容量や配線容量によって差動
増幅器のマイナス端子と一定電位の間に容量(C4)が
存在するため、出力波形の立ち上がりが遅くなり信号電
荷に対する感度が低下する、出力波形が発振する、など
の問題があった。However, since the capacitance (C4) exists between the negative terminal of the differential amplifier and the constant potential due to the output capacitance and wiring capacitance of the switching element (S1), the output waveform rises slowly. However, there are problems such as a decrease in sensitivity to signal charges and oscillation of the output waveform.
【0007】[0007]
【課題を解決するための手段】本発明者らは上記課題に
ついて鋭意検討した結果、電荷検出回路を特定の構成に
することによって、容量C4の影響を除き、信号電荷に
対する感度を上げ、S/N比を向上させることができる
ことを見いだし本発明を完成した。DISCLOSURE OF THE INVENTION As a result of intensive studies on the above-mentioned problems, the inventors of the present invention have eliminated the influence of the capacitance C4 to increase the sensitivity to signal charges by changing the S / The present invention has been completed by finding that the N ratio can be improved.
【0008】即ち、本発明の要旨は、信号電荷を蓄積す
る第一の容量を、第一のスイッチング素子を介して第一
の差動増幅器のマイナス端子と接続し、第一の差動増幅
器の出力端子と第一の差動増幅器のマイナス端子を第一
の抵抗で接続し、第一の差動増幅器の出力端子と第一の
差動増幅器のプラス端子とを第二の抵抗で接続し、第一
の差動増幅器のプラス端子と第二の差動増幅器のマイナ
ス端子とを接続し、第二の差動増幅器のプラス端子を実
質的に一定電位に保ち、第二の差動増幅器のマイナス端
子と一定電位の間を第二の容量で接続し、第二の差動増
幅器の出力端子と第二の差動増幅器のマイナス端子を第
三の容量で接続し、第二の差動増幅器の出力端子と第二
の差動増幅器のマイナス端子を第三の抵抗又は第二のス
イッチング素子で接続したことを特徴とした電荷検出回
路に存する。That is, the gist of the present invention is to connect the first capacitance for accumulating signal charges to the negative terminal of the first differential amplifier via the first switching element, The output terminal and the negative terminal of the first differential amplifier are connected by a first resistor, and the output terminal of the first differential amplifier and the positive terminal of the first differential amplifier are connected by a second resistor, The positive terminal of the first differential amplifier and the negative terminal of the second differential amplifier are connected to keep the positive terminal of the second differential amplifier at a substantially constant potential, and the negative terminal of the second differential amplifier is connected. The second capacitance is connected between the terminal and the constant potential by connecting the output terminal of the second differential amplifier and the negative terminal of the second differential amplifier by the third capacitance. Use the third resistor or the second switching element to connect the output terminal and the negative terminal of the second differential amplifier. Consists in the charge detecting circuit, characterized in that connection was.
【0009】[0009]
【発明の実施の態様】この発明の電荷検出回路では、第
一のスイッチング素子をON状態にした時に流れる電流
を、第一の差動増幅器、第四の容量、第一の抵抗、第二
の抵抗、第二の容量で構成される電流−電流変換回路を
介して、第二の差動増幅器、第三の容量、第三の抵抗又
は第二のスイッチング素子で構成される電流−電圧変換
回路に入力しているため、第四の容量の電流−電圧変換
回路への影響を除くことができる。BEST MODE FOR CARRYING OUT THE INVENTION In the charge detection circuit of the present invention, the current flowing when the first switching element is turned on is supplied to the first differential amplifier, the fourth capacitance, the first resistance, and the second differential amplifier. A current-voltage conversion circuit composed of a second differential amplifier, a third capacitor, a third resistor or a second switching element via a current-current conversion circuit composed of a resistor and a second capacitor. Since it is input to, it is possible to eliminate the influence of the fourth capacitance on the current-voltage conversion circuit.
【0010】[0010]
【実施例】本発明の電荷検出回路の実施例を図1に示
す。C4はスイッチング素子S1の出力容量である。信
号電荷は容量C1にスイッチング素子S1がOFF状態
の間、蓄積される。この電荷Qはスイッチング素子 S
1をON状態にすることによって電荷検出回路に流れ、
第二の差動増幅器2の出力端子に電圧Vout2が発生
する。FIG. 1 shows an embodiment of the charge detection circuit of the present invention. C4 is the output capacitance of the switching element S1. The signal charge is accumulated in the capacitor C1 while the switching element S1 is in the OFF state. This charge Q is a switching element S
When 1 is turned on, it flows to the charge detection circuit,
The voltage Vout2 is generated at the output terminal of the second differential amplifier 2.
【0011】[0011]
【数2】 Vout2=(Q/C3)×(R1/R2) (3)## EQU00002 ## Vout2 = (Q / C3) .times. (R1 / R2) (3)
【0012】Vout2はQに比例する。またR1をR
2よりも大きな値にすることが好ましく、このことによ
って回路出力のQに対する感度を上げることが可能であ
る。この後、差動増幅器2の出力端子の電圧は時定数t
2で減少する。Vout2 is proportional to Q. R1 to R
A value larger than 2 is preferable, which makes it possible to increase the sensitivity of the circuit output to Q. After this, the voltage at the output terminal of the differential amplifier 2 has a time constant t.
Decrease by 2.
【0013】[0013]
【数3】t2=R3×C3 (4)## EQU00003 ## t2 = R3.times.C3 (4)
【0014】ここで、R1,C4,R2,C2の値は下
式を満足することが望ましい。Here, it is desirable that the values of R1, C4, R2 and C2 satisfy the following equation.
【0015】[0015]
【数4】 (R2×C2)×0.8≦R1×C4≦(R2×C2)×1.2 (5)(R2 × C2) × 0.8 ≦ R1 × C4 ≦ (R2 × C2) × 1.2 (5)
【0016】また図2に示すように図1におけるR3の
代わりにスイッチング素子S2を用いてもよい。この場
合、差動増幅器2の出力端子の電圧はS2がOFF状態
の間Vout2に保たれ、S2をON状態にすることに
よってリセットされる。本発明において、さらには第
一、第二の差動増幅器1、2それぞれについてオフセッ
トを調整する回路等を付加してもよい。Further, as shown in FIG. 2, a switching element S2 may be used instead of R3 in FIG. In this case, the voltage at the output terminal of the differential amplifier 2 is maintained at Vout2 while S2 is in the OFF state, and is reset by turning S2 into the ON state. In the present invention, a circuit for adjusting the offset may be added to each of the first and second differential amplifiers 1 and 2.
【0017】[0017]
【発明の効果】以上の本発明の構成によって、スイッチ
ング素子の出力容量や配線容量の影響を受けない高感度
な電荷検出回路を提供することができる。With the above-described structure of the present invention, it is possible to provide a highly sensitive charge detection circuit which is not affected by the output capacitance of the switching element or the wiring capacitance.
【図面の簡単な説明】[Brief description of drawings]
【図1】本発明による電荷検出回路である。FIG. 1 is a charge detection circuit according to the present invention.
【図2】本発明による電荷検出回路である。FIG. 2 is a charge detection circuit according to the present invention.
【図3】従来使用されていた電荷検出回路の一例であ
る。FIG. 3 is an example of a charge detection circuit used conventionally.
1 第一の差動増幅器 2 第二の差動増幅器 3 従来例における差動増幅器 S1,S2 スイッチング素子 C1〜C4 容量 R1〜R3 抵抗 DESCRIPTION OF SYMBOLS 1 1st differential amplifier 2 2nd differential amplifier 3 Differential amplifier in a prior art example S1, S2 switching element C1-C4 capacitance R1-R3 resistance
フロントページの続き (72)発明者 松田 潔 神奈川県横浜市青葉区鴨志田町1000番地 三菱化学株式会社横浜総合研究所内Front page continuation (72) Inventor Kiyoshi Matsuda 1000 Kamoshida-cho, Aoba-ku, Yokohama-shi, Kanagawa Mitsubishi Chemical Corporation Yokohama Research Institute
Claims (3)
のスイッチング素子を介して第一の差動増幅器のマイナ
ス端子と接続し、第一の差動増幅器の出力端子と第一の
差動増幅器のマイナス端子を第一の抵抗で接続し、第一
の差動増幅器の出力端子と第一の差動増幅器のプラス端
子とを第二の抵抗で接続し、第一の差動増幅器のプラス
端子と第二の差動増幅器のマイナス端子とを接続し、第
二の差動増幅器のプラス端子を実質的に一定電位に保
ち、第二の差動増幅器のマイナス端子と一定電位の間を
第二の容量で接続し、第二の差動増幅器の出力端子と第
二の差動増幅器のマイナス端子を第三の容量で接続し、
第二の差動増幅器の出力端子と第二の差動増幅器のマイ
ナス端子を第三の抵抗又は第二のスイッチング素子で接
続したことを特徴とした電荷検出回路。1. A first capacitance for accumulating signal charges is connected to a negative terminal of a first differential amplifier via a first switching element, and an output terminal of the first differential amplifier and a first terminal of the first differential amplifier are connected. The negative terminal of the differential amplifier is connected with the first resistor, the output terminal of the first differential amplifier and the positive terminal of the first differential amplifier are connected with the second resistor, and the first differential amplifier The positive terminal of the second differential amplifier is connected to the negative terminal of the second differential amplifier, and the positive terminal of the second differential amplifier is maintained at a substantially constant potential. Is connected with the second capacitor, and the output terminal of the second differential amplifier and the negative terminal of the second differential amplifier are connected with the third capacitor,
A charge detection circuit characterized in that the output terminal of the second differential amplifier and the negative terminal of the second differential amplifier are connected by a third resistor or a second switching element.
定電位の間に存在する第四の容量と第一の抵抗の積)/
(第二の抵抗と第二の容量の積)が0.8から1.2の
間であることを特徴とする請求項1記載の電荷検出回
路。2. The product of the fourth resistance and the first resistance existing between the negative terminal of the first differential amplifier and the constant potential /
The charge detection circuit according to claim 1, wherein (the product of the second resistance and the second capacitance) is between 0.8 and 1.2.
大きいことを特徴とする請求項1又は2記載の電荷検出
回路。3. The charge detection circuit according to claim 1, wherein the first resistor has a resistance value larger than that of the second resistor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21176295A JPH0961478A (en) | 1995-08-21 | 1995-08-21 | Electric charge detection circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21176295A JPH0961478A (en) | 1995-08-21 | 1995-08-21 | Electric charge detection circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0961478A true JPH0961478A (en) | 1997-03-07 |
Family
ID=16611166
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21176295A Pending JPH0961478A (en) | 1995-08-21 | 1995-08-21 | Electric charge detection circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0961478A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2014162952A1 (en) * | 2013-04-02 | 2014-10-09 | 株式会社村田製作所 | Dummy load circuit and charge detection circuit |
CN113219275A (en) * | 2021-04-13 | 2021-08-06 | 西安子国微科技有限公司 | Brake residual pressure detection system |
-
1995
- 1995-08-21 JP JP21176295A patent/JPH0961478A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2014162952A1 (en) * | 2013-04-02 | 2014-10-09 | 株式会社村田製作所 | Dummy load circuit and charge detection circuit |
JP5930252B2 (en) * | 2013-04-02 | 2016-06-08 | 株式会社村田製作所 | Pseudo resistance circuit and charge detection circuit |
US9660592B2 (en) | 2013-04-02 | 2017-05-23 | Murata Manufacturing Co., Ltd. | Psuedo resistor circuit and charge amplifier |
CN113219275A (en) * | 2021-04-13 | 2021-08-06 | 西安子国微科技有限公司 | Brake residual pressure detection system |
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