JPH09232891A - Electric charge detection circuit - Google Patents

Electric charge detection circuit

Info

Publication number
JPH09232891A
JPH09232891A JP4144096A JP4144096A JPH09232891A JP H09232891 A JPH09232891 A JP H09232891A JP 4144096 A JP4144096 A JP 4144096A JP 4144096 A JP4144096 A JP 4144096A JP H09232891 A JPH09232891 A JP H09232891A
Authority
JP
Japan
Prior art keywords
differential amplifier
terminal
detection circuit
charge detection
output terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4144096A
Other languages
Japanese (ja)
Inventor
Nobuyoshi Miyazaki
信義 宮崎
Hiroshi Ishihara
啓 石原
Atsushi Tamaki
淳 玉木
Kiyoshi Matsuda
潔 松田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Chemical Corp
Original Assignee
Mitsubishi Chemical Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Chemical Corp filed Critical Mitsubishi Chemical Corp
Priority to JP4144096A priority Critical patent/JPH09232891A/en
Publication of JPH09232891A publication Critical patent/JPH09232891A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide an electric charge detection circuit with high sensitivity. SOLUTION: First capacity C1 storing signal electric charge is connected with the plus terminal of a first differential amplifier 1 and the minus terminal of a second differential amplifier 2 via first switching element S1, the output terminal of the first differential amplifier 1 and the plus terminal of the first differential amplifier are connected by a first resistor R1, the output terminal of the first differential amplifier 1 and the minus terminal of the first differential amplifier 1 by a second resistor R2, and the minus terminal of the first differential amplifier 1 and constant potential are connected by the second capacitor C2. The plus terminal of the second differential amplifier 2 is kept at a constant potential, the output terminal of the second differential amplifier 2 and the minus terminal of the second differential amplifier 2 are connected by the third capacitor C3, and the output terminal of the second differential amplifier 2 and the minus terminal of the second differential amplifier 2 are connected by a third resistor R3 or a second switching element.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は信号電荷の検出を行
う電荷検出回路に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge detection circuit for detecting signal charges.

【0002】[0002]

【従来の技術】光センサは光強度の計測に、またロボッ
ト、各種オートメーションシステムにおける位置センサ
として、また情報通信、情報処理における画像情報の読
み取りなどに広く用いられている。特に画像情報処理の
技術、能力の進歩した今日、高性能な画像情報の入力装
置としてのイメージセンサの進歩が強く望まれている。
ファクシミリ、ワードプロセッサ、電子ファイリングシ
ステムなどは画像入力装置を必要とする代表的な装置で
ある。
2. Description of the Related Art Optical sensors are widely used for measuring light intensity, as position sensors in robots and various automation systems, and for reading image information in information communication and information processing. In particular, with the recent advances in image information processing technology and capabilities, there is a strong demand for advances in image sensors as high-performance image information input devices.
Facsimile machines, word processors, electronic filing systems, etc. are typical devices that require an image input device.

【0003】このような入力装置としては、ビデオカメ
ラのような二次元情報を取り出すものと、ラインセンサ
を利用して画像をスキャンして読み出すイメージスキャ
ナーが考えられるが、通常十分な解像力(画素数)を得
るためにラインセンサを使用したイメージスキャナが使
用されている。ラインセンサとしては、結晶シリコンを
使用した電荷結合素子(CCD)が代表的であるが、素
子の大きさに限界があって、大きな面積の画像を読み取
るには縮小光学系を使用するか、素子を多数、高精度に
並べる必要がある。それに対して硫化カドミウム、アモ
ルファスシリコンを光導電面としたセンサは比較的大き
な面積が可能であり、ロッドレンズアレイを併用した等
倍密着型のラインセンサが一部実用化されている。
As such an input device, a device for taking out two-dimensional information such as a video camera and an image scanner for scanning and reading an image by using a line sensor can be considered, but usually a sufficient resolving power (number of pixels) is used. Image scanner using a line sensor is used to obtain a). As a line sensor, a charge coupled device (CCD) using crystalline silicon is typical, but there is a limit to the size of the device, and a reduction optical system is used to read an image of a large area. It is necessary to arrange a large number of lines with high accuracy. On the other hand, a sensor having a photoconductive surface made of cadmium sulfide or amorphous silicon can have a relatively large area, and a unit-size contact type line sensor that also uses a rod lens array has been put into practical use.

【0004】このような画像読み取り装置において、各
画素の出力電流は一定時間、容量に蓄積し、蓄積された
電荷を電荷検出回路で検出する方法が一般的である。図
5は従来用いられている電荷検出回路の一例である。ス
イッチング素子S1がOFF状態の間、C1に蓄積され
た信号電荷QはS1をON状態にすることによって検出
回路に流れ、差動増幅器3(通常、オペアンプが使用さ
れる)の出力端子に次式(1)で表される電圧Vout
が発生する。この後、出力端子の電圧は式(2)で表さ
れる時定数t1で減少する。
In such an image reading apparatus, a method is generally used in which the output current of each pixel is accumulated in a capacitor for a fixed time and the accumulated charge is detected by a charge detection circuit. FIG. 5 shows an example of a charge detection circuit used conventionally. While the switching element S1 is in the OFF state, the signal charge Q accumulated in C1 flows into the detection circuit by turning the S1 in the ON state, and the following expression is applied to the output terminal of the differential amplifier 3 (usually an operational amplifier is used). The voltage Vout represented by (1)
Occurs. After that, the voltage at the output terminal decreases at the time constant t1 represented by the equation (2).

【0005】[0005]

【数1】Vout=Q/C3 (1) t1=R3×C3 (2)## EQU1 ## Vout = Q / C3 (1) t1 = R3 × C3 (2)

【0006】[0006]

【発明が解決しようとする課題】しかしながら、スイッ
チング素子(S1)の出力容量や配線容量によって差動
増幅器のマイナス端子と一定電位の間に大きな容量(C
4)が存在するため、出力波形の立ち上がりが遅くな
り、信号電荷に対する感度が低下する、出力波形が発振
するなどの問題があった。
However, due to the output capacitance and wiring capacitance of the switching element (S1), a large capacitance (C
4) is present, there are problems that the rising of the output waveform is delayed, the sensitivity to signal charges is lowered, the output waveform oscillates, and the like.

【0007】[0007]

【課題を解決するための手段】本発明者らは上記課題に
ついて鋭意検討した結果、電荷検出回路を特定の構成と
することによって、容量C4の影響を除き、信号電荷に
対する感度を上げ、S/N比を向上させることができる
ことを見いだし本発明を完成した。
DISCLOSURE OF THE INVENTION As a result of intensive studies on the above problems, the inventors of the present invention have determined that the charge detection circuit has a specific configuration to eliminate the influence of the capacitance C4 and increase the sensitivity to signal charges. The present invention has been completed by finding that the N ratio can be improved.

【0008】即ち、本発明の第一の態様は、信号電荷を
蓄積する第一の容量を、第一のスイッチング素子を介し
て、第一の差動増幅器のプラス端子及び第二の差動増幅
器のマイナス端子と接続し、第一の差動増幅器の出力端
子と第一の差動増幅器のプラス端子とを第一の抵抗で接
続し、第一の差動増幅器の出力端子と第一の差動増幅器
のマイナス端子を第二の抵抗で接続し、第一の差動増幅
器のマイナス端子と一定電位の間を第二の容量で接続
し、第二の差動増幅器のプラス端子を一定電位に保ち、
第二の差動増幅器の出力端子と第二の差動増幅器のマイ
ナス端子を第三の容量で接続し、第二の差動増幅器の出
力端子と第二の差動増幅器のマイナス端子を第三の抵抗
又は第二スイッチング素子で接続したことを特徴とした
電荷検出回路である。
That is, according to the first aspect of the present invention, the first capacitance for accumulating the signal charge is connected to the plus terminal of the first differential amplifier and the second differential amplifier via the first switching element. Connected to the negative terminal of the first differential amplifier and the positive terminal of the first differential amplifier with a first resistor, and the output terminal of the first differential amplifier and the first difference The negative terminal of the dynamic amplifier is connected with a second resistor, the negative terminal of the first differential amplifier is connected with a constant potential with a second capacitor, and the positive terminal of the second differential amplifier is kept at a constant potential. Keep
The output terminal of the second differential amplifier and the negative terminal of the second differential amplifier are connected by the third capacitor, and the output terminal of the second differential amplifier and the negative terminal of the second differential amplifier are connected to the third terminal. Is a charge detection circuit characterized by being connected by the resistor or the second switching element.

【0009】また本発明の第二の態様は、信号電荷を蓄
積する第一の容量を、第一のスイッチング素子を介し
て、第一の差動増幅器のプラス端子及び第二の差動増幅
器のマイナス端子と接続し、第一の差動増幅器の出力端
子と第一の差動増幅器のプラス端子とを第二の容量で接
続し、第一の差動増幅器の出力端子と第一の差動増幅器
のマイナス端子を第一の抵抗で接続し、第一の差動増幅
器のマイナス端子と一定電位の間を第二の抵抗で接続
し、第二の差動増幅器のプラス端子を一定電位に保ち、
第二の差動増幅器の出力端子と第二の差動増幅器のマイ
ナス端子を第三の容量で接続し、第二の差動増幅器の出
力端子と第二の差動増幅器のマイナス端子を第三の抵抗
又は第二スイッチング素子で接続したことを特徴とした
電荷検出回路である。
According to a second aspect of the present invention, the first capacitance for accumulating signal charges is connected to the positive terminal of the first differential amplifier and the second differential amplifier via the first switching element. Connected to the negative terminal, the output terminal of the first differential amplifier and the positive terminal of the first differential amplifier are connected by the second capacitor, and the output terminal of the first differential amplifier and the first differential The negative terminal of the amplifier is connected with the first resistance, the negative terminal of the first differential amplifier is connected with the constant potential with the second resistance, and the positive terminal of the second differential amplifier is kept at the constant potential. ,
The output terminal of the second differential amplifier and the negative terminal of the second differential amplifier are connected by the third capacitor, and the output terminal of the second differential amplifier and the negative terminal of the second differential amplifier are connected to the third terminal. Is a charge detection circuit characterized by being connected by the resistor or the second switching element.

【0010】[0010]

【発明の実施の態様】この発明の電荷検出回路では、第
二の差動増幅器、第三の容量、第三の抵抗又は第二スイ
ッチング素子で構成される電流−電圧変換回路と並列
に、第一の差動増幅器、第一の抵抗、第二の抵抗、第二
の容量で構成される回路を接続しているため、第一のス
イッチング素子の出力容量である第四の容量の電流−電
圧変換回路への影響を除くことができる。
BEST MODE FOR CARRYING OUT THE INVENTION In a charge detection circuit of the present invention, a second differential amplifier, a third capacitor, a third resistor or a current-voltage conversion circuit composed of a second switching element is connected in parallel to a current-voltage conversion circuit. Since a circuit composed of one differential amplifier, a first resistor, a second resistor, and a second capacitor is connected, the current-voltage of the fourth capacitor, which is the output capacitance of the first switching element. The influence on the conversion circuit can be eliminated.

【0011】[0011]

【実施例】【Example】

(実施例1)本発明の電荷検出回路の実施例1を図1に
示す。図1中、S1はLC7938C(三洋電機(株)
製イメージセンサドライバ)中の1スイッチ、差動増幅
器1及び2はLM6365N(ナショナルセミコンダク
ター社製)を使用した。R1は18Ω抵抗、R2は10
Ω抵抗、R3は82KΩ抵抗、C1はスイッチS1の入
力容量、C2は330pFコンデンサ、C3は2pFコ
ンデンサ、C4は360pF程度(LC7938Cの出
力容量+配線容量+330pFコンデンサ:実際のイメ
ージセンサドライブ回路を想定して330pFコンデン
サを付加した)、の電流値は5×10-9アンペアであ
る。
(Embodiment 1) Embodiment 1 of the charge detection circuit of the present invention is shown in FIG. In FIG. 1, S1 is LC7938C (Sanyo Electric Co., Ltd.)
LM6365N (manufactured by National Semiconductor Co.) was used for 1 switch and differential amplifiers 1 and 2 in the image sensor driver manufactured by National Instruments. R1 is 18Ω resistance, R2 is 10
Ω resistance, R3 is 82 KΩ resistance, C1 is input capacitance of switch S1, C2 is 330 pF capacitor, C3 is 2 pF capacitor, C4 is about 360 pF (LC7938C output capacitance + wiring capacitance + 330 pF capacitor: Assuming an actual image sensor drive circuit) And a 330 pF capacitor was added), the current value was 5 × 10 -9 amps.

【0012】スイッチング素子S1はOFF状態の間、
信号電荷は容量C1に蓄積される。この電荷Qはスイッ
チング素子S1をON状態にすることによって電荷検出
回路に流れ、第二の差動増幅器2の出力端子にC4の影
響が無い場合、理論上式(1)で表される電圧Vout
が発生する。この後、差動増幅器2の出力端子の電圧は
式(2)で表される時定数t1で減少する。
While the switching element S1 is in the OFF state,
The signal charge is stored in the capacitor C1. This charge Q flows into the charge detection circuit by turning on the switching element S1, and when the output terminal of the second differential amplifier 2 is not affected by C4, the voltage Vout theoretically expressed by the equation (1) is obtained.
Occurs. After that, the voltage at the output terminal of the differential amplifier 2 decreases at the time constant t1 represented by the equation (2).

【0013】ここでR1、R2、C2、C4の値は下式
を満足することが望ましい。
Here, it is desirable that the values of R1, R2, C2 and C4 satisfy the following equation.

【0014】[0014]

【数2】 (R2×C2)×0.9≦R1×C4≦(R2×C2)×2.2 (3)(R2 × C2) × 0.9 ≦ R1 × C4 ≦ (R2 × C2) × 2.2 (3)

【0015】図1の回路に於ける出力波形を図6に示
す。図6中、スイッチS1がONする時間は図6中、0
(nsec)から800(nsec)の間で、この周期
(蓄積時間)は約1.6(msec)である。出力波形
は図6中、4に示す様に立ち上がりが急峻で、3V程度
の出力(ピーク値)が得られ、C4の影響を除くことが
できた。
The output waveform in the circuit of FIG. 1 is shown in FIG. In FIG. 6, the time when the switch S1 is turned on is 0 in FIG.
From (nsec) to 800 (nsec), this cycle (accumulation time) is about 1.6 (msec). The output waveform has a steep rise as shown by 4 in FIG. 6, and an output (peak value) of about 3 V was obtained, and the influence of C4 could be eliminated.

【0016】また図2に示すように図1におけるR3の
代わりにスイッチング素子S2を用いてもよい。この場
合、差動増幅器2の出力端子の電圧はS2がOFF状態
の間出力電圧は一定に保たれ、S2をON状態にするこ
とによってリセットされる。本発明において、さらに第
一、第二の差動増幅器1、2それぞれについてオフセッ
トを調整する回路等を付加してもよい。
Further, as shown in FIG. 2, a switching element S2 may be used instead of R3 in FIG. In this case, the voltage at the output terminal of the differential amplifier 2 is kept constant while S2 is in the OFF state, and is reset by turning S2 into the ON state. In the present invention, a circuit or the like for adjusting the offset may be added to each of the first and second differential amplifiers 1 and 2.

【0017】(実施例2)本発明の電荷検出回路の実施
例2を図3に示す。図3中、R1は10Ω抵抗、R2は
14Ω抵抗、C2は330pFコンデンサ、他は図1の
回路と同様である。回路動作も実施例1と同様である。
ここでR1、C4、R2、C2の値は下式を満足するこ
とが望ましい。
(Second Embodiment) FIG. 3 shows a second embodiment of the charge detection circuit of the present invention. In FIG. 3, R1 is a 10Ω resistor, R2 is a 14Ω resistor, C2 is a 330 pF capacitor, and others are the same as in the circuit of FIG. The circuit operation is the same as in the first embodiment.
Here, it is desirable that the values of R1, C4, R2, and C2 satisfy the following equation.

【0018】[0018]

【数3】 (R2×C4)×0.5≦R1×C2≦(R2×C4)×1.1 (4)(3) (R2 × C4) × 0.5 ≦ R1 × C2 ≦ (R2 × C4) × 1.1 (4)

【0019】図3の回路に於ける出力波形を図7に示
す。図7中、スイッチS1の動作は実施例1と同様であ
る。出力波形は図7中、5に示す様に立ち上がりが急峻
で、3V程度の出力(ピーク値)が得られ、C4の影響
を除くことができた。また実施例1と同様に図4に示す
ように図3におけるR3の代わりにスイッチング素子S
2を用いてもよい。さらに第一、第二の差動増幅器1、
2それぞれについてオフセットを調整する回路等を付加
してもよい。
The output waveform in the circuit of FIG. 3 is shown in FIG. In FIG. 7, the operation of the switch S1 is similar to that of the first embodiment. The output waveform had a steep rise as shown by 5 in FIG. 7, and an output (peak value) of about 3 V was obtained, and the influence of C4 could be eliminated. Further, as in the first embodiment, as shown in FIG. 4, instead of R3 in FIG.
2 may be used. Furthermore, the first and second differential amplifiers 1,
A circuit for adjusting the offset for each of the two may be added.

【0020】(比較例)従来使用されていた電荷検出回
路の実施例を図5に示す。図5中、差動増幅器3はLM
6365Nを使用した。他は図1の回路と同様である。
回路動作も実施例1と同様である。図5の回路に於ける
出力波形を図8に示す。図8中、スイッチS1の動作は
実施例1と同様である。出力波形は図8中、6に示す様
にC4の影響により立ち上がりが遅く、2.5V程度の
出力(ピーク値)である。
(Comparative Example) FIG. 5 shows an example of a charge detection circuit which has been conventionally used. In FIG. 5, the differential amplifier 3 is an LM
6365N was used. Others are the same as the circuit of FIG.
The circuit operation is the same as in the first embodiment. The output waveform in the circuit of FIG. 5 is shown in FIG. In FIG. 8, the operation of the switch S1 is similar to that of the first embodiment. As shown by 6 in FIG. 8, the output waveform has a slow rising due to the influence of C4 and is an output (peak value) of about 2.5V.

【0021】[0021]

【発明の効果】以上の本発明の構成によって、スイッチ
ング素子の出力容量や配線容量の影響を受けない高感度
な電荷検出回路を提供することができる。
With the above-described structure of the present invention, it is possible to provide a highly sensitive charge detection circuit which is not affected by the output capacitance of the switching element or the wiring capacitance.

【図面の簡単な説明】[Brief description of drawings]

【図1】請求項1記載の本発明による電荷検出回路の一
例を示す図である。
FIG. 1 is a diagram showing an example of a charge detection circuit according to the present invention according to claim 1;

【図2】請求項1記載の本発明による電荷検出回路の一
例を示す図である。
FIG. 2 is a diagram showing an example of a charge detection circuit according to the present invention according to claim 1;

【図3】請求項2記載の本発明による電荷検出回路の一
例を示す図である。
FIG. 3 is a diagram showing an example of a charge detection circuit according to the present invention as defined in claim 2;

【図4】請求項2記載の本発明による電荷検出回路の一
例を示す図である。
FIG. 4 is a diagram showing an example of a charge detection circuit according to the present invention as defined in claim 2;

【図5】従来使用されていた電荷検出回路の一例であ
る。
FIG. 5 is an example of a charge detection circuit that has been conventionally used.

【図6】本発明による電荷検出回路の出力波形である。FIG. 6 is an output waveform of the charge detection circuit according to the present invention.

【図7】本発明による電荷検出回路の出力波形である。FIG. 7 is an output waveform of the charge detection circuit according to the present invention.

【図8】従来使用されていた電荷検出回路の出力波形で
ある。
FIG. 8 is an output waveform of a charge detection circuit used conventionally.

【符号の説明】[Explanation of symbols]

1 第一の差動増幅器 2 第二の差動増幅器 3 従来例における差動増幅器 4〜6 出力波形 S1,S2 スイッチング素子 C1〜C4 容量 R1〜R3 抵抗 1 1st differential amplifier 2 2nd differential amplifier 3 Differential amplifier in a prior art example 4-6 Output waveform S1, S2 Switching element C1-C4 Capacitance R1-R3 Resistance

───────────────────────────────────────────────────── フロントページの続き (72)発明者 松田 潔 神奈川県横浜市青葉区鴨志田町1000番地 三菱化学株式会社横浜総合研究所内 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Kiyoshi Matsuda 1000 Kamoshida-cho, Aoba-ku, Yokohama-shi, Kanagawa Mitsubishi Chemical Corporation Yokohama Research Institute

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 信号電荷を蓄積する第一の容量を、第一
のスイッチング素子を介して、第一の差動増幅器のプラ
ス端子及び第二の差動増幅器のマイナス端子と接続し、
第一の差動増幅器の出力端子と第一の差動増幅器のプラ
ス端子とを第一の抵抗で接続し、第一の差動増幅器の出
力端子と第一の差動増幅器のマイナス端子を第二の抵抗
で接続し、第一の差動増幅器のマイナス端子と一定電位
の間を第二の容量で接続し、第二の差動増幅器のプラス
端子を一定電位に保ち、第二の差動増幅器の出力端子と
第二の差動増幅器のマイナス端子を第三の容量で接続
し、第二の差動増幅器の出力端子と第二の差動増幅器の
マイナス端子を第三の抵抗又は第二スイッチング素子で
接続したことを特徴とした電荷検出回路。
1. A first capacitance for accumulating a signal charge is connected to a positive terminal of a first differential amplifier and a negative terminal of a second differential amplifier via a first switching element,
The output terminal of the first differential amplifier and the positive terminal of the first differential amplifier are connected by a first resistor, and the output terminal of the first differential amplifier and the negative terminal of the first differential amplifier are connected to each other. The second differential amplifier connects between the negative terminal of the first differential amplifier and the constant potential with the second capacitor, and the positive terminal of the second differential amplifier is kept at the constant potential. The output terminal of the amplifier and the negative terminal of the second differential amplifier are connected by a third capacitor, and the output terminal of the second differential amplifier and the negative terminal of the second differential amplifier are connected by a third resistor or a second resistor. A charge detection circuit characterized by being connected by a switching element.
【請求項2】 信号電荷を蓄積する第一の容量を、第一
のスイッチング素子を介して、第一の差動増幅器のプラ
ス端子及び第二の差動増幅器のマイナス端子と接続し、
第一の差動増幅器の出力端子と第一の差動増幅器のプラ
ス端子とを第二の容量で接続し、第一の差動増幅器の出
力端子と第一の差動増幅器のマイナス端子を第一の抵抗
で接続し、第一の差動増幅器のマイナス端子と一定電位
の間を第二の抵抗で接続し、第二の差動増幅器のプラス
端子を一定電位に保ち、第二の差動増幅器の出力端子と
第二の差動増幅器のマイナス端子を第三の容量で接続
し、第二の差動増幅器の出力端子と第二の差動増幅器の
マイナス端子を第三の抵抗又は第二スイッチング素子で
接続したことを特徴とした電荷検出回路。
2. A first capacitance for accumulating signal charges is connected to a positive terminal of a first differential amplifier and a negative terminal of a second differential amplifier via a first switching element,
The output terminal of the first differential amplifier and the positive terminal of the first differential amplifier are connected by the second capacitor, and the output terminal of the first differential amplifier and the negative terminal of the first differential amplifier are connected to each other. Connect with one resistance, connect between the negative terminal of the first differential amplifier and a constant potential with a second resistance, keep the positive terminal of the second differential amplifier at a constant potential, The output terminal of the amplifier and the negative terminal of the second differential amplifier are connected by a third capacitor, and the output terminal of the second differential amplifier and the negative terminal of the second differential amplifier are connected by a third resistor or a second resistor. A charge detection circuit characterized by being connected by a switching element.
JP4144096A 1996-02-28 1996-02-28 Electric charge detection circuit Pending JPH09232891A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4144096A JPH09232891A (en) 1996-02-28 1996-02-28 Electric charge detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4144096A JPH09232891A (en) 1996-02-28 1996-02-28 Electric charge detection circuit

Publications (1)

Publication Number Publication Date
JPH09232891A true JPH09232891A (en) 1997-09-05

Family

ID=12608442

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4144096A Pending JPH09232891A (en) 1996-02-28 1996-02-28 Electric charge detection circuit

Country Status (1)

Country Link
JP (1) JPH09232891A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008105093A1 (en) * 2007-02-28 2008-09-04 Hamamatsu Photonics K.K. Toning circuit for liquid crystal back light

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008105093A1 (en) * 2007-02-28 2008-09-04 Hamamatsu Photonics K.K. Toning circuit for liquid crystal back light

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