JP2719058B2 - Solid-state imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device having an array composed of a plurality of light receiving elements.

[0002]

2. Description of the Related Art Solid-state imaging devices are roughly classified into two types, a CCD (charge coupled device) type and a MOS image sensor type, in a scanning system (charge transfer system), and have a high S / N ratio at present. The former is the mainstream due to advantages such as. However, a MOS image sensor may be more advantageous in some applications, such as when random access is made to pixels. In the case of a MOS image sensor, partial reading can be performed by replacing a shift register used for selecting a light receiving element on an array with a decoder and externally controlling an address line of the decoder.

[0003]

However, this type of conventional MOS image sensor has a low sensitivity to light because it is a system in which electric charges accumulated in a photodiode are simply transferred to a video line. In addition, the charge of the photodiode is reset each time it is read, and the time from when the charge is read to the next time is the information accumulation period. Therefore, the moment at which information accumulation starts is different for each photodiode. A means for converting to the integration time is required. As described above, the MOS image sensor type solid-state imaging device has flexibility, but has many problems to be solved, such as sensitivity, photoelectric conversion timing, and charge control method.

[0004]

A first solid-state imaging device according to the present invention is a solid-state imaging device having a plurality of photodiodes constituting a pixel, wherein a plurality of capacitance elements respectively connected in parallel to each photodiode are provided. A first switch element group consisting of a plurality of switch elements for controlling electric charges flowing between each photodiode and one end of each capacitance element; and a video line connected to one end of the capacitance element. After the second switch element group including a plurality of switch elements disposed between one end of the capacitive element and the video line and the switch elements of the first switch element group are turned on for a predetermined period, The switch elements of one switch element group are turned off collectively, and the switch elements of the second switch element group are turned on sequentially. A control circuit for controlling, further comprising the features. Further, the second solid-state imaging device according to the present invention includes a first operational amplifier in which one input terminal is connected to a video line and the other input terminal is fixed to a predetermined potential.
A first capacitor having a first capacitor connected between an output terminal of the operational amplifier and one input terminal, and a first reset switch connected between the output terminal of the first operational amplifier and one input terminal; And a control circuit that turns on the first reset switch of the first integrator before turning on the switch elements of the second switch element group. Further, a third solid-state imaging device according to the present invention includes a first operational amplifier in which one input terminal is connected to a video line and the other input terminal is fixed at a predetermined potential.
A first capacitor connected between an output terminal of the first operational amplifier and one input terminal; and a first capacitor having a first reset switch connected between the output terminal of the first operational amplifier and one input terminal. One integrator, a second operational amplifier having one input terminal connected to the video line and the other input terminal fixed at a predetermined potential, and a second operational amplifier connected between an output terminal of the second operational amplifier and one input terminal. Two capacitors, a second integrator having a second reset switch connected between the output terminal of the second operational amplifier and one input terminal, and provided on at least input sides of the first and second integrators, respectively. And the first and second selection switch elements, wherein the control circuit turns off the second reset switch of the second integrator when turning on the switch elements of the first switch element group. While the, with the first reset switch of the first integrator to the ON state, the first and second
One of the selection switch elements is turned on, and when the switch elements of the first switch element group are off, the first and second selection switch elements are turned on and off alternately. Further, the fourth solid-state imaging device according to the present invention is connected to the output side of the first integrator, and operates when the first reset switch of the first integrator changes from the on state to the off state. And a signal post-processing circuit that clamps a signal containing a noise component output from the second switch element and outputs a signal from which noise has been removed when the switch elements of the second switch element group are in an on state. .

Further, a plurality of transfer switch elements for turning on and off each photodiode and a corresponding capacitive element, and the transfer switch elements are turned on during a transfer period, and read during a read period after the transfer period has elapsed. A control circuit for sequentially turning on the switch elements and a plurality of readout switch elements having one end connected to the capacitive element and the other end commonly connected to a video line may be further provided.

A resettable integrator having an integrating capacitor having a capacitance smaller than that of the capacitive element and having an input connected to a video line is further provided.
The control circuit may further be configured to reset the integrator before sequentially turning on the readout switch elements.

[0007] Also, at least two integrators are provided in parallel, the input and output of which have a selection switch element, and the control circuit further turns on and off the selection switch element alternately with respect to the integrator. It is good.

[0008] Further, a signal post-processing circuit for amplifying the difference between the output of the integrator and the level at the time of resetting the integrator may be further provided.

[0009]

The charge generated by the photoelectric conversion in each photodiode is output to the corresponding capacitance element. More specifically, at the stage of reset, the connection terminal between the photodiode and the capacitor is kept at the reset potential. Thereafter, due to the charges generated according to the intensity of light irradiation on the photodiode, the potential of the connection terminal is reduced by the voltage of V6 = the generated charge amount / (capacity of the photodiode itself + capacitance element). According to the relationship of Q = C · V, in this case, the reset potential × the capacitance value is the maximum saturated charge amount, so it is obvious that the saturated charge amount can be increased by the charge amount of the capacitor element.

When a transfer switch element or the like is provided, each transfer switch element is turned on during a transfer period to output a charge to a corresponding capacitance element. Have the same photoelectric conversion time. The electric charge output to each of these capacitance elements is sequentially output from a video line.

When an integrator is further provided, the electric charge is transferred to the integrating capacitor, and the voltage is amplified by about "integrating capacitor / capacitance element" times. When there are two or more integrators, the integrators are operated by interleaving the selection switch elements, and the settling time at the time of resetting the integrators is covered.

When a signal post-processing circuit is further provided, the reset noise of the integrator is added to the level at the time of reset, and the reset noise is canceled by amplifying the difference between the output of the integrator and the level at the time of reset. Is done.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described with reference to FIGS. FIG. 1 shows an outline of a substrate layout of the solid-state imaging device of the present invention.

Photodiodes 10A to 10C which are light receiving elements
10F are arranged in a straight line, and each constitutes a pixel. Next to this is a MOS which is a transfer switch element.
Switches 11A to 11F, storage capacitors 13A to 13
F, MOS switches 12A-1 which are read switch elements
2F is arranged in proximity. MOS switches 12A-1
A video line 15 is provided next to 2F, and is connected to an integrator unit 20. MOS switches 11A to 11F
Controls the electrical connection between the photodiodes 10A to 10F and the storage capacitance elements 13A to 13F, and is controlled by a control signal data. MOS switch 1
2A to 12F control the electrical connection between the storage capacitance elements 13A to 13F and the video line 15, and are controlled by control signals selA to selF. The integrator section 20 amplifies the voltage of each of the storage capacitors 13A to 13F and outputs the amplified voltage to the signal post-processing circuit 21. The signal post-processing circuit 21 amplifies the difference between the output of the integrator and the level at the time of reset, thereby canceling and outputting reset noise. The control circuit 18 controls the control signals selA to s
eF, a shift register 16 for outputting the control signal da
ta, a timing generator 17 for outputting a control signal to the integrator section 20 and the signal post-processing circuit 21, and controls the operation of the entire apparatus.

FIG. 2 shows a circuit diagram relating to the light detection signal processing of this device. Photodiode 10A ~
10F, MOS switches 11A to 11F, storage capacitance elements 13A to 13F, and MOS switches 12A to 12F are shown only in part because of space in the drawing. Further, a control signal as shown in FIG. 3 or FIG. 4 is given from the control circuit 18. Figures 3 and 4
MOS switches 11A to 11
Control signals applied to the F and MOS switches 12A to 12F are limited to a part thereof. The integrator unit 20 and the signal post-processing circuit 21 will be further described with reference to FIG.

The integrator section 20 has two integrators 20A,
20B. The selection switches MS1 and MS2 provided in these integrators 20A and 20B are connected to a control signal S1.
The input and output of the integrators 20A and 20B are controlled by being turned on and off by A, S2A, S1B and S2B. The reset switch MQ3 outputs the control signal reset
When A and resetB are high, the integration capacitor Cf is short-circuited to reset the integrator, and the operational amplifiers A1 and A
2 is set to the reference voltage _Vref1 . When the control signal shown in FIG. 3 comes from the control circuit 18, the control circuit 18 operates with one integrator,
When the control signal shown in FIG. 4 is received, the operation is performed by two integrators.

The signal post-processing circuit 21 controls the control signal clam.
It is controlled by p and hold. When the control signal clamp is high, the transistors MQ4 and MQ5 are turned on and the integrator 20A
Alternatively, the difference between the reset level of 20B and the reference level V _ref2 is held in the capacitor C _S1 , and when the control signal hold is high, the transistor MQ6 conducts and the level at that time is held in the capacitor C _S2 . Thereby, the integrator 2
The difference between the output of 0A or 20B and the level at the time of reset is output. This operation will be described later.

Next, the operation of this device when one integrator is used will be described during the optical signal accumulation operation (from t ₁ to FIG. 3).
t ₃ ), at the time of the signal reading operation (t ₄ to t _{4 in} FIG. ₃ ).
divided into t ₁₅₎ it will be explained.

At the beginning of the optical signal storage operation, the storage capacitors 13A to 13F are reset as shown on the left side of FIG. At this time, the MOS switches 11A to 11F, M
The OS switches 12A to 12F are turned on, and the photodiodes 10A to 10F and the storage capacitors 13A to 13F are turned on.
F, the video line 15 is connected. Also, the control signal re
The output of the operational amplifier A1 and the inverting input are connected by setA, the integrator is reset, and the output becomes the reference voltage _Vref1.
become. The reference voltage V _ref1, via the video line 15 is applied to the storage capacitor 13A~13F, (t ₁ ~t ₂ in FIG. 3) is charged reset is completed.

After completion of the reset, the control signals selA to
selF becomes low, and the storage capacitors 13A to 13F
Is disconnected from the video line 15 and the operation becomes an accumulation operation. Photodiodes 10A to 10F and storage capacitor 13A
The ~13F are connected, in the initial state, the charge corresponding to the reference voltage V _ref1 is charged. A photocurrent according to the incident light intensity flows through each of the photodiodes 10A to 10F, and the charged charge decreases. That is,
The voltage between both ends of the storage capacitors 13A to 13F decreases by the amount of current flowing through the photodiodes 10A to 10F. After a certain time, the MOS switches 11A to 11F are turned off all at once by the control signal data going low. Storage capacitor 13A~13F is disconnected from the photodiode 1OA - 1OF, charge ie they each terminal voltage is held in the (t ₂ ~t ₃ in FIG. 3), the optical signal accumulating operation (integration operation) is completed.

The signal reading operation is performed by sequentially reading out the charges stored in the storage capacitors 13A to 13F as shown below. In this case, the control signals S1A, S2A are always high, and the control signals S1B, S1B,
S2B is always low, and the MOS of the integrator 20A is
The switches MS1 and MS2 are always on, and the selection switches MS1 and MS2 of the integrator 20B are always off.

Before the electric charge of the storage capacitor 13A is read, the control signal resetA goes high, the integration capacitor Cf is short-circuited, and the integrator 20A is reset. The video line 15 outputs the reference voltage V _ref1 via the selection switch MS1, and becomes the potential of the reference voltage V _ref1 . Also, the control signal hold becomes low and the control signal cla
mp goes high and the signal post-processing circuit 21 is reset. The reset level of the integrator 20A is output to the signal post-processing circuit 21 via the selection switch MS2. Subsequently, when the control signal resetA goes low, the integrator 20
The output in which the switching noise of the reset switch MQ3 is superimposed on the output of A appears. The control signal hold is high, the control signal clamp becomes low, the output of the integrator 20A is held in the capacitor Cs _1. (T ₄ ~t ₇ in FIG. 3).

When the control signal selA goes high, the storage capacitor 13A is connected to the integrator 20 via the video line 15.
A, and the electric charge stored in the storage capacitor 13A is transferred to the integration capacitor Cf. At this time, the operation is very fast due to the amplification effect of the operational amplifier A1. The voltage of the storage capacitor 13A is
It becomes the reference voltage _Vref1 in the reset state. Further, the output voltage V _O of the integrator is: V _O = V _ref1 + Ish · Δt / Cf (where Ish is the photocurrent and Δt is the integration time (t _{2 to} t
₃ ). ) The output V _out of the signal post-processing circuit 21 is expressed by the following equation using the law of conservation of charge. (V _off + V _ref2 −V _reset −ΔV _n ) × C _S1 + (V _off + V _ref2 −V _ref2 ) × C _S2 = (V _off + V _ref2 −V _o −ΔV _n ) × C _S1 + (V _off + V _ref2) −V _out ) × C _S2 where, V _reset : output at the time of resetting of the operational amplifier A1 V _off : offset voltage of the operational amplifier A1 ΔV _n : switching noise of the reset switch MQ3 The left side of the capacitors C _S1 and C _S2 at the time of resetting Status,
The right side shows the state when the charge is read from the storage capacitor.

Since V _reset is equal to the reference voltage V _ref1 , V _out = − (C _S1 / C _S2 ) · (Ish · Δt / Cf) + V _ref2 . Further, if C _S1 = C _S2 , V _out = V _ref2 −Ish · Δt / Cf, and the reference voltage is accurately determined without being affected by the offset voltage of the operational amplifier circuit A1 or the switching noise of the reset switch MQ3. signal corresponding to the intensity of the optical signal information or light for V _ref2 is output from the signal post-processing circuit 21 (t ₈ ~t ₉ in FIG. 3).

[0025] The storage capacitor 13B and later also read out stored charge in turn in a similar operation, the signal corresponding to the intensity of the light is output (t ₁₄ ~t ₁₉ in FIG. 3).

When the integrator 20A is reset (t _{5 in} FIG. 3).
~t _6), easily produce ringing at the output of the operational amplifier A1, the control signal resetA is should be sufficiently long period at the high, which may hinder high-speed operation. In this case, there are two or more integrators,
Switching these integrators solves this problem.

FIG. 4 is a timing chart of control signals when two integrators are used. In time of light signal accumulating operation (t ₁ ~t ₃ in FIG. 4), the charge on the storage capacitor 13A~13F is accumulated in the same operation as FIG. 3 described above.
During the signal read operation (right side in FIG. 4), the control signal S
1A and S2A and S1B and S2B, an integrator 20A,
20B is switched. Further, when one of the integrators is inputting the charge of the storage capacitor, the other integrator is reset. Therefore, the control signal reset
A, t ₂₈ ~t ₂₉ periods (Fig. 4 B is at high, t
_{38 to} t ₃₉ ) becomes sufficiently long, and even if ringing of the operational amplifier A1 appears, it is prevented from being output.

The above-mentioned solid-state imaging device can be colored. FIG. 5 shows an outline of a board layout in the case of colorization. Red photodiode row 4
10R, the green photodiode array 410G, and the blue photodiode array 410B correspond to the photodiode 10 of FIG.
They are equivalent to AF and are arranged adjacent to each other. Corresponding storage capacitors, MOS switches, and the like are provided in portions indicated by reference numerals 412R, 412G, and 412B. The charge of each storage capacitor is output to a red video line 415R, a green video line 415G, and a blue video line 415B, respectively.
Red integrator 420R, green integrator 420G, blue integrator 420B, red signal post-processing circuit 421R, green signal post-processing circuit 421G, blue signal post-processing circuit 4
The signal is amplified and output at 21B. FIG. 6 shows a red photodiode row 410R and a green photodiode row 410.
The enlarged view of the area where the G and blue photodiode arrays 410B are arranged is shown. Each photodiode row 4
10R, 410G, 410B, a red photodiode 610R, a green photodiode 610G,
A blue photodiode 610B is arranged close to the blue photodiode 611R, 611G, and 611B.
Each of the storage capacitors is connected via a switch.

As described above, the solid-state imaging device according to the above-described embodiment includes a plurality of photodiodes 10 constituting pixels.
In a solid-state imaging device having A to 10C, a plurality of capacitance elements 13A to 13C connected in parallel to the respective photodiodes 10A to 10C, the respective photodiodes 10A to 10C and the respective capacitance elements 13
A first switch element group 11 composed of a plurality of switch elements for controlling electric charges flowing between one ends of A to 13C, respectively.
A to 11C, a video line 15 connected to one end of each of the capacitance elements 13A to 13C, and a second switch element including a plurality of switch elements respectively arranged between one end of each of the capacitance elements 13A to 13C and the video line 15. Groups 12A-1
2C and the switch elements 11A to 11A of the first switch element group.
After 1C is turned on for a predetermined period of time from t1 to t3,
The switch elements of the first switch element groups 11A to 11C are turned off collectively, and the second switch elements 12A to 11C are turned off.
A control circuit is provided for controlling A to 12C to be sequentially turned on. Further, the solid-state imaging device according to the above-described embodiment includes a first operational amplifier A1 having a first input terminal connected to the video line 15 and the other input terminal fixed to a predetermined potential.
A first capacitor Cf connected between the output terminal of the operational amplifier A1 and one of the input terminals, and a first operational amplifier A
A first terminal connected between the first output terminal and one input terminal
The control circuit further includes a first integrator 20A having a reset switch MQ3, and the control circuit controls the first integrator 2 before turning on the switch elements 12A to 12C of the second switch element group.
The 0A first reset switch MQ3 is turned on. Further, in the solid-state imaging device of the above embodiment, the first operational amplifier A1 in which one input terminal is connected to the video line 15 and the other input terminal is fixed to a predetermined potential, the output terminal of the first operational amplifier A1 and one input terminal A first capacitor Cf connected between the first terminal C and a first integrator 20A having a first reset switch MQ3 connected between the output terminal of the first operational amplifier A1 and one input terminal; A second operational amplifier A1 having one input terminal connected to the line 15 and the other input terminal fixed at a predetermined potential; a second capacitor Cf connected between an output terminal of the second operational amplifier A1 and one input terminal; And the second operational amplifier A1
A second integrator 20B having a second reset switch MQ3 connected between the output terminal and one input terminal of the second integrator 20B;
First and second selection switch elements M provided on at least input sides of the first and second integrators 20A and 20B, respectively.
S1, MS1, and the control circuit, when the switch elements 11A to 11C of the first switch element group are turned on, the second reset switch M of the second integrator 20B.
While Q3 is kept off, the first reset switch MQ3 of the first integrator 20A is turned on, and one of the first and second selection switch elements MS1 and MS1 is turned on, and the first switch element is turned on. Group switch element 1
When 1A to 11C are off, the first and second selection switch elements MS1 and MS1 are alternately turned on and off. The solid-state imaging device according to the above-described embodiment includes a first integrator 2
0A, and clamps a signal containing a noise component output from the first integrator 20A when the first reset switch MQ3 of the first integrator 20A changes from the on state to the off state, It further includes a signal post-processing circuit 21 that outputs a signal from which noise has been removed when the switch elements 12A to 12C of the second switch elements are in an ON state. The present invention is not limited to the above-described embodiment, and various modifications are possible.

For example, the charging voltage at the time of resetting the storage capacitor is set to the reference voltage _Vref1 , but a separate switch is provided between the charging power supply and the power supply and the video line, and the charging The capacitor may be charged. In this case, the power supply can be made variable, and the level can be adjusted. When the light intensity is high, a buffer amplifier using an FET can be used instead of the integrator. Further, the shift register may be replaced with a decoder, and data may be read from an arbitrary photodiode.

[0031]

As described above, according to the solid-state imaging device of the present invention, since each transfer switch element is turned on during the same period, the photoelectric conversion time of each photodiode is equal, and the output signal The conditions are equal, and no external level correction is required. In addition, since a capacitance element is provided for each photodiode, and the terminal voltage of the capacitance element, which is pixel information, is sequentially read from the readout switch element and the voltage is amplified by an integrator, pixel information with high sensitivity can be obtained. Further, when two integrators are used, high-speed operation can be achieved. Further, since the output of the current amplifying means is taken out via a signal post-processing circuit built in the device,
Since a signal having a high N ratio can be taken out and a complicated signal processing circuit is not required outside, it is easy to use.

[Brief description of the drawings]

FIG. 1 is a schematic diagram of a layout according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing one embodiment of the present invention.

FIG. 3 is a timing chart showing an operation of one system of the integrator of the embodiment.

FIG. 4 is a timing chart showing the operation of two systems of the integrator of the present embodiment.

FIG. 5 is a schematic diagram of a layout of one embodiment of the present invention when colorized.

FIG. 6 is an enlarged view of a region where a photodiode array is arranged.

[Explanation of symbols]

 10A to 10F Photodiodes 11A to 11F, 12A to 12F MOS switches 13A to 13F Storage capacitors 15 Video lines 18 Control circuits 20A and 20B Integrators 21 Signal post-processing circuits MS1, MS2 Selection switches 415R, 415G, 415B ... Video line 420R, 420G, 420B ... Integrator section 421R, 421G, 421B ... Signal post-processing circuit 610R, 610G, 610B ... Photodiode

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification number Agency reference number FI Technical indication location H01L 31/10 H01L 31/10 A H04N 5/335 G (56) References JP-A 1-248888 (JP, A) JP-A-1-109975 (JP, A) JP-A-61-56572 (JP, A)

Claims (4)

(57) [Claims] 1. A solid-state imaging device having a plurality of photodiodes constituting a pixel, wherein a plurality of capacitance elements respectively connected in parallel to each of the photodiodes; and each of the photodiodes and the respective capacitances A first switch element group including a plurality of switch elements that respectively control electric charges flowing between one end of the element, a video line connected to the one end of the capacitive element, the one end of the capacitive element, and the video line And a second switch element group including a plurality of switch elements respectively disposed between the first switch element group and the first switch element group. The devices are simultaneously turned off and the second
A solid-state imaging device, comprising: a control circuit that controls the switch elements of the switch element group to be sequentially turned on. 2. A first operational amplifier having one input terminal connected to the video line and the other input terminal fixed at a predetermined potential, and connected between an output terminal of the first operational amplifier and the one input terminal. And a first integrator having a first reset switch connected between the output terminal and the one input terminal of the first operational amplifier. 2. The solid-state imaging device according to claim 1, wherein the first reset switch of the first integrator is turned on before the switch elements of the second switch element group are turned on. 3. 3. A first operational amplifier having one input terminal connected to the video line and the other input terminal fixed at a predetermined potential, and connected between an output terminal of the first operational amplifier and the one input terminal. A first capacitor, a first integrator having a first reset switch connected between the output terminal of the first operational amplifier and the one input terminal, and one input terminal connected to the video line. Is connected, the other input terminal is fixed at a predetermined potential, a second operational amplifier, a second capacitor connected between the output terminal of the second operational amplifier and the one input terminal, and a second operational amplifier. A second integrator having a second reset switch connected between the output terminal and the one input terminal; and a second integrator provided on at least input sides of the first and second integrators. And a first and a second selection switch element, wherein the control circuit turns off the second reset switch of the second integrator when the switch elements of the first switch element group are turned on. While keeping the state, the first reset switch of the first integrator is turned on, and one of the first and second selection switch elements is turned on, and the switch element of the first switch element group is turned on. 2. The solid-state imaging device according to claim 1, wherein when the switch is off, the first and second selection switch elements are turned on and off alternately. 3. 4. A noise connected to an output side of the first integrator and output from the first integrator when the first reset switch of the first integrator changes from an on state to an off state. 4. A signal post-processing circuit for clamping a signal including a component and outputting a signal from which the noise has been removed when a switch element of the second switch element group is in an ON state. 3. The solid-state imaging device according to item 1.