JPH0956171A - Method and apparatus for controlling power supplied to parallel load in current inverter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent mutual interference between inductive loads and improve the efficiency of operation by controlling in a time-division manner the switching operation of an inverter circuit in correspondence with the operating conditions for the inductive loads. SOLUTION: A counter 12 counts the pulses of switching signals TPA, TPB of an input circuit (CI) 11 for a counter, and outputs it to a comparator 13. The comparator 13 compares the values of switching signal TPA, TPB counts with a set value of operation ratio. Base on the result of the comparison the AND gates 21, 22 of the CI 11 and the AND gates 26, 27 of an input circuit 15 for flip-flop are on/off-controlled to output a gate control signal for controlling the timing of pulse signal input from a VCO 14 to flip-flop circuits 16, 17. That is, the switching operation of an inverter circuit is controlled in a time-division manner with the timing get on the VCO 14 based on a set voltage corresponding to the operating conditions for loads connected in parallel.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for controlling power supply to a parallel load of a current type load resonance inverter and a power supply control apparatus for the same, and more particularly to parallel driving a plurality of inductive loads having different operating conditions. The present invention relates to a method for controlling power supply to a parallel load of a current-type load resonance inverter and a power supply control apparatus for the same.

[0002]

2. Description of the Related Art Conventionally, as a load to which AC power is supplied from a current type load resonance inverter, for example, a plurality of inductive loads arranged in close parallel with each other under different operating conditions (for example, a melting furnace utilizing induction heating). , Etc.), and in this case, a plurality of resonance circuits having different resonance conditions are formed due to the difference in the inductance component included in each inductive load.

[0003]

However, in the case of a plurality of conventional inductive loads which are arranged in parallel in close proximity and have different operating conditions, a plurality of resonance conditions are caused by the difference in the inductance component contained in each inductive load. Since different resonant circuits were formed, when trying to operate each inductive load in parallel with a current type load resonant inverter composed of a single power source, mutual interference occurs between the inductive loads arranged in close proximity and There is a problem that the normal operation of the power supply control to the parallel load by the load resonance inverter becomes difficult and the operation efficiency is reduced.

Further, in the current type load resonance inverter in which the inductive load is operated in parallel, it operates as a constant current source with respect to the inductive load and the output current supplied to each inductive load cannot be interrupted. It was necessary to perform switching operation by overlapping each load.

An object of the present invention is to provide an operating condition for each inductive load when a plurality of inductive loads arranged in parallel in close proximity and having different operating conditions are operated in parallel by a current type load resonance inverter composed of a single power source. By controlling the switching operation of the switching elements in each inverter circuit set in accordance with the above, the mutual interference between inductive loads is prevented and the efficiency of operation is improved. A supply power control method and a supply power control device thereof are provided.

[0006]

The means of the present invention are as follows.

According to a first aspect of the present invention, DC power is supplied from a single DC power source to a plurality of inverter circuits, loads having different operating conditions are connected in parallel to each of the inverter circuits, and a switching element in each inverter circuit is connected. In a method for controlling power supply to a parallel load of a current-type inverter that controls AC power supplied to each load connected in parallel by switching control, an operation of a switching element in each inverter circuit corresponding to the operating condition for each load A condition is set, and the switching timing of each switching element in each inverter circuit is time-divisionally controlled based on the set operating condition. In this time-divisional control, the operation of the switching element of each inverter circuit in the previous time-division period. Memorize the conditions, and based on this memorized operating condition, Set the operating condition of the switching elements of the inverter circuit in the period, by controlling the switching timing of the switching elements of each inverter circuit is characterized in that so as to control the AC power supplied to the parallel load.

According to a second aspect of the present invention, direct current power is supplied from a single direct current power source to a plurality of inverter circuits, loads having different operating conditions are connected in parallel for each of the inverter circuits, and a switching element in each inverter circuit is connected. In a power supply control device for controlling AC power supplied to each load connected in parallel by switching control, an operation condition setting means for setting an operation condition of a switching element in each inverter circuit corresponding to an operation condition for each load. And a control means for time-divisionally controlling the switching timing of each switching element in each inverter circuit based on the set operating conditions.

Further, in this case, as in the supply power control device according to claim 3, the control means stores the operating condition of the switching element of each inverter circuit in the previous time division period in the time division control. Then, based on the stored operating conditions, set the operating conditions of the switching elements of each inverter circuit in this time division period, control the switching timing of the switching elements of each inverter circuit, and supply the AC power to the parallel load. It is effective to control

According to the invention of claim 1, DC power is supplied from a single DC power source to a plurality of inverter circuits, and loads having different operating conditions are connected in parallel for each inverter circuit.
In a method for controlling power supply to a parallel load of a current type inverter that controls alternating-current power supplied to each load connected in parallel by switching control of a switching element in each inverter circuit, the method corresponding to the operating conditions for each load, The operating conditions of the switching elements in each inverter circuit are set, and the switching timing of each switching element in each of the inverter circuits is time-divisionally controlled based on the set operating conditions. The operating condition of the switching element of each inverter circuit in is stored, the operating condition of the switching element of each inverter circuit in this time division period is set based on the stored operating condition, and the switching element of each inverter circuit is switched. Timing is controlled AC power is controlled to be supplied to the parallel load.

Therefore, when the inductive loads arranged in parallel are operated in parallel, the electric power supplied to the parallel load of the current type inverter composed of a single power source can prevent the mutual interference between the inductive loads. A control method can be provided.

According to the second aspect of the present invention, DC power is supplied from a single DC power source to a plurality of inverter circuits, and loads having different operating conditions are connected in parallel for each inverter circuit.
In a supply power control device for controlling alternating current power supplied to each load connected in parallel by switching control of a switching element in each inverter circuit, the operating condition setting means includes the inverters corresponding to the operating conditions for each load. The operating conditions of the switching elements in the circuit are set, and the control means time-divisionally controls the switching timing of each switching element in each of the inverter circuits based on the set operating conditions.

Therefore, when the inductive loads arranged in parallel are operated in parallel, the electric power supplied to the parallel load of the current type inverter composed of a single power source can prevent the mutual interference between the inductive loads. A control device can be provided.

According to the third aspect of the invention, the control means stores the operating condition of the switching element of each inverter circuit in the previous time division period in the time division control, and the stored operation. Based on the condition, the operating condition of the switching element of each inverter circuit in this time division period is set, the switching timing of the switching element of each inverter circuit is controlled, and the AC power supplied to the parallel load is controlled.

Therefore, in the power supply control device for the parallel load of the current type inverter, an appropriate operation according to the parallel load can be time-divisionally controlled, and the operation efficiency of the current type inverter constituted by a single power source can be improved. Can be improved.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to FIGS. 1 to 5 are diagrams showing an embodiment of a current type load resonance inverter to which the present invention is applied.

First, the configuration will be described. FIG. 1 is a diagram showing a circuit configuration of a current type load resonance inverter 1 of the present embodiment. In FIG. 1, a current-type load resonance inverter 1 includes a full-wave phase control rectifier circuit 2 that rectifies an AC voltage input from an AC power supply (not shown) by thyristors D1 and D2, and outputs a DC voltage. A DC reactor LD that smoothes a pulsating current component included in the DC voltage output from the control rectification circuit 2, and inverter circuits 3 and 4 configured by bridge-connecting switching elements S1 to S4 such as power MOS-FETs. , High-frequency output currents IHF1 and IHF2 output from the inverter circuits 3 and 4 are load A and load B
Transformers T1 and T2 for transmission to the inverter circuit 3,
High-frequency current detection transformers CT1 and CT2 for detecting high-frequency output currents IHF1 and IHF2 output from the radio frequency converter 4, and high-frequency voltage detection for detecting high-frequency load voltages VHF1 and VHF2 generated on the load side by the high-frequency output currents IHF1 and IHF2. Transformers VT1 and VT2.

In the switching elements S1 to S4 of the inverter circuits 3 and 4, the switching timing of each gate electrode is controlled by a combination of the switching elements S1 and S4 and the switching elements S2 and S3.
PA, TP * A, TPB, and TP * B are flip-flop circuits 16 and 1 in a switching control circuit 10 described later.
Input from 7.

Loads A and B are connected to the output terminal of the inverter circuit 3 via transformers T1 and T2. The loads A and B are capacitors C1 and C2 and coils L1 and L.
It is composed of two synthesis circuits.

FIG. 2 shows switching elements S1 to S1 of the inverter circuits 3 and 4 in the current type load resonance inverter 1 shown in FIG.
It is a block block diagram of the switching control circuit 10 which controls the switching timing of S4.

In FIG. 2, the switching control circuit 10 includes an AND gate 21, 22, 23 and an inverter 2
4 and an OR gate 25, a counter input circuit 11, a counter 12, a comparator 13, and V
CO14, AND gates 26 and 27, and inverter 2
Flip-flop input circuit 15 composed of 8
And flip-flops 16 and 17.

The counter input circuit 11 has a switching signal T output from the flip-flop circuits 16 and 17.
PA and TPB are input to one input terminals of the AND gates 21 and 22, and the AND gate 23 is operated via the OR gate 25.
It is a circuit for outputting to the counter 12 by. Also, AN
The START DELAY signal input to the D gate 23 is set to the “Lo” signal during the start-up operation period of the current type load resonance inverter 1 by the control unit (not shown), so that the start-up operation period is After the data input to the counter 12 is invalidated and the normal operation is completed after the start-up operation is completed, the data input to the counter 12 is enabled by setting the “Hi” signal.

The counter 12 is a counter input circuit 11
Each pulse number of the switching signals TPA and TPB input from is counted, and each count value is output to the comparator 13. The comparator 13 compares the count value by the switching signals TPA and TPB input from the counter 12 with the operation ratio setting value input from a memory (not shown) in which an operation ratio setting table described later is set, and based on the comparison result. AND gates 21 and 22 of the counter input circuit 11 and A of the flip-flop input circuit 15
Each gate of the ND gates 26 and 27 is turned on / off to output a gate control signal for controlling the input timing of the pulse signal from the VCO 14 to the flip-flop circuits 16 and 17.

An example of the operation ratio setting table stored in the memory for outputting the operation ratio setting value to the comparator 13 is shown in FIG. In this operation ratio setting table, the horizontal axis indicates the cycle T for time-division control, and the vertical axis indicates the load A within the time-division cycle T.
And an operation ratio that determines at what ratio (%) the load B is operated.

VCO (Voltage Controled Oscillator:
The voltage-controlled oscillator 14 is a set voltage generation circuit 3 described later.
A pulse signal corresponding to each operating condition of the load A and the load B is oscillated based on the set voltage signal input from 0, and is output to the flip-flop input circuit 15. VCO
Reference numeral 14 denotes a flip-flop input circuit 15 that oscillates a pulse signal corresponding to a start-up operating condition based on a start-up set voltage signal input from a control unit (not shown) when the current-type load resonance inverter 1 is started up. Output to.

The flip-flop input circuit 15 has a VC
The pulse signal input from O14 is applied to the AND gate 26
The output pulse signal is output to the flip-flop circuit 16 via the AND gate 27 and the input pulse signal is output to the flip-flop circuit 17 via the AND gate 27 when the gate of the AND gate 27 is turned on.

The flip-flop circuit 16 generates switching signals TPA and TP * A based on the pulse signal input from the flip-flop input circuit 15, and the gates of the switching elements S1 to S4 of the inverter circuit 3 of FIG. To control the switching operation of the switching elements S1 to S4.

The flip-flop circuit 17 generates the switching signals TPB, TP * B based on the pulse signal input from the flip-flop input circuit 15, and the gates of the switching elements S1 to S4 of the inverter circuit 4 of FIG. To control the switching operation of the switching elements S1 to S4.

FIG. 4 shows the VCO 14 of FIG. 2 when the current type load resonance inverter 1 shifts from the starting operation to the normal operation.
2 is a circuit configuration diagram of a set voltage generation circuit 30 that outputs a set voltage signal.

In FIG. 4, the set voltage generating circuit 30
Is a phase comparison circuit 31 and a load A setting voltage generation circuit 32.
And a load B setting voltage generation circuit 33.

The phase comparison circuit 31 includes a high frequency output current IHF detected by the high frequency current detecting transformers CT1 and CT2 and the high frequency voltage detecting transformers VT1 and VT2 shown in FIG.
1, IHF2 and the high frequency load voltages VHF1 and VHF2 are compared in phase, and a voltage signal corresponding to the phase difference is generated based on the comparison result and output to the VCO 14.

The load A set voltage generating circuit 32 is composed of a sample hold circuit (SH-A) 32a, a voltage setting capacitor CA, and switches SW1 and SW2.

The sample hold circuit 32a samples the load A set voltage signal output from its own load A set voltage generation circuit 32 at the input timing of the A-MEMORY signal input from the control unit (not shown). It is then held and output to the voltage setting capacitor CA.
The voltage setting capacitor CA is a sample hold circuit 3
Charges due to the load A setting voltage signal input from 2a are accumulated.

The switch SW1 is turned on by an ASet signal input from a control unit (not shown),
The set voltage signal for the load A by the electric charge accumulated in the voltage setting capacitor CA is output to the VCO 14. Switch S
W2 is an AR input from a main controller (not shown)
It is turned on by the reset signal and discharges the electric charge accumulated in the voltage setting capacitor CA to the ground side,
The voltage setting capacitor CA is initialized.

The load B set voltage generating circuit 33 is composed of a sample hold circuit (SH-B) 33a, a voltage setting capacitor CB, and switches SW3 and SW4.

The sample hold circuit 33a samples the load B setting voltage signal output from the load B setting voltage generating circuit 33 of its own at the input timing of the B-MEMORY signal input from the control unit (not shown). It is then held and output to the voltage setting capacitor CB.
The voltage setting capacitor CB is used in the sample hold circuit 3
The charge due to the load B setting voltage signal input from 3a is accumulated.

The switch SW3 is turned on by a BSet signal input from a main control unit (not shown), and outputs a load B setting voltage signal due to the charges accumulated in the voltage setting capacitor CB to the VCO 14. The switch SW4 is turned on by a BReset signal input from a main control unit (not shown) and discharges electric charges accumulated in the voltage setting capacitor CB to the ground side to initialize the voltage setting capacitor CB. To do.

Next, the operation of this embodiment will be described. The operation of the current type load resonance inverter 1 of the present embodiment will be described with reference to the timing chart of the signals of the respective parts shown in FIG.

In the current type load resonance inverter 1, when a main power switch (not shown) is turned on, an AC voltage input from an AC power supply (not shown) is rectified by the full wave phase control rectifier circuit 2 and output as a DC voltage. Then, the DC reactor LD smoothes the pulsating flow component included in the output DC voltage and supplies the smoothed component to the inverter circuits 3 and 4.

Then, in the switching control circuit 10,
The start set voltage signal is VC from the control unit (not shown).
When input to O14, a pulse signal corresponding to the startup operation condition is oscillated based on the startup set voltage signal and output to the flip-flop input circuit 15. When the AND gates 26 and 27 of the flip-flop input circuit 15 output the pulse signals corresponding to the startup operation conditions to the flip-flop circuits 16 and 17, the flip-flop circuits 16 and 17 switch the switching signals TPA and T.
P * A, TPB and TP * B are generated and output to the gates of the switching elements S1 to S4 of the inverter circuits 3 and 4, respectively.

In the inverter circuits 3 and 4, the flip-flop circuits 16 and 17 are connected to the switching elements S1 to S4.
Switching signals TPA, TP * input to the gate of
A, TPB, TP * B, switching elements S1 to
The switching operation of S4 is performed by switching elements S1 and S
4 is controlled by each combination of the switching elements S2 and S3, the output current of the starting frequency is supplied to the load A and the load B, and the starting operation is started.

When the load A and the load B are operated at the starting frequency for a predetermined period by this starting operation, the high-frequency current detecting transformers CT1 and CT are supplied during each starting operation period.
The high frequency output currents IHF1 and IHF2 are detected by 2 and the high frequency load voltages VHF1 and VHF2 generated on the load A and load B sides by the high frequency output currents IHF1 and IHF2, respectively.
Are respectively detected by the high frequency voltage detecting transformers VT1 and VT2 and output to the phase comparison circuit 31 in the set voltage generation circuit 30 of FIG.

In the phase comparison circuit 31, during the operation of the load A, the phases of the high frequency output current IHF1 and the high frequency load voltage VHF1 are compared to generate the set voltage signal for A corresponding to the phase difference and the load A During the operation, the phases of the high frequency output current IHF2 and the high frequency load voltage VHF2 are compared, a B set voltage signal corresponding to the phase difference is generated and output to the VCO 14, and the normal operation state is entered.

During the start-up operation, the AND gate 23 of the counter input circuit 11 in the switching control circuit 10 is also used.
Then, the START DEL input from the control unit (not shown)
Since the AY signal is set to the “Lo” level, the switching signals TPA and TPB output from the flip-flop circuits 16 and 17 are not input to the counter 12.

Then, when shifting to the normal operation state, ST
The ART DELAY signal is switched to the “Hi” level, and the comparator 1 in the switching control circuit 10 is
If the output of 3 is at the “Hi” level before the count value is input from the counter 12, the inverter 28 of the AND gate 26 of the flip-flop input circuit 15
Side input becomes "Lo" level and the gate is turned off, and the comparator side input of AND gate 27 becomes "Hi".
The level becomes high (see FIG. 5F), the gate is turned on, and the oscillation signal input from the VCO 14 is output to the flip-flop circuit 17.

In the flip-flop circuit 17, the switching signals TPB and TP * B are generated by the input oscillation signal (see FIGS. 5D and 5E) and output to the inverter circuit 4. The switching operation of the four switching elements S1 to S4 is controlled by each combination of the switching elements S1 and S4 and the switching elements S2 and S3, the output current of the operating frequency is supplied to the load B, and the normal operation is started. It

At this time, the high frequency output current IHF2 to the load B
Is detected by the high-frequency current detecting transformer CT2, and the high-frequency load voltage VHF2 due to the high-frequency output current IHF2 is detected by the high-frequency voltage detecting transformer VT2 and output to the phase comparison circuit 31 in the set voltage generation circuit 30. Then, a voltage signal corresponding to the phase difference is generated,
By being output to the VCO 14 in the switching control circuit 10, an oscillation signal based on the phase difference is generated and output to the flip-flop circuit 17.

At this time, the flip-flop circuit 17
The switching signal TPB output from is output to the AND gate 22 in the counter input circuit 11, is output to the counter 12 via the OR gate 25 and the AND gate 23, and is counted up in the counter 12.
Then, the count-up value is output to the comparator 13 and is compared with the operation ratio set value on the load B side shown in FIG. 3, and it is confirmed that the input count value has reached the operation ratio set value. Then, when the output of the comparator 13 is switched from the "Hi" level to the "Lo" level (see FIG. 5 (f)), the AND gate 27 is turned off and the supply of the pulse signal to the flip-flop circuit 17 is stopped. Then, the operation of the load B is stopped.

At this time, the load B in the set voltage generating circuit 30
In the setting voltage generation circuit 33 for use, BM from the control unit (not shown)
The EMORY signal is input (see FIG. 5 (j)), the B setting voltage signal input to the sample hold circuit 33a is held, and the charge is stored in the voltage setting capacitor CB.

Next, the flip-flop input circuit 15
The AND gate 26 in the inside becomes the gate-on state (see FIG. 5C), and in the set voltage generating circuit 32 for the load A in the setting voltage generating circuit 30, the ASet signal is input to the switch SW1 from the control unit (not shown). To turn on (Fig. 5
(See (h)), the voltage setting capacitor C in the previous startup operation.
The electric charge accumulated in A is VCO1 as the A setting voltage signal.
4 is output.

Immediately after this, the set voltage generating circuit 32 for the load A is
Then, the A Reset signal is sent from the control unit (not shown) to the switch S.
It is input to W2 and turned on (see FIG. 5 (i)),
The charges accumulated in the voltage setting capacitor CA are discharged to the ground side and initialized.

The VCO 14 generates an oscillation signal based on the input A setting voltage signal, and the AND gate 26
When it is output to the flip-flop circuit 16 via the, the flip-flop circuit 16 generates switching signals TPA and TP * A based on the input oscillation signal (see FIGS. 5A and 5B). , When output to the inverter circuit 3, the switching elements S1 to S1 of the inverter circuit 3 are output.
The S4 switching operation is performed by the switching elements S1 and S4.
Controlled by each combination of the switching elements S2 and S3, the output current of the operating frequency is supplied to the load A, and the normal operation is started.

At this time, the high frequency output current IHF1 to the load A
Is detected by the high-frequency current detecting transformer CT1, and the high-frequency load voltage VHF1 due to the high-frequency output current IHF1 is detected by the high-frequency voltage detecting transformer VT1 and output to the phase comparison circuit 31 in the set voltage generation circuit 30. Then, a voltage signal corresponding to the phase difference is generated,
By being output to the VCO 14 in the switching control circuit 10, an oscillation signal based on the phase difference is generated and output to the flip-flop circuit 16.

At this time, the flip-flop circuit 16
The switching signal TPA output from is output to the AND gate 21 in the counter input circuit 11, is output to the counter 12 via the OR gate 25 and the AND gate 23, and is counted up in the counter 12.
Then, the count-up value is output to the comparator 13 and is compared with the operation ratio setting value on the load A side shown in FIG. 3, and it is confirmed that the input count value has reached the operation ratio setting value. Then, when the output of the comparator 13 is switched from the “Lo” level to the “Hi” level (see FIG. 5C), the AND gate 26 is turned off and the supply of the pulse signal to the flip-flop circuit 16 is stopped. Then, the operation of the load A is stopped.

At this time, the load A in the set voltage generating circuit 30
In the setting voltage generation circuit 32 for use, the control unit (not shown)
The EMORY signal is input (see FIG. 5G), the A setting voltage signal input to the sample hold circuit 32a is held, and the charge is stored in the voltage setting capacitor CA.

Next, the flip-flop input circuit 15
The AND gate 27 in the inside becomes the gate-on state (see FIG. 5C), and in the set voltage generating circuit 33 for the load B in the setting voltage generating circuit 30, the BSet signal is input to the switch SW3 from the control unit (not shown). To turn on (Fig. 5
(See (k)), the voltage setting capacitor C in the previous normal operation
The electric charge accumulated in B is VCO1 as a B setting voltage signal.
4 is output.

Immediately after this, the set voltage generation circuit 33 for the load B
Then, the BRESET signal is sent from the control unit (not shown) to the switch S.
It is input to W4 and turned on (see FIG. 5 (l)),
The charges accumulated in the voltage setting capacitor CB are discharged to the ground side and initialized.

The VCO 14 generates an oscillation signal based on the input B setting voltage signal, and the AND gate 27
When it is output to the flip-flop circuit 17 via the, the flip-flop circuit 17 generates switching signals TPB and TP * B based on the input oscillation signal (see FIGS. 5D and 5E). , When output to the inverter circuit 4, the switching elements S1 to S1 of the inverter circuit 4 are output.
S4 switching operation is performed by switching elements S1 and S4
Controlled by each combination of the switching elements S2 and S3, the output current of the operating frequency is supplied to the load B, and the normal operation is repeated.

At this time, similarly, the high frequency output current IHF2 to the load B is detected by the high frequency current detecting transformer CT2, and the high frequency load voltage VHF2 due to the high frequency output current IHF2 is detected by the high frequency voltage detecting transformer VT2. The phase comparison circuit 3 in the set voltage generation circuit 30 that is detected
When it is output to 1, a voltage signal corresponding to the phase difference is generated and output to the VCO 14 in the switching control circuit 10 to generate an oscillation signal based on the phase difference, and then to the flip-flop circuit 17. Is output.

At this time, the flip-flop circuit 17
The switching signal TPB output from is output to the AND gate 22 in the counter input circuit 11, is output to the counter 12 via the OR gate 25 and the AND gate 23, and is counted up in the counter 12.
Then, the count-up value is output to the comparator 13 and is compared with the operation ratio set value on the load B side shown in FIG. 3, and it is confirmed that the input count value has reached the operation ratio set value. Then, when the output of the comparator 13 is switched from the "Lo" level to the "Hi" level (see FIG. 5 (f)), the AND gate 27 is turned off and the supply of the pulse signal to the flip-flop circuit 17 is stopped. Then, the operation of the load A is stopped.

At this time, the load A in the set voltage generating circuit 30
In the setting voltage generation circuit 33 for use, BM from the control unit (not shown)
The EMORY signal is input (see FIG. 5 (j)), the B setting voltage signal input to the sample hold circuit 33a is held, and the charge is stored in the voltage setting capacitor CB.

Then, in the normal operation state, the time-divisional operation in which the operation conditions are set for the load A and the load B is repeatedly executed.

As described above, in the current type load resonance inverter 1 having the single power supply configuration of the present embodiment, the load A and the load B connected in parallel are loaded in the set voltage generating circuit 30 during the normal operation. The switching operation of the inverter circuits 3 and 4 is time-divisionally controlled at the switching timing based on the set voltage corresponding to the operating conditions of the loads A and B set in the A set voltage generation circuit 32 and the load B set voltage generation circuit 33. Therefore, it is possible to prevent mutual interference between inductive loads, set operating conditions for each parallel load, and perform time-division control, and a current-type load resonant inverter configured by a single power supply. The operation efficiency in 1 can be improved.

[0064]

According to the invention described in claim 1, when the inductive loads arranged in parallel are operated in parallel, a single power source can prevent the mutual interference between the inductive loads. It is possible to provide a method for controlling power supply to a parallel load of a current type inverter.

According to the second aspect of the present invention, when the inductive loads arranged in parallel are operated in parallel, a current type constituted by a single power source capable of preventing mutual interference between the inductive loads. A power supply control device for a parallel load of an inverter can be provided.

According to the invention described in claim 3, in the power supply control device for the parallel load of the current type inverter, an appropriate operation according to the parallel load can be time-division controlled,
It is possible to improve the operation efficiency of the current type inverter configured with a single power source.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a current type load resonance inverter to which the present invention is applied.

2 is a switching element S1 of the inverter circuit of FIG.
The block block diagram of the switching control circuit which controls the switching timing of-S4.

FIG. 3 is a diagram showing an operation ratio setting table for setting operation ratio setting values input to the comparator of FIG.

FIG. 4 is a circuit configuration diagram of a set voltage generation circuit that generates a set voltage signal of the VCO of FIG.

5 is a switching element S1 of the inverter circuit of FIG.
The figure which shows the timing chart of the signal of each part at the time of controlling the switching timing of-S4.

[Explanation of symbols]

 1 Current type load resonance inverter 2 Full wave phase control rectifier circuit 3, 4 Inverter circuit 10 Switching control circuit 11 Counter input circuit 12 Counter 13 Comparator 14 VCO 15 Flip-flop input circuit 16, 17 Flip-flop circuits 21-23, 26 , 27 AND gate 24, 28 Inverter 25 OR gate 30 Set voltage generation circuit 31 Phase comparison circuit 32 Load A set voltage generation circuit 32a Sample hold circuit 33 Load B set voltage generation circuit 33a Sample hold circuit LD DC reactor CT1, CT2 High-frequency current detection transformer VT1, VT2 High-frequency voltage detection transformer S1-S4 Switching element CA, CB Voltage setting capacitor SW1-SW4 switch

Claims (3)

[Claims] 1. A single DC power supply supplies DC power to a plurality of inverter circuits, loads in which operating conditions are different are connected in parallel for each inverter circuit, and the inverter circuits are connected in parallel by switching control of switching elements. In the method for controlling the power supply to the parallel load of the current type inverter that controls the AC power supplied to each load, the operating condition of the switching element in each inverter circuit is set corresponding to the operating condition for each load, The switching timing of each switching element in each inverter circuit is time-division controlled based on the set operating condition, and in this time-division control, the operating condition of the switching element of each inverter circuit in the previous time-division period is stored. Based on the stored operating conditions, each in The parallel condition of the current type inverter characterized in that the operating condition of the switching element of the inverter circuit is set, the switching timing of the switching element of each inverter circuit is controlled, and the AC power supplied to the parallel load is controlled. Power supply control method to load. 2. A single DC power source supplies DC power to a plurality of inverter circuits, loads of which operating conditions are different are connected in parallel to each inverter circuit, and the inverter circuits are connected in parallel by switching control of switching elements. In the supply power control device for controlling the AC power supplied to each load, operating condition setting means for setting the operating condition of the switching element in each inverter circuit corresponding to the operating condition for each load, and the set operation A supply power control device comprising: a control unit that time-divisionally controls the switching timing of each switching element in each inverter circuit based on a condition. 3. The control means stores, in the time division control, operating conditions of a switching element of each inverter circuit in a previous time sharing period, and based on the stored operating conditions, each control unit in the current time sharing period. A supply power control device characterized in that the operating condition of a switching element of an inverter circuit is set, the switching timing of the switching element of each inverter circuit is controlled, and AC power supplied to a parallel load is controlled.