JP3961817B2 - Double voltage inverter device - Google Patents

Description

[0001]
The present invention relates to a voltage doubler inverter device that stabilizes operation.
[0002]
[Prior art]
In general, thyristor inverter devices are widely used as high-frequency power sources for induction heating furnaces. This thyristor inverter device is configured as shown in FIG. In the figure, 1 is a rectifier that converts three-phase AC power into DC power, 2 is a DC reactor, 3 to 6 are thyristors, 7 is a capacitor, and 8 is a load coil. The DC reactor 2 functions to smooth the DC current and to maintain the current. Further, alternating power is supplied to the capacitor 7 and the load coil 8 by alternately turning on the pair of thyristors 3 and 6 and 4 and 5.
[0003]
The operation as this inverter will be described. Since the thyristors 3 to 6 do not have a self-extinguishing capability, they are turned off by the capacitor 7 provided on the load side. That is, when the thyristors 3 and 6 are turned on and the capacitor 7 has the polarity shown in the figure, when the thyristors 4 and 5 are turned on, the charge of the capacitor 7 is discharged through the thyristors 5 and 6. When the current becomes zero, the thyristor 6 turns off.
[0004]
In the path of thyristors 4 and 3 as well, the charge of capacitor 7 is discharged, so that thyristor 3 similarly turns off. When the thyristors 4 and 5 are on, the polarity of the capacitor 7 changes to the opposite polarity to that shown in the figure. Next, when the thyristors 3 and 6 are turned on, the thyristors 4 and 5 are similarly turned off. In this way, the thyristor is alternately turned on and off by the action of the capacitor 7 and the operation as an inverter is performed.
[0005]
If the reverse voltage is not applied for a predetermined time after the current becomes zero, the thyristor does not completely recover the off capability. Therefore, securing this reverse voltage time is most important in this type of inverter. In general, this reverse voltage time is called a commutation margin angle or a commutation margin time. This angle or time is equal to the current advance angle or lead time with respect to the voltage. Strictly speaking, the overlap time must be taken into account, but since it is not essential, the description is omitted. FIG. 5 shows voltage and current waveforms on the output side of the inverter. It is important that the current is advanced by a certain angle γ or time with respect to the voltage.
[0006]
A typical example of the load coil is an induction furnace. In this process, the impedance of the induction furnace changes greatly in the process from when the metal material is put into the induction furnace until the melting is completed and all the molten metal is taken out. Regardless of this change in impedance, it is important for the inverter to always ensure the necessary commutation margin angle or time. For this reason, the load voltage or current is detected, and the frequency is automatically adjusted so that the phase of the current and voltage becomes a constant angle or time.
[0007]
For example, when the frequency increases, the capacitor current increases and the load coil current decreases, so the phase advances. Conversely, when the frequency drops, the phase is delayed. This phase characteristic is shown in FIG. The horizontal axis is the frequency f, and the vertical axis is the phase θ.
[0008]
When the phase characteristic changes from A to B depending on the load condition, the frequency of the intersection of the phase characteristic curve and the predetermined value θ 0 set to the target phase level moves from f A to f B , and the inverter frequency changes. Change . For example, a PLL (phase lock circuit) is used as a control circuit for realizing this.
[0009]
Next, the voltage doubler inverter will be described. FIG. 7 shows a conventional voltage doubler inverter. Actually, this is equivalent to the capacitor 7 of FIG. In FIG. 7, 11 is an inverter, 71 and 72 are capacitors, and their capacities are C1 and C2, respectively. A load coil 8 is an inductive load such as an induction furnace. V1 is an inverter output voltage and V2 is an inductive load voltage.
[0010]
The principle that this circuit doubles the voltage will be described. When C1≈C2 = 2C and the inductance and resistance of the load coil 8 are L and R, respectively, the resonance angular frequency ω is approximately expressed by Equation 1.
[0011]
[Formula 1]
[0012]
FIG. 8 is a vector diagram showing the relationship between C1, C2, L and R. Expressions 2 and 3 are derived from this figure, and the relationship of V2≈2V1 is established.
[0013]
[Formula 2]
[0014]
[Formula 3]
[0015]
Since the voltage doubler inverter device can increase the inverter voltage nearly twice without using a transformer, it is not only economically cost-effective but also reduces noise from the transformer and reduces weight. There are merits such as being able to plan. Nevertheless, the actual situation is that it is rarely used, and the cause is thought to be that the inverter does not operate stably. Certainly, a phenomenon may occur in which the frequency suddenly decreases abnormally during melting in an induction furnace. Therefore, the reason why the frequency drops abnormally was investigated.
[0016]
In the circuit of FIG. 7, the impedance Z as viewed from the inverter 11 to the load side is the combined impedance of the series circuit of C2, L, R and C1. When the frequency becomes very low, the series circuit impedance is expressed by Equation 4.
[0017]
[Formula 4]
[0018]
From this relationship, the combined impedance with 1 / ωC1 is approximately 1 / ωC, and exhibits capacitive reactance. On the other hand, when the frequency becomes very high, the series impedance of C2 and the load coil becomes almost ωL, and the combined impedance of this and 1 / ωC1 becomes almost 1 / ωC1 from ωL >> 1 / ωC1, which also reduces the capacitive reactance. Present.
[0019]
Therefore, in the vicinity of the resonance frequency, inductive reactance is exhibited from the capacitive in many cases. However, when the load becomes heavy, that is, when R increases, a situation in which the phase does not become smaller than a certain advance value appears as shown in FIG. As a result, a gate signal for controlling the frequency of the thyristor inverter is created at the frequency of the intersection of the phase characteristic curve and the predetermined value θ 0 set to the target phase level, but the phase is set to the predetermined value θ 0. In the case of A, a frequency of fA exists, but in the case of B, it does not exist. As a result, the inverter cannot operate with a load showing the characteristic of B. Thus, since the cause of sudden instability was not known, the countermeasure was not taken and it is thought that the voltage doubler inverter device was not widely used conventionally.
[0020]
[Problems to be solved by the invention]
The present invention improves the above problems and provides a voltage doubler inverter device suitable for an induction furnace that can be stably operated under any load condition and that has an abnormally low frequency suddenly during heating and melting.
[0021]
[Means for Solving the Problems]
The voltage doubler inverter device according to claim 1 of the present invention includes a first capacitor connected in parallel to the first and second output terminals of the thyristor inverter, a second capacitor having one end connected to the first output terminal, In the voltage doubler inverter device comprising an inductive load connected in series between the other end of the second capacitor and the second output terminal, a phase characteristic curve obtained from the inverter voltage and inverter current of the inverter output voltage signal And a first gate signal generator for creating a gate signal for controlling the frequency of the thyristor inverter at the frequency of the intersection with the predetermined value set at the target phase level, the load voltage of the inductive load voltage signal and the inverter current The frequency of the thyristor inverter at the frequency of the intersection of the phase characteristic curve obtained from A second gate signal generator to create a control gate signal, the two select gate signal having a higher or frequency of the output of the gate signal generators, or thyristors one of the gate signal of the output And a selection circuit for outputting the signal.
[0022]
According to a second aspect of the present invention, the voltage doubler inverter device generates a gate signal for controlling the frequency of the thyristor inverter at the frequency of the intersection of the phase characteristic curve and the predetermined value set at the target phase level. In the second gate signal generator, the predetermined value set to the target phase level is set to a different value in each gate signal generator.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. In FIG. 1, the voltage doubler inverter device has a first capacitor 71 having a capacity C 1 connected in parallel with the first output terminal 91 and the second output terminal 92 of the inverter 11, and one end connected to the first output terminal 91. A second capacitor 72 and a load coil 8 serving as an inductive load connected in series between the other end of the second capacitor 72 and the second output terminal 92 are configured.
[0024]
Further, an inverter voltage detecting transformer 20 is connected to both sides of the capacitor 71, and the inverter output voltage V1 is measured here. A load voltage detecting transformer 21 is connected to both sides of the load coil 8, and the inductive load voltage V2 is measured here. The inverter voltage detection transformer 20 is connected to a first gate signal generator 22 for generating a thyristor gate signal by using an inverter output voltage signal as an input. The load voltage detecting transformer 21 is connected to a second gate signal generator 23 that receives an inductive load voltage signal and generates a thyristor gate signal. As shown in FIG. 2A, the first gate signal generator 22 has a phase characteristic curve θ 1 obtained from the inverter voltage and inverter current of the inverter output voltage signal, and a predetermined phase level set to a target phase level. A gate signal for controlling the frequency of the thyristor inverter 11 is created at the frequency f A1 at the intersection with the value θ A0 . Further, the second gate signal generator 23 sets the frequency f B1 at the intersection of the phase characteristic curve θ2 obtained from the load voltage of the inductive load voltage signal and the inverter current and the predetermined value θ B0 set to the target phase level. A gate signal for controlling the frequency of the thyristor inverter 11 is created .
[0025]
Further, the first gate signal generator 22 and the second gate signal generator 23 are connected to a selection circuit 24. The selection circuit 24 selects one of the outputs of the first and second gate signal generators 22 and 23, whichever has the higher frequency, or outputs one of the output gate signals to the thyristor. It is like that. In the selection circuit 24, a gate signal distributor 25 that alternately outputs gate signals is connected to the thyristors 3 and 6 and the thyristors 4 and 5, and a pulse amplifier 26 is further connected to output the gate signals to the thyristors 3 to 6. It is supposed to be. Reference numeral 27 denotes a starting circuit, which is necessary not only in FIG. 1 but also in FIG. 4 and FIG.
[0026]
The operation of the voltage doubler inverter having the above configuration will be described. Prior to starting the inverter 11, the thyristors 3 and 5 are turned on to short-circuit the direct current, and the current of the direct-current reactor 2 is first raised. Next, the thyristors 3 and 6 are turned on, the thyristor 5 is turned off, the DC short circuit is released, and thereby the operation of the inverter 11 is started. Here, in order to turn on the thyristors 3 and 6 and turn off the thyristor 5, it is necessary that the capacitors 71 and 72 are charged to the illustrated polarity. A circuit for charging the capacitors 71 and 72 is a starting circuit 27.
[0027]
The first and second gate signal generators 22 and 23 are circuits for generating a thyristor gate signal from the waveform of the inverter voltage detection transformer 20 or the load voltage detection transformer 21. Here, the half period of the resonance waveform is calculated from the quarter period waveform from the time when the sinusoidal waveform given from the inverter voltage detection transformer 20 or the load voltage detection transformer 21 crosses 0 to the peak value. This is a circuit for generating the gate signal of the thyristor to be turned on next.
[0028]
As described above, the cause of the frequency abnormality is to generate a signal that has a predetermined value regardless of the load situation in which the phase of the inverter voltage and current cannot be the predetermined value set to the target phase level. It depends. Therefore, in such a case, it is clear that the circuit that controls the phase to the predetermined phase level set to the target phase level is temporarily stopped and another circuit is used, or the value of the predetermined value itself can only be changed. is there.
[0029]
Therefore, in the present invention, a backup signal is made from the signals from the load voltage detecting transformer 21 and the second gate signal generator 23. This will be described in detail based on the phase characteristics shown in FIG. FIGS. 2A and 2B depict the frequency characteristics of θ1 and θ2 when the phase of the inverter output voltages V1 and I is θ1, and the phase of the inductive load voltage V2 and I is θ2. Fig. 2 (A) shows the case when the load is relatively light. There is an intersection between the θ1 curve and the straight line of the predetermined value θA0 set at the target phase level, and the inverter operates at a frequency fA1 where θ1 = θA0. To do.
[0030]
FIG. 2B shows a case where the load is heavy, and there is no frequency satisfying θ1 = θA0. On the other hand, the frequency θ2 = θB0 is fB1 in FIG. 2A and fB2 in FIG. 2B. Here, fB1 <fA1. In other words, even if fB1 is not a frequency at which the phase becomes 0, a phase θB0 is selected so that the frequency becomes fB1 <fA1.
[0031]
Here, in the case of FIG. 2A, fB1 <fA1 means that after a pulse is output from the first gate signal generator 22, a pulse is output from the other second gate signal generator 23 with a slight delay. Note that the pulse comes out only from fA1. The reason is that the inverter is moved by the pulse of the first gate signal generator 22 because the frequency of the inverter is fA1 and not fB1. Next, in FIG. 2B, there is no pulse from the first gate signal generator 22, and the inverter is driven only by the pulse from the second gate signal generator 23. Therefore, the selection circuit 24 is an OR circuit that can output either signal rather than switching between two inputs, or a priority circuit that operates with the earlier pulse.
[0032]
As can be seen from the above description, in the normal operation state, the inverter is operated at a frequency at which the phase θ1 of the inverter voltage and the inverter current becomes the predetermined value θA0 set to the target phase level, but the load becomes heavy and θ1 When the frequency satisfying = θA0 cannot be obtained, the phase shifts to the frequency fB2 satisfying the phase θ2 = θB0 between the load voltage and the inverter current. At this time, since θ1> θA0, there is no problem in the commutation of the inverter.
[0033]
Next, the case of starting will be described. As described above, in the first gate signal generators 22 and 23, the input waveform must be such that a quarter period can be extracted. However, the voltage waveform that appears when the inverter is started is as shown in FIG. As can be seen, the inverter voltage waveform of a is a monotonically increasing (or decreasing) waveform, and the peak value cannot be obtained, and therefore a quarter period cannot be found. On the other hand, a peak value exists in the load voltage waveform of b. From this, the gate signal can be generated by the second gate signal generator 23 if the signal from the load voltage detecting transformer 21 is used at the time of starting. When starting, the phase is set so as to be larger than normal, and after starting, when the phase difference is set to gradually become about 0, it automatically shifts to the pulse generated by the first gate signal generator 22. Can do.
[0034]
The gate signal generator is not limited to the above-described circuit, and for example, a PLL circuit can be used. Even if the gate signal generator is not completely divided into two parts, a part for determining the magnitude of the phase may be shared apart from the input part of the inverter voltage signal and the load voltage signal. When a microcomputer is used, there is no specific circuit called a gate signal generator. However, when the same idea is included in a program, it is included in the present invention.
[0035]
【The invention's effect】
As described above, according to the voltage doubler inverter device of the first aspect of the present invention, two types of circuits for generating a reference for the gate signal of the inverter are provided, and the pulse of the faster frequency of the two gate signal generators is provided. Since the priority circuit is used, switching from one pulse to the other is smoothly performed according to changes in the load state, and stable operation from start to steady and from light load to heavy load is possible. Can be done. As a result, it has been possible to take advantage of the advantages of the voltage doubler inverter, that is, boosting without using a step-up transformer, weight reduction, noise reduction, and cost reduction associated with the transformer not being used.
[0036]
Further, according to the voltage doubler inverter device according to claim 2, two first and second gate signal generators for generating a reference for the gate signal of the inverter are provided, and the predetermined phase level set to the target phase level of each phase is provided. By setting the values to different values, it is possible to reliably generate the gate signal from at least one of them.
[Brief description of the drawings]
FIG. 1 is a circuit configuration diagram showing a voltage doubler inverter device according to an embodiment of the present invention.
FIG. 2A is a waveform diagram showing a phase / frequency characteristic between each voltage of the voltage doubler circuit and an inverter current, and FIG. 2B is a waveform diagram showing a high load state.
FIG. 3 is a waveform diagram of an inverter voltage and a load voltage at start-up.
FIG. 4 is a main circuit configuration diagram of a conventional inverter device.
FIG. 5 is a waveform diagram showing a relationship between an inverter voltage and a current waveform.
6 is a phase / frequency characteristic diagram between inverter voltages and currents in the circuit of FIG. 4;
FIG. 7 is a circuit configuration diagram showing a voltage doubler inverter circuit.
FIG. 8 is a vector diagram showing the reason for double voltage.
FIG. 9 is a waveform diagram showing phase / frequency characteristics between inverter voltage and current in a voltage doubler inverter circuit.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Rectifier 2 DC reactor 3 Thyristor 4 Thyristor 5 Thyristor 6 Thyristor 7 Capacitor 71 Capacitor 72 Capacitor 8 Load coil 11 Inverter 20 Inverter voltage detection transformer 21 Load voltage detection transformer 22 1st gate signal generator 23 2nd gate signal Generator 24 Selection circuit 25 Gate signal distributor 26 Pulse amplifier 27 Start circuit V1 Inverter output voltage V2 Inductive load voltage 91 First output terminal 92 Second output terminal

Claims (2)

A first capacitor connected in parallel to the first and second output terminals of the thyristor inverter; a second capacitor having one end connected to the first output terminal; the other end of the second capacitor; and the second output terminal In a voltage doubler inverter device comprising an inductive load connected in series between the phase voltage curve obtained from the inverter voltage and inverter current of the inverter output voltage signal , and a predetermined value set to the target phase level A first gate signal generator for creating a gate signal for controlling the frequency of the thyristor inverter at the frequency of the intersection, a phase characteristic curve obtained from the load voltage of the inductive load voltage signal and the inverter current, and a target phase level the frequency of the intersection of the set to a predetermined value, the second gate signal onset to create a gate signal for controlling the frequency of the thyristor inverter And a selection circuit that selects one of the outputs of the two gate signal generators, whichever has the higher frequency, or outputs one of the output gate signals to the thyristor. A voltage doubler inverter device. In the first and second gate signal generators for generating a gate signal for controlling the frequency of the thyristor inverter at the frequency of the intersection of the phase characteristic curve and the predetermined value set to the target phase level, the target phase level 2. The voltage doubler inverter device according to claim 1 , wherein the predetermined value set in (1) is set to a different value in each gate signal generator.