JPH0955371A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To etch back an interlayer insulating film whose surface comprises uneven parts so as to enhance the flatness of the film in a semiconductor device which comprises a multilayer interconnection. SOLUTION: A silicon oxide film 3 whose surface comprises uneven parts due to aluminum interconnections 2 is coated with a photoresist film 4. Then, CF4 and H2 are used as etching gases, and an etching-back operation is performed. Oxygen which is generated from the silicon oxide film 3 is reacted with the H2 gas so as to be removed as H2 and the oxygen does not increase the etching rate of the photoresist film 4. Since the flatness of the silicon oxide film 3 is enhanced, the uneven parts are not left on the surface of the silicon oxide film 3, the disconnection of aluminum interconnections 5 and a short circuit between the aluminum interconnections 5 can be prevented, and the reliability of a semiconductor device is enhanced when interconnections are formed in many layers.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor technology, and is particularly suitable for use in flattening the surface of an interlayer insulating film.

[0002]

2. Description of the Related Art In recent years, with higher integration and miniaturization of elements in semiconductor devices, in order to achieve higher speed operation of the device and higher performance of electrical characteristics, for example, multi-layers such as aluminum wiring and refractory metal wiring are used. Is being promoted. As the wiring becomes multi-layered in this way, the upper layer wiring formed on the lower layer wiring and on the interlayer insulating film such as a silicon oxide film having unevenness on the surface is disconnected due to the step due to the unevenness. Alternatively, a defect such as a short circuit between wirings due to a poor resolution of photolithography at the step portion may occur. In order to avoid such a situation and realize multi-layered wiring, it is necessary to flatten the irregularities on the surface of the interlayer insulating film formed on the lower layer wiring.

A so-called etch back method is known as one of the flattening techniques. This etch back method is
A condition that a coating film such as a resist film is formed on the entire surface of an interlayer insulating film such as a silicon oxide film formed on the lower layer wiring and having irregularities on the surface, and the etching rate of the coating film and the interlayer insulating film are the same. Then, dry etching is performed using a gas such as CF ₄ to flatten the surface of the interlayer insulating film.

Further, in order to further improve the flatness by the etch back method, as described in, for example, Japanese Patent Laid-Open No. 5-102144, the etching rate of the silicon oxide film which is the interlayer insulating film is changed to the etching rate of the resist film. A technique is known in which etching is performed under conditions that are larger than the above. According to this method, the resist film applied to the recesses of the silicon oxide film serves as an etching block, especially when the surface roughness of the silicon oxide film is large, so that the flatness of the silicon oxide film is further improved as compared with the conventional etchback method. It is possible.

[0005]

However, according to the above-mentioned conventional etch-back method, the etching rate of the resist film increases due to the effect of oxygen gas generated from the underlying silicon oxide film during the etch-back. This will be described with reference to FIG.

FIG. 3 is a schematic diagram for explaining the conventional etchback method, and shows a state at the time when the underlying silicon oxide film 20 is exposed from the resist film 21 as the etchback progresses. As shown in FIG. 3, when etched back by dry etching using CF _4, oxygen gas is generated by the reaction CF ₄ is the silicon oxide film 20.

This oxygen gas acts to increase the etching rate of the resist film. Therefore, when the etching back is performed under the condition that the etching rates of the resist film 21 and the silicon oxide film 20 are the same, and when the etching rate of the silicon oxide film 20 is larger than the etching rate of the resist film 21, etching is performed. In any case where the backing is performed, it becomes impossible to obtain the flatness of the silicon oxide film 20 which is originally obtained. As a result, the unevenness remains on the surface of the silicon oxide film 20, causing disconnection of the upper layer wiring or short circuit between the wirings, which lowers the reliability of the semiconductor device when the wirings are multi-layered. There was a problem.

Therefore, an object of the present invention is to realize a highly reliable multilayer wiring by flattening an interlayer insulating film having surface irregularities by an etch-back method, which is superior to conventional ones. It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of manufacturing the semiconductor device.

[0009]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device in which the surface of an interlayer insulating film is flattened by etching back. In the above, there is a step of forming a coating film on the interlayer insulating film and a step of adding a reducing gas to an etching gas to etch back the interlayer insulating film and the coating film.

In one aspect of the present invention, the etch back is performed under the condition that the etching rate of the interlayer insulating film is higher than the etching rate of the coating film.

In one aspect of the present invention, the reducing gas is a gas containing at least one selected from the group consisting of hydrogen gas and hydrocarbon gas.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. 1A to 1D are sectional views showing a manufacturing process of a semiconductor device having a multilayer wiring according to the present embodiment. FIG. 2 is a schematic diagram for explaining the state of etch back in the present embodiment.

First, as shown in FIG. 1A, elements such as MOS transistors (not shown) are formed in an element active region on a silicon substrate (not shown), and then a BPSG film 1 is formed on the entire surface. Is reflowed by heat treatment and BPSG
The surface of the film 1 is flattened. Then, a contact hole (not shown) reaching the impurity diffusion layer on the surface of the silicon substrate is formed in the BPSG film 1 and then aluminum (lower wiring) having a wiring width of 1 μm and a film thickness of 1 μm is filled in the contact hole. Al) The wiring 2 is formed.

Next, as shown in FIG. 1B, a silicon oxide film 3 having a thickness of about 1.6 μm is formed as an interlayer insulating film on the entire surface by a CVD method. The thickness of the silicon oxide film 3 is the same as that of the aluminum wiring 2 and the upper wiring 5 to be formed later.
The film thickness may be such that sufficient insulation can be secured between and. By thus forming the silicon oxide film 3 on the aluminum wiring 2, irregularities due to the aluminum wiring 2 are formed on the surface of the silicon oxide film 3. Then, the photoresist film 4 is formed on the entire surface of the silicon oxide film 3.
Are formed by coating. Since this photoresist film 4 has fluidity, its surface is flattened by applying a sufficient amount.

Next, as shown in FIG. 1C, the entire surface is etched back by dry etching using CF ₄ and H ₂ as etching gases. At this time, the flow rate of CF ₄ gas is about 60 sccm, and the flow rate of H ₂ gas is equal to or higher than that of CF ₄ gas. Under this etching condition, the etching rate of the silicon oxide film 3 is about 50% higher than that of the photoresist film 4. The etching rate of the silicon oxide film 3 and the photoresist film 4
The etching back may be performed under the etching conditions such that the etching rate is the same.

When this etch back progresses, the silicon oxide film 3 is exposed on the surface of the photoresist film 4. The state at this time will be described in more detail with reference to FIG. When the silicon oxide film 10 is exposed on the surface of the photoresist film 11, the silicon oxide film 10 reacts with CF _4, and oxygen is released into the etching atmosphere. The reaction formula at this time is shown in Formula (1). CF ₄ + SiO ₂ → SiF ₄ + CO + O (1)

The oxygen released from the silicon oxide film 10 reacts with H ₂ contained in the etching gas to generate H.
₂ O. The reaction formula at this time is shown in Formula (2). H ₂ + O → H ₂ O ↑ (2)

In this embodiment, since H ₂ gas which is a reducing gas is contained in the etching gas, oxygen generated by etching the silicon oxide film 3 may lower the etching rate of the photoresist film 4. Absent. From the viewpoint of preventing the etching rate of the photoresist film 4 from decreasing as described above, the flow rate of the H ₂ gas is preferably 1.5 to 3 times the flow rate of the CF ₄ gas. The H ₂ gas may be added when the silicon oxide film 3 is exposed from the surface of the photoresist film 4.

Next, as shown in FIG. 1D, a silicon oxide film 3 having a thickness of about 0.6 μm is formed on the aluminum wiring 2.
Etch back until is left. At this time,
In the present embodiment, since the etching back is performed under the condition that the etching rate of the silicon oxide film 3 is higher than the etching rate of the photoresist film 4, the silicon oxide film 3 is flattened with the photoresist film 4 remaining. After that, the etching gas is switched to O ₂ , and the remaining photoresist film 4 is removed by etching.

In this etching with O ₂ gas, the silicon oxide film 3 is hardly etched because the difference in the selection ratio between the silicon oxide film 3 and the photoresist film 4 is large. As a result, as shown in FIG. 1E, a silicon oxide film 3 having a sufficiently flat surface is obtained. In addition,
The photoresist film 4 may be removed by ashing.

Next, as shown in FIG. 1 (f), BPSG
Contact holes (not shown) in the film 1 and the silicon oxide film 3
And an aluminum wiring 5 having a wiring width of 1 μm and a film thickness of 1 μm to be an upper layer wiring so as to fill the contact hole.
Are patterned on the silicon oxide film 3. After a while
A protective film or the like is formed on the entire surface of the aluminum wiring 5, and the manufacture of the semiconductor device of this embodiment is completed. A second interlayer insulating film (not shown) may be formed on the silicon oxide film 3, which is an interlayer insulating film, in order to ensure insulation between the upper and lower aluminum wirings 2 and 5.

As described above, in the present embodiment, the H ₂ gas, which is a reducing gas, is added to the etching gas when performing the etch back method. Therefore, this H ₂ gas is removed from the silicon oxide film 3. H ₂ O is produced by reacting with generated oxygen. Therefore, oxygen generated from the silicon oxide film 3 does not increase the etching rate of the photoresist film 4, and the silicon oxide film 3 having excellent flatness can be obtained.
Therefore, no unevenness remains on the surface of the silicon oxide film 3, and the aluminum wiring 5 as the upper layer wiring is not broken or a short circuit occurs between the aluminum wirings 5. As a result, the reliability of the semiconductor device when the wiring is multi-layered can be improved.

Further, the etching rate of the silicon oxide film 3 is 50% higher than that of the photoresist film 4.
%, The photoresist film 4 applied to the concave portion of the silicon oxide film 3 serves as an etching block when the surface of the silicon oxide film 3 has large irregularities. Therefore, the flatness of the silicon oxide film 3 can be further improved.

In this embodiment, C is used as an etching gas.
F ₄ and H ₂ were used, but C ₂ F instead of CF ₄
An etching gas such as ₆ or CHF ₃ may be used. Also, instead of H ₂ , a hydrocarbon gas such as CH ₄ or C ₄ H ₁₀ that reacts with oxygen generated from the silicon oxide film 3 to remove the reaction product as a gas is used. It can also be used. For example, when CH ₄ is used, oxygen released from the silicon oxide film 3 reacts with CH ₄ contained in the etching gas and becomes C ₂ H ₆ and H ₂ O, which are removed. The reaction formula at this time is shown in Formula (3). 2CH ₄ + O → C ₂ H ₆ + H ₂ O ↑ (3)

Further, as the interlayer insulating film, a BPSG film or a PSG film may be used instead of the silicon oxide film 3. Also,
As the coating film, a photoresist film, an X-ray resist film, U
In addition to a resist film such as a V resist film, a film that can ensure the flatness of the surface applied by spin coating or the like may be used.

[0026]

According to the present invention, a reducing gas is added to the etching gas to etch back the interlayer insulating film and the coating film, whereby gases such as oxygen generated from the interlayer insulating film are reduced by the reducing gas. Are removed. Therefore, the gas such as oxygen generated from the interlayer insulating film does not increase the etching rate of the coating film,
An interlayer insulating film having excellent flatness can be obtained. Therefore, unevenness does not remain on the surface of the interlayer insulating film, the upper layer wiring formed on the interlayer insulating film is not broken, and a short circuit between the upper layer wirings does not occur,
It is possible to improve the reliability of the semiconductor device when the wiring is multilayered.

Further, by performing the etching back under the condition that the etching rate of the interlayer insulating film is higher than the etching rate of the coating film, it is formed in the concave portion of the interlayer insulating film especially when the unevenness of the surface of the interlayer insulating film is large. Since the applied film serves as an etching block, it is possible to further improve the flatness of the interlayer insulating film as compared with the conventional etchback method.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a manufacturing process of a semiconductor device having multilayer wiring according to an embodiment of the present invention.

FIG. 2 is a schematic diagram for explaining a state of etch back in FIG.

FIG. 3 is a schematic diagram for explaining a state of a conventional etchback method.

[Explanation of symbols]

 3, 10 Silicon oxide film 4, 11 Photoresist film

Claims (3)

[Claims] 1. A method of manufacturing a semiconductor device in which the surface of an interlayer insulating film is flattened by performing etch back, comprising: a step of forming a coating film on the interlayer insulating film; and a reducing gas as an etching gas. Is added to etch back the interlayer insulating film and the coating film. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the etch back is performed under a condition that an etching rate of the interlayer insulating film is higher than an etching rate of the coating film. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the reducing gas is a gas containing at least one selected from the group consisting of hydrogen gas and hydrocarbon gas. .