JPH0954753A - Computer bus system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the length of a bus up to a range where the transfer of data is secured at a logic level via the bus and regardless of clock cycle. SOLUTION: In the computer bus system including plural devices 3a to 3n connected to a bus, at least one of synchronizing signal oscillation means 6 and 7 is prepared to output the synchronizing signal together with a synchronizing signal transmission means. When one of devices 3a to 3n transmits an information signal to another via the bus, the synchronizing signal used for transmission of the information signal is sent in the same direction as the information signal through the proper arrangement of the means 6 and 7 and the synchronizing signal transmission means.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer bus system used for a computer system or computer application equipment.

[0002]

2. Description of the Related Art In a computer system, a bus system is essential for transmitting various information between devices. Among various signals used in this bus system, the clock frequency for synchronizing the signals affects the operating speed of the entire computer system.

In recent years, with the increase in speed of computers and the shortening of clock frequency, the phase shift caused by the positional relationship between the clock oscillator and each device has become a problem. FIG. 12 is an explanatory diagram in the case where the distance between the slots accommodating the devices is large and the delay cannot be ignored in the computer using the conventional bus system.

FIG. 1 shows the case where the clock is delayed by 1/4 cycle while the signal is transmitted between slot A and slot B. In FIG. 12A, in this computer, a main board 51 and an option card 52 are stored as devices in slots A and B, respectively, and a data bus 53 is connected between the boards 51 and 52.

An oscillator 54 is provided in the slot A, and clock signal lines 55 and 56 from the oscillator 54 are inserted into the main board 51 and the option card 52, respectively. The distance between the slot A and the slot B is about 10 cm.

The signal transmission failure at this time will be described by taking the data transmission phase as an example. Here, when the main board 51 in the slot A reads data from the option card 52 in the slot B, the clock signal line 5
Consider a case in which the transmission direction of the clock transmitted over 6 and the transmission direction of the data transmitted over the data bus are different.

First, since the clock is transmitted from slot A to slot B, there is a clock delay in slot B by the distance between both slots. That is,
The clock in slot A is C as shown in FIG.
Assuming LK-A, the clock in slot B corresponding to this is CLK-B in FIG. That is, in this case, the transmission between slots A and B causes the signal to be delayed by a quarter period with respect to the clock period.

Therefore, in data transmission, in the slot B, the data DATA-BQ shown in FIG. 7B is output toward the slot A in synchronization with the clock CLK-B transmitted with a delay.

This data DATA-BQ is transmitted through the data transmission bus 53 and reaches the slot A side.
Further, the data DATA-AD shown in FIG.

As described above, when the distance between the slots A and B is large and the phase shift (clock skew) of the transmitted clocks is large, the slot A cannot receive data at the correct timing. Here, the correct timing means that the data setup / hold time for the clock is secured.

Therefore, in the above case, as shown in FIG. 12B, since the data DATA-AD is read at the falling edge of the clock CLK-A on the slot A side, the finally read data DATA-AQ is obtained. , And the data DATA-BQ output on the slot B side cannot be guaranteed.

Therefore, as described above,
When the bus is extended to a distance corresponding to 4 cycles, a signal transmission failure will occur. On the other hand, normally, the bus length is limited and used so that the deviation of the phase difference of the clock is sufficiently small with respect to the cycle of the clock.

[0013]

Therefore, in the conventional computer bus system, if the clock cycle is shortened to provide a high data transfer rate, the bus length must be shortened. In this case, a long bus length cannot be supported.

Further, as the computer system is required to operate at higher speed and the clock cycle becomes shorter, the above problem becomes more serious. The present invention has been made in consideration of such a situation, and it is possible to increase the bus length to a range secured at the logic level for data transmission on the bus regardless of the clock cycle. The purpose is to provide a bus system.

[0015]

In order to solve the above problems, the invention according to claim 1 provides a computer bus system of a computer in which a plurality of devices are connected to a bus,
At least one synchronizing signal oscillating means for outputting a synchronizing signal, and a synchronizing signal transmitting means for transmitting the synchronizing signal and running in parallel with the bus are provided, and from one device among a plurality of devices to another device via the bus. When transmitting an information signal, the computer bus system is provided with a synchronizing signal oscillating means and the synchronizing signal means so that the synchronizing signal used for transmitting the information signal is transmitted in the same direction as the information signal.

According to a second aspect of the invention, in a computer bus system of a computer in which a plurality of devices are connected to a bus, when one end side of the bus is an upper side and the other end side is a lower side, A device having a plurality of devices; a sync signal upper transfer means for transmitting a sync signal only from the lower side to the upper side; a sync signal lower transfer means for transmitting the sync signal only from the upper side to the lower side. From the device to another device via the bus, the device position determining means for determining whether the other device is on the upper side or the lower side of the device, and the determination by the device position determining means. Based on the result, when the other device is on the upper side, it is notified that the synchronization signal on the synchronization signal upper transmission means is valid, and when the other device is on the lower side, the synchronization signal lower transmission is performed. And a valid synchronization signal notifying means synchronizing signal on the means to notify to be valid, and a synchronization signal corresponding to the information signal is a computer bus system so as to transmit in the same direction.

Further, the invention according to claim 3 is the invention according to claim 2, wherein the information signal is at least one of a data signal, an address signal, a command signal, an interrupt signal, a bus request signal, and a bus permission signal. This is one computer bus system.

Further, the invention corresponding to claim 4 is:
In the invention corresponding to claim 2, the device position determining means is a computer bus system provided with a location map that associates the computer resources assigned to each device with the physical relative positions of the devices on the bus. .

Therefore, first, in the computer bus system of the invention according to claim 1, a plurality of devices are connected to the bus. Further, the synchronizing signal oscillating means outputs the synchronizing signal, and the outputted synchronizing signal is transmitted by the synchronizing signal transmitting means.

Then, when an information signal is transmitted from one of a plurality of devices to another device via a bus, the synchronization signal used for transmitting the information signal is transmitted in the same direction as the information signal. Oscillation means and the synchronizing signal means are arranged.

Therefore, regardless of the clock cycle, it is possible to increase the bus length to the range secured at the logic level for data transmission on the bus. In the computer bus system of the invention according to claim 2, a plurality of devices are connected to the bus of the bus system.

Next, when one end side of the bus is set to the upper side and the other end side is set to the lower side by the synchronization signal upper transmission means,
The synchronization signal is transmitted only from the lower side to the upper side. On the other hand, the synchronization signal lower transmission means transmits the synchronization signal only from the upper side to the lower side.

Further, when an information signal is transmitted from a device having a plurality of devices to another device via a bus, the device position determining means determines whether the other device is higher or lower than the device. It is determined whether there is any.

Then, by the effective synchronization signal notifying means,
When the other device is on the upper side, the synchronization signal on the synchronization signal upper transfer means is notified, and when the other device is on the lower side, the synchronization signal on the synchronization signal lower transfer means is effective. Will be notified.

Therefore, the information signal and the corresponding synchronizing signal are transmitted in the same direction, and the bus length is extended to the range secured at the logic level for data transmission on the bus regardless of the clock cycle. Is possible.

Further, in the computer bus system of the invention according to claim 3, the same operation as in the invention according to claim 2 is achieved, and the information signal is a data signal, an address signal, a command signal, an interrupt signal, a bus. It is at least one of a request signal and a bus grant signal, and similar effects can be obtained for bus arbitration, for example.

Furthermore, in the computer bus system of the invention according to claim 4, the same operation as in the invention according to claim 2 is achieved, and in addition, the device position determination means is used for the computer resources and devices assigned to each device. Since the location map relating the physical relative position on the bus is provided, it is possible to surely carry out the same-direction transmission of the information signal and the corresponding synchronization signal.

[0028]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below. (First Embodiment of the Invention) FIG. 1 is a block diagram showing an example of a computer system using a computer bus system according to an embodiment of the first invention.

The computer system shown in the figure includes a bus section 1 including various signal lines, and a plurality of slot connectors 2a, 2b ,. . .
2n (hereinafter represented by 2x) and devices 3a, 3 provided corresponding to these slot connectors 2x
b,. . . 3n (represented below by 3x) and other peripheral elements (not shown).

The bus portion 1 is provided with terminal portions 4 and 5 at both ends thereof, one of which is an upper side and the other of which is a lower side. An upper oscillator 6 is provided in the upper terminal 4 of the bus unit 1, and a lower oscillator 7 is provided in the lower terminal 5.

Various signal lines are provided in the bus section 1, and the signal lines are connected to the device 3x via the slot connector 2x. FIG. 2 shows a detailed configuration of the bus section 1.

FIG. 2 is a diagram showing the configuration of the bus section of the computer bus system according to this embodiment. FIG.
As shown in (c), the clock signal line 8 is provided in the bus section 1.
D, 8U, effective clock signal lines 9D, 9U, and information transmission signal line 10 are provided.

First, FIG. 3A shows the transmission of the clock signal. The upper oscillator 6 is a lower transmission clock CLK_ transmitted from the upper side of the bus unit 1 to the lower side.
D is output to the lower-side terminal unit 5 via the clock signal line 8D.

The lower oscillator 7 outputs the upper transfer clock CLK_U transmitted from the lower side of the bus unit 1 to the upper side to the upper terminal unit 6 via the clock signal line 8U. Next, FIG. 2B shows a clock valid signal indicating which of the transmitted clock signals is valid.

When some information is transmitted through the information transmission signal line 10, the information transmission signal line 10
The above information is synchronized with either the lower transfer clock CLK_D or the upper transfer clock CLK_U. Which of these clocks is valid depends on the lower clock valid signal CLK_ transmitted on the valid clock signal lines 9D and 9U.
D_ENB or higher clock valid signal CLK_U_
Indicated by ENB.

Further, FIG. 2 (c) illustrates the information to be transmitted. That is, the information transmitted on the bus unit 1 is data, addresses, bus request / response signals, command signals, interrupt signals, etc., and each of these bus signal groups actually passes over the data bus, address bus, etc. For the sake of simplification of the description, it is represented here that each bus signal group is transmitted on the information transmission signal line 10 as a representative.

Next, each device 3x shown in FIG. 1 is provided with a location map 11, a data transmission section 12 and a data reception section 13. Location map 11
Stores information about which slot connector 2x has a device having a target resource (memory space, I / O space, interrupt, etc.) when transmitting information such as data transmission or address transmission. .

FIG. 3 is a diagram showing an example of the location map in this embodiment. In the figure, the location map 11 shows how the resources of the memory space, the I / O space, and the interrupts are allotted correspondingly to the slot connector numbers.

The data transmission section 12 uses the information transmission signal line 1 in the address transmission phase, the data transmission phase, etc.
Various information is transmitted via 0. In addition, when the device 3x performing data transmission or the like takes the initiative of the bus,
From the location map 11, the physical position of the partner device 3y located on the upper side or the lower side is determined based on the information of the target resource.

Then, the data transmission unit 12 outputs the upper clock valid signal CLK_U_ENB if the target device 3y is located on the upper side, and outputs the lower clock valid signal CLK_D_ENB if located on the lower side. Has become.

The data receiving unit 13 receives the upper clock valid signal CLK_U_ENB or the lower clock valid signal C.
When any one of LK_D_ENB is output and is received, either one of the corresponding upper transmission clock CLK_U or lower transmission clock CLK_D is made valid, and the data, address, etc. transmitted in synchronization with the valid clock are read. It is like this.

The above-mentioned configurations correspond to the configurations in the claims as follows, for example. First, the sync signal upper transmission oscillation means is composed of, for example, the lower oscillator 7 and the clock signal line 8U, and the synchronization signal lower transmission oscillation means is composed of, for example, the upper oscillator 6 and the clock signal line 8D.

The device position determining means is composed of, for example, a location map 11 and a transmitting section 12, and the valid synchronizing signal notifying means is composed of, for example, valid clock signal lines 9D and 9U, a transmitting section 12 and a receiving section 13. It is composed by.

Next, the operation of the computer bus system according to the embodiment of the present invention configured as above will be described. First, in operating a computer using the computer bus system of the present embodiment, it was described in which slot connector 2x a device having computer resources (memory space, I / O space, interrupt, etc.) exists. The location map 11 is created.

If the computer system has an automatic configuration function, the location map 1 is obtained by using the configuration result.
1 can be created.

On the other hand, if the computer system does not have the automatic configuration function, the administrator of the computer inputs the information necessary for creating the location map and causes the location map 11 to be created.

That is, although not particularly shown, the computer system has an information input unit for inputting computer resource allocation information and a location map creating unit for creating the location map 11 based on the information.

Then, the created location map 1
1 is loaded into all devices 3x connected to the bus unit 1 when the computer system is started up. This allows each device to know the physical location of the computer resource.

Next, the start-up is completed, and in the computer system having the location map 11 in each device, various kinds of information transmission using the bus section 1 is performed. When executing the information transmission, the device 3x that intends to execute the information transmission must secure the bus use right.

Which device 3x uses the bus is
This is a problem of bus arbitration, and one of the slot connectors 2x in the computer system is provided with a device 3x (arbiter) having an arbitration function, and this arbiter is the bus arbitration (arbitration).
I do.

Therefore, the device 3 which wants to use the bus
When x obtains the right to use the bus, it sends a request signal to the device 3y serving as an arbiter. The position of the device 3y serving as an arbiter is determined from the location map 11.

At this time, when the position of the device 3y serving as an arbiter is lower than the device 3x which is trying to obtain the bus right, the request signal is output in synchronization with the lower transfer clock CLK_D. If the request is accepted,
The device having the bus arbitration function returns a response signal in synchronization with the upper transfer clock CLK_U.

On the other hand, if the position of the arbiter device 3y is higher than the position of the device 3x that is trying to obtain the bus right, the request signal is output in synchronization with the upper transfer clock CLK_U.

When the request is accepted, the device 3y having the bus arbitration function returns a response signal in synchronization with the lower transfer clock CLK_D. When the lower transfer clock CLK_D is valid, the lower clock valid signal CL
The K_D_ENB signal is validated to notify the target device 3x that the lower transfer clock CLK_D is valid.

On the contrary, when the upper transfer clock CLK_U is valid, the upper transfer clock valid signal CLK_U_ENB
Enable signal and clock CLK to target device 3x
Notify that _U is valid.

Next, for example, how the device 3k or 3m having the bus right transfers the data, the address and the like to the device transmitting the information will be described with reference to FIGS. 4, 5 and 6.
This will be described with reference to FIG.

FIG. 4 is a diagram for explaining in principle the information transmission between the devices in this embodiment. As shown in FIG. 3A, for example, when data is transferred from the device 3m to the device 3k located on the upper side, the device 3m
Upper transmission clock CLK_ output from lower oscillator 7
Send data in sync with U.

As shown in FIG. 4B, the clock CLK which is actually the same signal as the upper transfer clock CLK_U.
_Um is input to the device 3m and data DATA-m
Q is output. Therefore, the phases of both are completely the same.

The clock CLK_Um and the data D
The ATA-mQ is transmitted to the device 3k through the signal lines of the bus unit 1, respectively. Therefore, these signals become the clock CLK_Uk and the data DATA-kD, which are the signals with the phase delay shown in FIG. 4B.
Since they transmit almost the same distance, their phase delay amounts are almost the same.

Therefore, when the data DATA-kD is read using the clock CLK_Uk, the device 3
The k can reliably receive the data DATA-kQ of the same data as the output data DATA-mQ.

As described above, since the clock transmission direction is the same as the information transmission direction such as data, long-distance information transmission is possible as long as it is guaranteed at the logic level. 5 and 6
FIG. 6 is an explanatory diagram showing how information is specifically transmitted from the upper side to the lower side and from the lower side to the upper side in the computer bus system of the present embodiment.

In FIG. 5, information is transmitted from the upper device 3k to the lower device 3m. At this time, first, the device 3k for transferring the data / address etc.
After getting the right to use the bus by arbitration,
It is determined from the location map 11 that the position of the target device 3m using the computer resource is on the lower side.

Next, the device 3k transmits the data address and the like in synchronization with the lower transfer clock CLK_D. As shown in FIG. 5B, the lower clock enable signal CLK_D_ENB signal is enabled prior to the information transfer. Then, the target device 3m is notified that the lower transmission clock CLK_D is valid.

The device 3m for receiving the data address receives the data or the like transmitted on the information transmission signal line 10 such as the data bus in synchronization with the lower transmission clock CLK_D.

Therefore, there is no phase difference between the clock CLK_D and the transmission information as described with reference to FIG. On the other hand, in FIG. 6, information is transmitted from the lower device 3m to the upper device 3k.

At this time, first, the device 3m which transfers the data and the address determines from the location map 11 that the position of the target device 3k is on the upper side in the same manner as in the above case.

Next, the device 3m, as shown in FIG. 6 (b), prior to the information transmission, the upper clock valid signal CL.
The K_U_ENB signal is enabled to notify the target device 3k that the upper transfer clock CLK_U is valid, and the data transfer is performed in synchronization with the lower transfer clock CLK_D.
The address etc. are transmitted.

The device 3k for receiving the data address receives the data or the like transmitted on the information transmission signal line 10 such as the data bus in synchronization with the upper transmission clock CLK_U.

Therefore, there is no phase difference between the clock CLK_U and the transmission information as described with reference to FIG. The above description has been made in the case of data (address) transfer, but in the case of other bus phases, such as command, interrupt signal, bus request signal, etc., the same purpose as the data / address transfer phase Considering the position of the device, it operates so that the signal to be sent and the clock are in the same direction.

As described above, in the computer bus system according to the embodiment of the present invention, in the computer in which the device 3x is connected to the bus unit 1, the location map 11 that correlates the position of each device and the allocation of computer resources 11
And clock signal lines 8D and 8U parallel to the information transmission signal line 10 and effective clock signal lines 9D and 9U,
When transmitting information from one device to another device, the direction of information transmission and the direction of clock transmission are set to be the same, so that the transmission direction of data / address etc. and the transmission direction of clock can always be the same. The signal transmission delay between two devices can be ignored.

Therefore, the relationship of the AC timing (timing of setup / hold time of data with respect to the clock) is constant regardless of the distance between the two devices, and theoretically, the AC timing shifts even if the distance becomes long. Disappears. It enables long-distance transmission.

Therefore, data or the like can be transmitted within a distance up to the range where the logic level is secured. According to the computer bus system of the present invention, the speed of the computer becomes higher and higher, and even if the clock frequency thereof becomes higher, the AC timing does not shift, and it is possible to cope with the higher speed. (Second Embodiment of the Invention) FIG. 7 is a block diagram showing an example of a computer system using a computer bus system according to an embodiment of the second invention. The same reference numerals are given and detailed description is omitted.

In the present embodiment, the device 2x in the computer system of the first embodiment is replaced with the main board Mb or the option card Oc, which is substantially the same.

Further, in the present embodiment, the number of slot connectors is 4, and each slot connector 2
A main board Mb and option cards Oc1, Oc2 and Oc3 are provided for a, 2b, 2c and 2d. The main board Mb is located on the uppermost side, and the option card Oc3 is located on the lowermost side.

On the other hand, in the present embodiment, the oscillator 1
4 is provided only in the main board Mb, and the terminating end of the bus 1'is limited to the lower terminating end 5 '. FIG. 8 is a diagram showing the configuration of the bus unit of the computer bus system in this embodiment.

In the figure, the clock signal is output from the oscillator 14 in the main board Mb and transmitted to the lower side as the lower transmission clock CLK_D through the clock signal line 8D. This same clock signal is sent to the lower terminal 5 '.
And returns the clock signal line 8U as the higher-order transmission clock CLK_U toward the upper side,
It terminates at the termination 4'in the main board Mb.

The lower clock valid signal CLK_D_ENB or the upper clock valid signal CLK_U_ENB transmitted on the valid clock signal lines 9D and 9U and the signal transmitted on the information transmission signal line 10 are the same as those in the first embodiment. It is similar to the case. However, in the case of the present embodiment, the terminal part is only the lower-side terminal part 5 '.

The signal transmitter 12a shown in FIG.
It is a signal output portion in the data transmission unit 12 in each device shown in FIG. 7. Each device, that is, main board Mb, option cards Oc1, Oc2, Oc3
In the same manner as in the first embodiment, the location map 11, the data transmission unit 12, and the data reception unit 13 are included.
And are provided, and each unit performs similar processing.

FIG. 9 is a diagram showing an example of the location map in this embodiment. In the case of this embodiment,
Since only four slot connectors 2x are provided, computer resources are allocated to these four devices.

In addition to the above processing units, the main board M
The b has a processing function of performing arbitration management for the bus unit 1, and also serves as an arbiter.
The computer bus system according to the embodiment of the present invention configured as described above operates similarly to the computer bus system according to the first embodiment.

In the present embodiment, the main board M
The location map is created by the operation of b and the operating system of the computer system.
Further, since the main board Mb located at the highest level controls the arbitration, when the option board Oc obtains the right to use the bus, the clock C is issued to the main board Mb.
A request signal is sent in synchronization with LK_U.

When the request is accepted, the main board Mb returns a response signal to the requesting option card Oc in synchronization with the clock CLK_D. Less than,
The device that has acquired the bus right transmits information in the same manner as in the case of the first embodiment.

As described above, the computer bus system according to the embodiment of the present invention has the same configuration and operation as the computer bus system according to the first embodiment of the present invention, and also has a clock signal line as a termination unit. 5 ', the upper transmission direction is the clock signal line 8U, and the lower transmission direction is the clock signal line 8
Since it is set to D, the same effect as that of the computer bus system according to the embodiment of the first invention can be obtained, and the number of oscillators 14 can be one, and an inexpensive and simple configuration can be realized. (Third Embodiment of the Invention) FIG. 9 is a block diagram showing an example of a computer system using a computer bus system according to an embodiment of the third invention. The same reference numerals are given and detailed description is omitted.

This computer system is provided with a bus section 1 "including various signal lines, and the slot connectors 2a, 2b ,. . . Two
n (2x) and the devices 3a ', 3b', ... Provided corresponding to these slot connectors 2x. . . 3n '
(Hereinafter, represented by 3x ') and other peripheral elements (not shown).

FIG. 11 is a diagram showing the configuration of the bus section and a part of the device in this embodiment. As shown in the figure, the bus section 1 "is provided with a clock signal line 8, an effective clock signal line 9 and an information transmission signal line 10, and both ends thereof are terminated by termination sections 4" and 5 ". .

On the other hand, as shown in FIG.
x ′ is provided with a data transmission unit 12 ′ and a data reception unit 13 ′, respectively, and further, the data transmission unit 12 ′
An oscillator 14 that outputs a clock CLK is provided at the position ′.

Further, the signal transmitting section 12a 'includes an oscillator 14
And outputting a clock valid signal CLK_ENB and an information transfer signal indicating that the clock is valid,
It is a signal output portion in the data transmission unit 12 '.

The above-described configurations correspond to the configurations in the claims as follows, for example. First, the synchronization signal transmission / oscillation means is composed of, for example, the oscillator 14, and the synchronization signal transmission means is composed of, for example, the clock signal line 8.

In the computer bus system thus configured, a certain device 3x 'acquires the bus right,
When transmitting a signal via the information transmission signal line 10, the data transmission unit 12 'outputs the clock CLK and validates the clock valid signal CLK_ENB before transmitting the data address or the like.

At this time, since the clock CLK and the data address are output from the same device 3x, the clock CLK and the data address are transmitted in the same direction when viewed from any slot on the bus section 1 ", resulting in a phase shift between the two. Absent.

As described above, in the computer bus system according to the embodiment of the present invention, the oscillator 1 is provided in each device 3x '.
Since the clock signal is also output from the device 3x 'when transmitting information, the transmission direction of the data / address etc. and the transmission direction of the clock can always be the same, and the signal transmission between the two devices is provided. You can ignore the delay.

Therefore, AC timing (data setup / hold time timing relative to the clock)
The relationship between two devices, regardless of distance
It becomes constant, and theoretically, there is no AC timing deviation even if the distance becomes long. It enables long-distance transmission.

Further, it is not necessary to provide the effective clock signal lines 9D and 9U and the location map 11, and the structure can be simple. The present invention is not limited to the above embodiments, and can be variously modified without departing from the gist thereof.

[0094]

As described in detail above, according to the present invention, both upper and lower clock signal lines are provided in parallel with the signal line for transmitting information, and both signals are transmitted in the same direction.
It is possible to provide a computer bus system capable of increasing the bus length to the range secured at the logic level for data transmission on the bus, regardless of the clock cycle.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an example of a computer system using a computer bus system according to an embodiment of the first invention.

FIG. 2 is a diagram showing a configuration of a bus unit of the computer bus system according to the embodiment of the present invention.

FIG. 3 is a diagram showing an example of a location map according to the embodiment of the present invention.

FIG. 4 is a diagram for explaining in principle information transmission between devices according to the embodiment of the present invention.

FIG. 5 is an explanatory diagram showing how information is transmitted from the upper side to the lower side in the computer bus system according to the embodiment of the present invention.

FIG. 6 is an explanatory diagram showing how information is transmitted from the lower side to the upper side in the computer bus system according to the embodiment of this invention.

FIG. 7 is a configuration diagram showing an example of a computer system using a computer bus system according to an embodiment of the second invention.

FIG. 8 is a diagram showing a configuration of a bus unit of the computer bus system according to the embodiment of the present invention.

FIG. 9 is a diagram showing an example of a location map according to the embodiment of the present invention.

FIG. 10 is a configuration diagram showing an example of a computer system using a computer bus system according to an embodiment of the third invention.

FIG. 11 is a diagram showing a configuration of a bus unit of the computer bus system according to the embodiment of the present invention.

FIG. 12 is an explanatory diagram in the case where the distance between slots in which devices are accommodated is large and the delay cannot be ignored in a computer using a conventional bus system.

[Explanation of symbols]

1 ... Bus section, 2a, 2b ... Slot connector, 3a, 3
b ... device, 6 ... upper oscillator, 7 ... lower oscillator, 8,
8D, 8U ... Clock signal line, 9, 9D, 9U ... Effective clock signal line, 10 ... Information transmission signal line, 11 ... Location map, 12 ... Data transmitting unit, 13 ... Data receiving unit, Mb ... Main board, Oc1, Oc2, Oc3 ... Option card.

Claims (4)

[Claims] 1. A computer bus system of a computer comprising a plurality of devices connected to a bus, wherein at least one synchronization signal oscillating means for outputting a synchronization signal, and synchronization for transmitting the synchronization signal and running in parallel with the bus. A signal transmission means, and when an information signal is transmitted from one device of the plurality of devices to another device via the bus, a synchronization signal used for transmitting the information signal is transmitted in the same direction as the information signal. A computer bus system in which the synchronizing signal oscillating means and the synchronizing signal means are arranged in such a manner. 2. A computer bus system of a computer comprising a plurality of devices connected to a bus, wherein one end side of the bus is an upper side and the other end side is a lower side. Only, a sync signal upper transfer means for transferring a sync signal, a sync signal lower transfer means for transferring a sync signal only from the upper side to the lower side, and from one device of the plurality of devices to another device When transmitting an information signal via the bus, a device position determination unit that determines whether the other device is on the upper side or the lower side of the certain device, and the determination result of the device position determination unit Based on the above, when the other device is on the upper side, the synchronization signal on the synchronization signal upper transmission means is notified as valid, and when the other device is on the lower side. A valid synchronizing signal notifying unit for notifying that the synchronizing signal on the lower synchronizing signal transmitting unit is valid, and the information signal and the corresponding synchronizing signal are transmitted in the same direction. Bus system. 3. The computer bus system according to claim 2, wherein the information signal is at least one of a data signal, an address signal, a command signal, an interrupt signal, a bus request signal, and a bus permission signal. . 4. The device position determination means is provided with a location map that associates computer resources assigned to each device with a physical relative position of the device on the bus. The computer bus system according to item 2.