JPH0954629A - Microcomputer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the microcomputer which can generate a CPU clock of high frequency precision at low cost. SOLUTION: Commercial AC electric power 142 which is divided by resistances R4 and R5 is inputted to the AC input circuit 203 of the microcomputer 201 through a capacitor C5 and the AC input circuit 203 generates a reference signal synchronized accurately with the commercial AC electric power 142. This reference signal is inputted to a multiplying circuit 202, which multiplies the reference signal up to a desired frequency and inputs the multiplied signal to a clock generating circuit 102. Further, the clock generating circuit 102 generates a two-phase clock according to the signal supplied from the multiplying circuit to drive a CPU 103. Consequently, the microcomputer 201 can be placed in operation with the clock of high frequency precision synchronized accurately with the commercial AC electric power.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer, and more particularly to a microcomputer which generates a clock for a CPU (central processing unit) from a commercial AC power source and uses the clock.

[0002]

2. Description of the Related Art Conventionally, from a microcomputer to a CPU
As a method for generating a clock for the clock signal, a method using a crystal oscillation circuit as a reference signal source, a method using a CR oscillation circuit, a method using a commercial AC power supply, and the like have been proposed.

First, a first conventional example using a crystal oscillator circuit as a clock reference signal source will be described with reference to FIG. The crystal oscillator circuit is the microcomputer 1
01 is built in the inverter 105 and a resistor R1 and a resonance circuit composed of a crystal oscillator 110 and capacitors C1 and C2. The obtained oscillation output is shaped by an inverter 106. The clock generation circuit 102 outputs the output Cout of the inverter 106.
2 phase clocks CLK1 and C that do not overlap each other
LK2 is generated and supplied to the CPU 103 as a two-phase clock. Here, FIG. 19 shows the clock generation circuit 102.
20 is a circuit diagram of FIG. 20. The two-phase clocks CLK1 and CLK2 generated by the clock generation circuit 102 in response to the output signal Cout of the inverter 106 do not overlap each other.
3 is a timing chart showing the timing of FIG. The method of generating a reference signal using such a crystal oscillator circuit can obtain a clock with high frequency accuracy, but has the drawback of increasing the cost by using a crystal oscillator.

Next, a second conventional example will be described with reference to FIG.

In FIG. 21, the same reference numerals and symbols as in FIG. 18 indicate the same components and signals. The oscillation output Cout obtained by the CR oscillator 124 is supplied to the clock generation circuit 102, and as a result, two-phase clocks CLK1 and CLK2 that do not overlap each other are generated, and the CPU1
It is supplied to 03.

FIG. 22 shows the CR oscillator 12 included in FIG.
4 is a specific circuit configuration diagram of FIG. 4, and FIG.
It is a signal waveform diagram which shows the oscillation waveform of 24. In FIG. 22, when the output of the inverter 132 changes, the exclusive OR circuit 135 generates a one-shot pulse having a pulse width corresponding to the delay time determined by the delay circuit 134 formed by connecting a plurality of inverters in series.

Next, the operation of the CR oscillator 124 when the oscillator input Oin is at the power supply potential at the time t0 in FIG. 23 will be described with reference to FIGS. 21, 22 and 23.
When the output of the clocked inverter 136 that constitutes the CR oscillator 124 of FIG. 21 is in the high impedance state, the inverter 130 outputs the GND potential, so that the electric charge stored in the capacitor C3 is discharged through the resistor R2. With the discharge, the potential of the oscillator input Oin decreases with the time constant determined by the capacitor C3 and the resistor R2.
When the input threshold voltage of the inverter 131 is reached at 1, the output of the inverter 131 changes from low level to high level, the output of the inverter 132 changes from high level to low level, and the output Oout of the inverter 130 changes from low level to high level (power supply potential). At the same time, the exclusive OR circuit 135 outputs a one-shot pulse corresponding to the delay time determined by the delay circuit 134, so that the clocked inverter 136 outputs the GND potential and the potential of the oscillator input Oin is lowered to the GND potential during this period. .

After that, when the clocked inverter 136 is in the high impedance state, the potential of the oscillator input Oin rises because the inverter 130 outputs the power source potential, and reaches the input threshold voltage of the inverter 131 at time t2 in FIG. , The output of the inverter 131 is changed from high level to low level, the output of the inverter 132 is changed from low level to high level,
The output Oout of outputs the GND potential. At the same time, the exclusive OR circuit 135 outputs a one-shot pulse corresponding to the delay time determined by the delay circuit 134. Therefore, the clocked inverter 136 outputs the power supply potential during this period and the potential Oin of the oscillator input is raised to the power supply potential. It returns to the initial state. After that, the above-described operation is repeated to obtain the oscillation output Cout. The clock generation circuit 102 generates two-phase clocks CLK1 and CLK2 that do not overlap each other from the oscillation output Cout and supplies them to the CPU 103 as in the first conventional example.

The second conventional example has the advantage that the external parts required for oscillation are the resistor R2 and the capacitor C3, and the manufacturing cost is low, but both the resistance value of the resistor R2 and the capacitance value of the capacitor C3 are low. There is a problem that high frequency accuracy cannot be obtained because the variation is large and the temperature coefficient is large, and the accuracy of the oscillation frequency depends on the resistor R2 and the capacitor C3. Generally, in a microcomputer, the higher the clock frequency for driving the CPU, the shorter the processing time, and the larger the processing capability. On the other hand, when the clock frequency becomes higher than the performance of the CPU, the CPU cannot process. Therefore, when determining the constant of the oscillator, even if all the components of the circuit related to generating the clock, including the microcomputer, are scattered at the higher oscillation frequency, the clock frequency becomes CP.
It is necessary to decide not to exceed the performance of U.
Therefore, when the accuracy of the oscillation frequency cannot be obtained as in the CR oscillator, the constants of the components forming the oscillator must be determined with a margin, and the processing capacity of the microcomputer cannot be used sufficiently. Of course, in this case, it is impossible to realize the clock function using a microcomputer.

Further, as shown in FIG. 24, a third conventional example in which a clock is generated by a CR oscillator and a clock function is realized by a microcomputer is disclosed in Japanese Patent Laid-Open No. 56-147092.

In this conventional example, the clock of the CPU of the microcomputer 143 is generated by the oscillation circuit 141 whose oscillation frequency depends on the resistor R3 and the capacitor C4, and the clock operation is performed from the commercial AC power source 142 through the clock input circuit 140. The frequency of the power supply is controlled by the microcomputer 143.
The time is displayed on the display unit 144 of the clock by taking in the data. The frequency of the commercial AC power supply is carefully controlled by the electric power company, so it has sufficient accuracy to realize the clock function. Therefore, a sufficiently practical timepiece can be obtained in this conventional example.

On the other hand, in this conventional example, since the CPU is driven by the clock obtained by the CR oscillator, the variation of the clock frequency is large similarly to the microcomputer 121 of FIG. 21, and the constants of the components constituting the oscillator must be determined with a margin. I have to. Therefore, the processing capacity of the microcomputer cannot be fully used. Moreover, noise is generally superimposed on the commercial AC power supply, and this noise causes a malfunction of the clock input circuit, and there is a problem that a reference pulse accurately synchronized with the commercial AC power supply cannot be generated. Generally, household devices require severe cost reduction, but in general, ICs including microcomputers are required.
If the number of terminals is large, the cost will increase accordingly. This conventional example requires a terminal for taking in the frequency of the commercial AC power supply from the clock input circuit 140 in addition to the oscillation circuit 141 for obtaining the clock of the CPU, which is disadvantageous in terms of cost.

[0013]

Since the crystal oscillator is used in the first conventional example, a clock with high frequency accuracy can be obtained, but there is a problem that the cost becomes high. Further, in the second conventional example, since the only external parts required for the oscillator are the resistors and the capacitors, there is an advantage that the cost is low, but there is a problem that the accuracy of the oscillation circuit is poor and the performance of the CPU cannot be sufficiently brought out. . Furthermore the third
In the conventional example, the accuracy of the clock is sufficiently high because the commercial AC power supply is used as the reference signal, but the clock for driving the CPU is generated using the CR oscillator, so that the performance of the CPU is sufficient as in the second conventional example. I can't withdraw. In addition, the watch may malfunction if used in an environment where there is a lot of noise coming from the commercial power supply. As described above, the conventional microcomputer has a problem that it is not possible to achieve both low cost and high processing capability.

Therefore, an object of the present invention is to extract a pulse signal that is accurately synchronized with a commercial AC power source, multiply the pulse signal by a multiplying circuit built in a microcomputer to a clock frequency required for a CPU, and further to perform two-phase. Another object of the present invention is to provide a microcomputer including a clock generation circuit that generates non-overlapping clocks and supplies the clocks to the CPU.

Another object of the present invention is to provide at low cost a microcomputer having a built-in clock generation circuit and a multiplication circuit for supplying a stable clock to the CPU even if noise is superimposed on the commercial AC power supply. .

[0016]

Therefore, the microcomputer according to the present invention comprises an extracting means for extracting a reference signal synchronized with the commercial AC power source and a multiplying means for multiplying the reference signal extracted by the extracting means. And clock generating means for obtaining a plurality of clocks that do not overlap each other from the output signal of the multiplying means, and the multiplying means includes
Frequency dividing means for dividing the output signal of the means; a phase difference between the output signal of the extracting means and the output signal of the frequency dividing means is detected, and the phase of the output signal of the extracting means is the output signal of the frequency dividing means. The first control signal is output when the phase is advanced with respect to the phase, and the second control signal is output when the phase of the output signal of the extracting means is delayed with respect to the phase of the output signal of the frequency dividing means. A phase comparator for outputting; an output voltage lower than an output voltage in a balanced state in response to the first control signal, and an output voltage lower than an output voltage in the balanced state in response to the second control signal. A low-pass filter to be increased; and an output signal of the multiplying means as an output signal, and when the output voltage of the low-pass filter becomes higher than the output voltage in the balanced state, oscillates more than the oscillation frequency in the balanced state. frequency And a voltage controlled oscillator that raises the oscillation frequency higher than the oscillation frequency in the balanced state when the output voltage of the low pass filter becomes lower than the output voltage in the balanced state. .

Further, a microcomputer according to another embodiment of the present invention comprises an extracting means for extracting a reference signal synchronized with a commercial AC power source and a multiplying means for multiplying the reference signal extracted by the extracting means. And a clock generating means for obtaining a plurality of clocks that do not overlap each other from the output signal of the multiplying means, wherein the multiplying means divides the output signal of the means, and the output signal of the extracting means. A phase comparator that detects the phase difference between the output signals of the frequency dividing means and outputs a control signal according to this phase difference; a low-pass filter that receives the control signal of the phase comparator as an input signal;
When the commercial AC power supply is switched from a positive voltage to a negative voltage or from a negative voltage to a positive voltage, the output signal of the multiplication means is used as an output signal, and the commercial AC power supply includes a voltage controlled oscillator that controls the oscillation frequency by the output voltage of the low pass filter. And a means for holding the input signal of the multiplying means between the extracting means and the multiplying means in a period other than immediately before and immediately thereafter.

[0018]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

In the present embodiment, the commercial AC power source divided by the resistors R4 and R5 is input to the AC input circuit 203 of the microcomputer 201 via the capacitor C5.

FIG. 2 is a circuit diagram showing a concrete example of the AC input circuit 203. In FIG. 2, the inverter 211 and the inverter 212 are designed to have the same input threshold voltage. The input and output of the inverter 211 are connected, and the input of the AC input circuit 203 is biased to the input threshold voltage of the inverter 211 via the resistor R6. Therefore, the center potential of the AC signal input via the capacitor C5 provided outside the microcomputer 201 matches the input threshold voltage of the inverter 212. The input of the inverter 212 is A with the input threshold voltage of the inverter 212 as the center potential.
Since the C signal is added, when the potential of the AC input is higher than the center potential, the input potential of the inverter 212 is the inverter 21.
2 becomes higher than the input threshold voltage of 2 and the potential of the AC input is lower than the central potential, the input potential of the inverter 212 becomes lower than the input threshold voltage of the inverter 212. As a result, as shown in FIG. 3, the AC input circuit 203 outputs the AC signal of the commercial AC power supply 142 as a reference signal having a digital waveform. By configuring the AC input circuit in this way, it is possible to extract from the commercial AC power supply 142 a digital signal having a high-level and low-level duty ratio with a simple circuit configuration.

FIG. 4 shows a multiplication circuit 20 used in this embodiment.
It is a block diagram which shows an example of 2.

The phase comparator 221 compares the phase of the reference signal f1 with the output signal f2 of the frequency divider 224 and inputs a pulse signal UP bar or Down bar proportional to the phase difference to the low pass filter 222. Low pass filter 222
Supplies the control voltage V1 to the voltage controlled oscillator 223 by smoothing the input pulse signal UP bar or Down bar. The voltage controlled oscillator 223 supplies the oscillation output f3 of the multiplication circuit 202 to the clock generation circuit 102 at the next stage and also supplies the oscillation output f3 to the frequency divider 224. The frequency divider 224 outputs 1 / N of the oscillation output f3, where N is a positive integer.
The divided frequency f2 is supplied to the phase comparator.

Since the multiplication circuit 202 is fed back as a whole so that the reference signal f1 and the output f2 of the frequency divider coincide with each other, it operates as a multiplication circuit which multiplies the reference signal f1 by N and outputs it. Here, as an example, when N = 65536, the oscillation output f3 becomes 65536 times the reference signal f1. If the frequency of the commercial AC power supply is 50 Hz, the output frequency of the multiplication circuit, that is, the oscillation frequency f3 of the voltage controlled oscillator 223.
Is 3.2768 MHz.

Next, the operation of the multiplication circuit 202 will be described in detail for each block.

First, the phase comparator 221 shown in FIG. 5 compares the phases of the reference signal f1 and the output signal f2 of the frequency divider 224, and outputs the output signal UP bar or Down bar equal to the phase difference. FIG. 6A shows a case where the reference signal f1 has a phase advanced as compared with the output signal f2, and FIG. 6B shows a case where the reference signal f1 has a phase delayed as compared with the output signal f2. When the phase of the reference signal f1 is ahead of that of the output signal f2, the phase comparator 221 outputs an UP bar signal equal to the phase difference between the reference signal f1 and the output signal f2, as shown in FIG. 6 (a). On the contrary, when the phase of the reference signal f1 is delayed as compared with the output signal f2, the phase comparator 221 outputs the reference signal f1 and the output signal f as shown in FIG. 6B.
A Down bar signal equal to the phase difference of 2 is output.

Now, when the reference signal f1 is higher than the frequency of the output signal f2, that is, when the reference signal f1 is higher than 1/65536 times the oscillation output f3, the phase of the reference signal f1 is on average the output signal f2. The phase comparator 221 outputs the UP bar signal to the low-pass filter 222 because it is ahead of the phase of.

Next, the operation of the low pass filter 222 will be described with reference to FIG. Phase comparator 221 to U
When the P bar signal is input to the inverter 213, the N type MO
The SFET 232 becomes conductive and the potential of the capacitor C6, that is, the control voltage V1 decreases. On the other hand, when the Down bar signal is input, the P-type MOSFET 231 conducts and the power source Vcc charges the capacitor C6 via the P-type MOSFET 231, so that the control voltage V1 rises. As described above, the low-pass filter 222 lowers the control voltage V1 when the frequency of the reference signal f1 is higher than that of the output signal f2, and conversely controls when the frequency of the reference signal f1 is lower than that of the output signal f2. It operates to increase the voltage V1.

The voltage controlled oscillator 223 receives the control voltage V1 output from the low pass filter 222 and outputs an oscillation output f3 according to the control voltage V1.

Next, the operation of the voltage controlled oscillator 223 will be described with reference to FIGS. 8 and 9. 8 is a block diagram of the voltage controlled oscillator 223, and FIG. 9 is a voltage controlled oscillator 22.
9 is a circuit diagram of the delay circuit 240 used in FIG. 3, and when the Reset signal shown in FIG. 8 is set to “1”, the output of the NOR circuit becomes “0” and the output of the inverter becomes “1”, and therefore the circuit of FIG. Since the N-type MOSFET 252 becomes conductive and the capacitor C7 is discharged, the voltage of the capacitor C7 is fixed at the GND potential, and the voltage controlled oscillator 223 stops oscillating.

Next, when the Reset signal is set to "0", the oscillation output f3 is also set to "0" at the same time.
The gate of the FET 252 becomes "0", and the N-type MOSFE
T252 becomes outrageous. At this time, when the potential of the control voltage V1 is high, the impedance of the P-type MOSFET 251 increases, so that the charging time of the capacitor C7 is slow,
When the potential of the control voltage V1 is low, the P-type MOSFET 25
Since the impedance of 1 becomes smaller, the charging time of the capacitor C7 becomes faster. Therefore, the delay circuit shown in FIG. 9 has a long delay time when the control voltage V1 is high and a short delay time when the control voltage V1 is low. From this, the oscillation output f3 of the voltage controlled oscillator 223 having the ring oscillator configuration in which the delay circuits 240 are connected in series in three stages
When the control voltage V1 is high, the oscillation frequency is low, and conversely, when the control voltage V1 is low, the oscillation frequency is high. Therefore, when the frequency of the reference signal f1 is higher than that of the output signal f2, the control voltage V1 output from the low-pass filter 222 is low, and the voltage-controlled oscillator 223 receives the control voltage V1 to increase the oscillation frequency. Works like.

FIG. 10 is a circuit diagram showing a concrete example of the frequency divider. In this embodiment mode, 16 stages of flip-flops are connected to form a frequency divider for dividing the entire frequency by 65536. The frequency divider 224 divides the oscillation output f3 by 1/65536 and inputs the output signal f2 to the phase comparator 221.

As initially assumed, if the frequency of the reference signal f1 is higher than that of the output signal f2, the phase comparator 22
1 generates an UP bar signal and supplies it to the low pass filter 222. The low pass filter 222 receives the UP bar signal and reduces the control voltage V1. Voltage controlled oscillator 223
Raises the oscillation frequency f3 when the control voltage V1 decreases, and raises the frequency of the output signal f2 via the frequency divider 224. The frequency of the reference signal f1 and the output signal f2 finally match with each other by repeating the above-mentioned operation of the frequency multiplier circuit 202, and the frequency of 65536 times the frequency of the commercial AC power source is stably supplied to the clock generation circuit 102. To do. The microcomputer 201 outputs the output signal f of the multiplication circuit 202.
3, the clock generator circuit 102 generates two-phase clocks CLK1 and CLK2 that do not overlap each other, and the CPU 10
3

In the present embodiment, the frequency of the commercial AC power supply with high frequency accuracy is multiplied to obtain the clock of the CPU 103, so that the clock with high frequency accuracy can be obtained, and the necessary parts are the capacitor C5, Since the resistors R4 and R5 are cheap, the performance of the CPU can be obtained inexpensively and sufficiently.

Next, a second embodiment of the present invention will be described with reference to FIGS. 11, 12 and 13. It should be noted that common reference characters / numerals are given to constituent elements common to FIGS. 1 and 4.

In this embodiment, as in the first embodiment, the commercial AC power source 142 divided by the resistors R4 and R5 is connected to the A of the microcomputer 201 via the capacitor C5.
It is input to the C input circuit 203. AC input circuit 203
Is similar to that of the first embodiment, and commercial AC power source 142
Is output as a reference signal having a digital waveform as shown in FIG.

The multiplication circuit 272 receives the reference signal f1 from the AC input circuit 203 and outputs a 50 Hz reference signal 655.
The oscillation output f3 of 3.276 MHz which is multiplied by 36 is supplied to the clock generation circuit 102.

Referring to FIG. 12, the multiplication circuit 272 is
A phase comparator 221 that detects a phase difference between the reference signal f1 and the output signal f2 of the frequency divider and outputs an output signal UP bar or Down bar equal to the phase difference, and an UP bar or Down bar input from the phase comparator 221. Low-pass filter 222 that generates control voltage V1 according to the pulse width of the signal
And a voltage-controlled oscillator 223 that makes the frequency of the oscillation output f3 variable according to the control voltage V1, and the internal circuit and operation are the same as in the first embodiment.

Further, the frequency divider 224 is the flip-flop 2
The oscillation output f3 output from the voltage controlled oscillator including 61 to 264 is divided by 1/65536, and the output signal f2 is supplied to the phase comparator 221. A, B, and C are outputs of the flip-flops 264 to 262, respectively. Now, the oscillation frequency of the oscillation output f3 is 50 times that of the reference signal.
65536 times Hz, the frequency of the output signal f2 of the frequency divider is 50 Hz, which is the same as that of the reference signal, and the flip-flop 2
The frequency of the output C of 62 is 100 Hz. Further, the multiplication circuit 272 controls the timing of the signal input to the phase comparator 221 by a circuit including the RS flip-flop 265, the flip-flop 266, and the OR circuit 267.

Next, the operation of the multiplication circuit 272 will be described.

First, when the microcomputer 271 is reset, the RS flip-flop 265 is reset and the output Q-bar becomes "1". Therefore, the clock terminal CP of the flip-flop 266 keeps holding “1”, and the reference signal f1 is output as it is to the output Q of the flip-flop 266. The phase comparator 221 uses the reference signal f
1 and the phase of the output signal f2 of the frequency divider are compared, and the reference signal f
If the phase of 1 leads the output signal f2, FIG.
UP signal is generated as shown in FIG.
If the phase of is delayed from the output signal f2,
A Down bar signal is generated as shown in FIG.

The low-pass filter 222 lowers the control voltage V1 when the UP bar signal is input, and conversely increases the control voltage V1 when the Down bar signal is input, and controls the voltage controlled oscillator 223. Then, the voltage controlled oscillator 22
3 operates so as to lower the frequency of the oscillation output f3 when the control voltage V1 increases, and conversely increases the frequency of the oscillation output f3 when the control voltage lowers.
Enter in 4. The frequency divider 224 receives the input oscillation output f
3 is divided to the frequency of the reference signal and the output signal f2 is input to the phase comparator.

Now, the frequency of the reference signal f1 is the frequency divider 22.
4 is higher than the frequency of the output signal f2, the phase of the reference signal f1 leads the phase of the output signal f2. Therefore, the phase comparator 221 inputs the UP bar signal to the low-pass filter 222. . The low pass filter controls the voltage controlled oscillator 223 so that the control voltage V1 is lowered and the frequency of the oscillation output f3 is raised as described above.

Therefore, the frequency of the oscillation output f3 is changed so as to be high and is input to the phase comparator 221 via the frequency divider 224. By repeating such operation,
The multiplication circuit 272 oscillates at 65536 times the frequency of the commercial AC power supply.

Next, the CPU 103 executes the program to set the RS flip-flop 265. When the RS flip-flop 265 is set,
The output Q bar of the RS flip-flop outputs "0", and the flip-flop 266 outputs the value of D which is the input of the flip-flop 266 only when the OR circuit 267 outputs "1". Output from. At other times, the previous value of Q of the flip-flop 266, that is, the previous value of the output of the AC input circuit 203 is held in the flip-flop 266, and the held value is output. The OR circuit 267 becomes "1" because the outputs of the flip-flops 262 to 264 are all 1 as shown in FIG.
Or only when all 0s are output, that is, before and after the AC input changes the polarity from positive to negative or from negative to positive.

As can be seen from the above description, the output of the AC input circuit 203 is the phase comparator 22 during the shaded period in FIG.
Does not reach 1. Therefore, when the RS flip-flop 265 is set, even if accidental noise other than the original AC signal comes from the commercial AC power supply 142 during the hatched period in FIG. 13, it is not transmitted to the phase comparator 221.

Next, the operation of the multiplication circuit 272 when noise is mixed into the commercial power supply will be described with reference to FIG.

In FIG. 14, the signal when the negative voltage noise A is superimposed in the vicinity of the positive peak value of the commercial power source is SA, and the positive voltage noise B is superimposed when the commercial power source is switched from positive to negative. The signal is shown at SB. In addition, the signal SA is AC
The reference signal when input to the input circuit 203 is f1 (S
In A), the reference signal when the signal SB is input to the AC input circuit 203 is indicated by f1 (SB).

Assuming that the multiplication circuit has the circuit configuration shown in FIG. 4, the signal SA is inverted from positive to negative at the time t1 when the noise A is superimposed, so that the reference signal f1 (SA inputted to the phase comparator 221 is changed. ) Is inverted from high level to low level. Therefore, the phase comparator 221 outputs the reference signal f1 (S
The UP bar signal corresponding to the time difference between the fall of A) and the fall of the frequency divider output f2 is generated. Since noise mixes into the commercial power supply at random timing, in the case of the multiplication circuit of FIG. 4, when a large negative pulse is applied near the positive peak value of the commercial power supply like the noise A, the UP bar signal has a width. A wide pulse is input to the low pass filter 222. Therefore, the control voltage V of the low pass filter 222 is
1 greatly decreases so as to increase the frequency of the voltage controlled oscillator 223, and therefore the oscillation frequency of the voltage controlled oscillator 223 deviates greatly from the oscillation output f3 that the voltage controlled oscillator should originally output.

On the other hand, in the case of the frequency multiplier circuit of FIG. 12, even if the noise A is mixed into the commercial power source, the time t1 is within the shaded portion of FIG. 13, the phase comparator 221 is insensitive to the noise, and no noise is generated. Not affected by. Also, noise B
, The reference signal f1 (SB) is affected by noise and the pulse width is expanded. However, the phase comparator 221 causes the reference signal f1 to fall when the output f2 of the frequency divider falls.
Since a Down bar signal equal to the trailing time difference of (SB) is generated, it is input to the low pass filter 222 as a pulse having a narrow width. Therefore, the low-pass filter 222 generates a voltage slightly higher than the control voltage V1 during normal operation, but the pulse width of the Down bar signal is narrow,
The increase in the control voltage V1 is small. Therefore, the oscillation frequency of the voltage controlled oscillator 223 at the time of normal operation is slightly deviated, and the oscillation frequency of the original voltage controlled oscillator 223 is immediately restored.

In the above-mentioned embodiment, as described above, the frequency of the commercial AC power source having high frequency accuracy is multiplied to obtain the CP.
Since the clock of U103 is obtained, a clock with high frequency accuracy can be obtained, and the necessary parts are cheap, such as capacitor C5 and resistors R4 and R5.
The performance of the PU can be sufficiently obtained at low cost. The voltage control oscillator 223 supplies a stable oscillation frequency to the clock generation circuit 102, and the clock generation circuit 102 supplies the CPU 103 as a two-phase clock that does not overlap each other. be able to.

Next, a third embodiment of the present invention will be described with reference to FIGS. 15, 16 and 17. It should be noted that common reference characters / numerals are given to constituent elements common to FIGS. 1 and 4.

In this embodiment, as shown in FIG. 15, the commercial AC power source 142 divided by the resistors R4 and R5 is connected to the A of the microcomputer 281 via the capacitor C5.
The operation is input to the C input circuit 203, but the operation until the output of the AC input circuit 203 is input to the multiplication circuit 282 is the same as in the first and second embodiments.

Referring to FIG. 16, the multiplication circuit 282 is
A phase comparator 221 that detects a phase difference between the reference signal f1 and the output signal f2 of the frequency divider and outputs an output signal UP bar or Down bar equal to the phase difference, and a UP bar or Down bar signal input from the phase comparator 221. It includes a low-pass filter 222 that generates a control voltage V1 according to the pulse width of V and a voltage controlled oscillator 223 that makes the frequency of the oscillation output f3 variable by the control voltage V1. The operation and the internal circuit include the first and second circuits. This is the same as the embodiment.

Further, the frequency divider 224 is the flip-flop 2
61 to 264, and divides the oscillation output f3 output from the voltage controlled oscillator to output the output signal f2 to the phase comparator 221.
To supply. A, B, and C are outputs of the flip-flops 264 to 262, respectively. Further, the multiplication circuit 28
2 is RS flip-flops 265, 291 and 2
The timing of the signal input to the phase comparator is controlled by a circuit including 92, AND circuit 293, and OR circuit 294.

Next, the multiplication circuit 28 used in this embodiment.
The operation 2 will be described with reference to FIGS. 16 and 17.

First, when the microcomputer 281 is reset, the RS flip-flop 265 is reset and the output Q-bar becomes "1". Therefore, the output 294OUT of the logical sum circuit 294 is always "1" regardless of the output signal f2 of the frequency dividing circuit 224, and the logical product circuit 2
Since the output 293OUT of 93 is always "0", R-
The reference signal f1 is input to the set terminal S of the S flip-flop, and the inverted signal f1 bar of the reference signal is input to the reset terminal R. Therefore, the RS flip-flop 29
The reference signal f1 is directly output to the output terminal Q of No. 2. The phase comparator 221 compares the phases of the reference signal f1 and the output signal f2 of the frequency divider, and if the phase of the reference signal f1 leads the output signal f2, as shown in FIG.
If the bar signal is generated and the phase of the reference signal f2 is delayed behind the output signal f2, Do is output as shown in FIG. 6B.
A wn bar signal is generated and applied to the low pass filter 222 as in the first and second embodiments. Further, the voltage controlled oscillator 223 receives the control voltage V1 from the low pass filter 222 to control the oscillation frequency, and inputs the oscillation output f3 to the frequency dividing circuit 224. The frequency divider 224 outputs the oscillation output f
After dividing 3 into the frequency of the reference signal f1, the output signal f2 is input to the phase comparator 221. By repeating such operation, the multiplication circuit 282 supplies the stable oscillation output f3 to the clock generation circuit 102, and the clock generation circuit 10
2, the two-phase clocks CLK1 and CLK2 that do not overlap each other are generated from the oscillation output f3 and are supplied to the CPU 103.

Next, the CPU 103 executes the program to set the RS flip-flop 265 at time t0. When the RS flip-flop 265 is set, the output Q bar of the RS flip-flop outputs "0", and the AND circuit 293 and the OR circuit 294 output the output Q of the RS flip-flop 291 as it is. It outputs to respective outputs 293OUT and 294OUT. The RS flip-flop 292 can be set only when the output 294OUT of the logical sum circuit 294 outputs "1", that is, when the RS flip-flop 291 outputs "1", and the output 29 of the logical product circuit 293 can be set.
It can be reset only when 3OUT outputs "0", that is, when the output 291Q of the RS flip-flop 291 outputs "0". As shown by 291S which is a set terminal of the RS flip-flop 291 in FIG. 17, when the outputs A, B, C, and f2 of the flip-flops 261 to 264 are all “0”, the RS flip-flop 291 is That is, the flip-flop is set in the period between time t3 and time t4, which is slightly before the time when the AC input is expected to change the polarity from negative to positive, and as shown in 291R which is the reset terminal of the RS flip-flop 291. When the outputs A, B, and C of 262 to 264 are "0" and the output signal f2 of the flip-flop 261 is "1", that is, a time t1 which is slightly before the time when the AC input is expected to change its polarity from positive to negative. And is reset in the period between time t2.

Output 29 of RS flip-flop 291
After 1Q becomes "1" between time t0 and time t1 and the RS flip-flop 292 can be set, the reference signal f1 becomes "1" and the RS flip-flop 292 is set.
When "1" is input to the set terminal S of the RS flip-flop 292, the output 291Q of the RS flip-flop 291 becomes "0" between the time t1 and the time t3, and the resetting is possible. Until then, the RS flip-flop 292 continues to hold the output. Further, the output 291Q of the RS flip-flop 291 becomes "0" and R-
After the S flip-flop 292 becomes resettable,
When the reference signal f1 becomes "0" and "1" is input to the reset terminal R of the RS flip-flop 292 to reset the RS flip-flop 292, the output 291Q of the RS flip-flop 291 is next output. Becomes 1 and can be set, the RS flip-flop 292 continues to hold the output.

Thus, the RS flip-flop 29
Reference numeral 2 repeats setting and reset in synchronization with the reference signal, and supplies a signal in synchronization with the reference signal to the phase comparison circuit 221. RS flip-flops 291 and 292
As can be seen from FIG. 17, since setting and resetting do not switch at the same time, spike noise does not occur,
The multiplication circuit 282 can perform stable operation. Further, even if accidental noise other than the original AC signal comes from the commercial AC power supply 142, it is not transmitted to the phase comparator 221. Although noise is often added to the commercial AC power supply 142, in the present embodiment, the influence of the noise on the commercial AC power supply 142 on the voltage controlled oscillator 223 can be significantly reduced. The microcomputer 281 outputs the clock generation circuit 1 from the output of the multiplication circuit 282.
02 to generate two-phase clocks that do not overlap each other
Is being supplied to 103.

In the above-described third embodiment, the frequency of the commercial AC power source having high frequency accuracy is multiplied to the CPU 103.
Since the clock of is obtained, it is possible to obtain a clock with high frequency accuracy, and the necessary parts are capacitors C5,
Since the resistors R4 and R5 are cheap, the performance of the CPU can be obtained inexpensively and sufficiently. Further, it is possible to significantly reduce the influence of noise mixed in the commercial power supply and supply a stable oscillation frequency to the clock generation circuit 102 by the voltage controlled oscillator 223.

[0062]

As described above, according to the present invention, since the frequency of the commercial AC power source having high frequency accuracy is multiplied to obtain the clock of the CPU, it is possible to obtain the clock with high frequency accuracy, and it is necessary. Various parts are also cheap, so CPU
The performance of can be fully obtained at low cost. Further, even when noise is mixed in the commercial AC power supply, the influence of noise can be significantly reduced and stable operation can be performed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram of an AC input circuit used in the first embodiment of the present invention.

3 is a signal waveform diagram for explaining the operation of an AC input circuit 203. FIG.

FIG. 4 is a block diagram showing a configuration of a multiplication circuit 202.

5 is a circuit diagram showing a configuration of a phase comparator 221. FIG.

FIG. 6 is a timing chart for explaining the operation of the phase comparator 221.

FIG. 7 is a circuit diagram showing a configuration of a low pass filter 222.

FIG. 8 is a block diagram showing a configuration of a voltage controlled oscillator 223.

9 is a circuit diagram showing a configuration of a delay circuit 240. FIG.

FIG. 10 is a circuit diagram showing a configuration of a frequency divider 224.

FIG. 11 is a block diagram showing a second embodiment of the present invention.

FIG. 12 is a circuit diagram showing a configuration of a multiplication circuit 272.

FIG. 13 is a signal waveform diagram for explaining the operation of the multiplication circuit 272.

FIG. 14 is a signal waveform diagram for explaining the operation of the multiplication circuit 272 when noise is superimposed on the commercial power supply 142.

FIG. 15 is a block diagram showing a third embodiment of the present invention.

16 is a circuit diagram showing a configuration of a multiplication circuit 282. FIG.

FIG. 17 is a signal waveform diagram for explaining the operation of the multiplication circuit 282.

FIG. 18 is a block diagram showing a first conventional example.

FIG. 19 is a circuit diagram showing a configuration of a clock generation circuit 102.

20 is a timing chart of clocks generated by the clock generation circuit 102. FIG.

FIG. 21 is a block diagram showing a second conventional example.

22 is a circuit diagram showing a configuration of a CR oscillator 124. FIG.

23 is a signal waveform diagram showing an oscillation waveform of the CR oscillator 124. FIG.

FIG. 24 is a block diagram showing a third conventional example.

[Explanation of symbols]

101, 121, 143, 201, 271, 281
Microcomputer 102 Clock generation circuit 103 CPU 105, 106, 130, 131, 132, 133, 2
11,112,213,255 Inverter 110 Crystal oscillator 124 CR oscillator 134,240 Delay circuit 135 Exclusive OR circuit 136 Clocked inverter 140 Clock input circuit 141 Oscillation circuit 142 Commercial AC power supply 144 Clock indicator 202,272, 282 Multiplier circuit 203 AC input circuit 221 Phase comparator 222 Low pass filter 223 Voltage controlled oscillator 224 Frequency divider 231,251 P-type MOSFET 232,252 N-type MOSFET 261,262,263,264,266 Flip-flop 265,291 , 292 RS flip-flop 267, 294 OR circuit 293 AND circuit R1, R2, R3, R4, R5, R6, R7, R8
Resistors C1, C2, C3, C4, C5, C6, C7 capacitors

Claims (2)

[Claims] 1. Extraction means for extracting a reference signal synchronized with this power supply from a commercial AC power supply, multiplication means for multiplying the reference signal extracted by the extraction means, and a plurality of output signals of the multiplication means which do not overlap each other. Clock generating means for obtaining a clock of the frequency dividing means for dividing the output signal of the means, the frequency dividing means for detecting a phase difference between the output signal of the extracting means and the output signal of the frequency dividing means. When the phase of the output signal of the extracting means leads the phase of the output signal of the frequency dividing means, the first control signal is output, and the phase of the output signal of the extracting means is the output of the frequency dividing means. A phase comparator which outputs a second control signal when delayed from the phase of the signal; in response to the first control signal, the output voltage is made lower than the output voltage in the equilibrium state; In response to the control signal A low-pass filter that makes the output voltage higher than the output voltage in the equilibrium state; and an output signal of the multiplying means as an output signal, and the output voltage of the low-pass filter becomes higher than the output voltage in the equilibrium state. When the output frequency of the low pass filter is lower than the output voltage in the balanced state, the oscillation frequency is lower than the output frequency in the balanced state. A microcomputer including a voltage-controlled oscillator for increasing the voltage. 2. An extracting unit for extracting a reference signal synchronized with the power source from a commercial AC power source, a multiplying unit for multiplying the reference signal extracted by the extracting unit, and a plurality of output signals of the multiplying unit that do not overlap each other. Clock generating means for obtaining a clock of the frequency dividing means for dividing the output signal of the means, the frequency dividing means for detecting a phase difference between the output signal of the extracting means and the output signal of the frequency dividing means. A phase comparator that outputs a control signal according to this phase difference; a low-pass filter that uses the control signal of the phase comparator as an input signal; an output signal of the multiplying means that is an output signal, and an output of the low-pass filter Including a voltage controlled oscillator that controls the oscillation frequency by a voltage, when the commercial AC power source switches from a positive voltage to a negative voltage or from a negative voltage to a positive voltage, and immediately before and immediately thereafter. Microcomputer, characterized in that a means for holding an input signal of said multiplying means between the extraction means and the multiplying means.