JPH0951090A - Charge coupled device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the deterioration of a transfer efficiency while increasing the handling charge amount of a transfer unit. SOLUTION: A charge coupled device(CCD) 10 comprises a of electrodes 16 arranged above an impurity diffused layer 12 via a gate insulating film 15, wherein the film 15 is formed in thickness of a range of 20 to 600nm. The potential of the CCD 10 in the case of applying a voltage for storing charge in the layer 12 directly under the electrode 16 is set to a range of the potential to form a depletion layer on the layer 12 to 10V.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge coupled device [hereinafter referred to as CCD. CCD is an abbreviation for Charge-Coupled Device].

[0002]

2. Description of the Related Art A typical conventional CCD will be described with reference to FIG. As shown in FIG.
A P ⁻ type impurity diffusion layer 112 is formed in the N type silicon substrate 111. In addition, the silicon substrate 111
An N ⁺ -type impurity diffusion layer 113 is formed on the surface side of
A P ⁺ -type impurity diffusion layer 114 is provided below the impurity diffusion layer 113. An electrode 116 is formed on the impurity diffusion layer 113 with a gate insulating film 115 interposed therebetween. An insulating film 117 is formed around the electrode 116. The gate insulating film 115 is formed with a relatively thick film thickness (usually about 70 nm).

[0003]

However, the above C
In CD, the amount of charge handled is limited by the thickness of the gate insulating film. The amount of charges to be handled can be increased by thinning the gate insulating film, but the thinning causes a so-called deep potential dip. The potential dip will be described below with reference to FIG. 6 showing the potential of the CCD 110 in the depth direction.

The gate insulating film capacitance Cox when the film thickness of the gate insulating film under the electrode is dox can be expressed by the equation (1).

[0005]

[Number 1] _{Cox = ε 0 · χox · (} s / dox) ··· (1) ( wherein, Cox is the gate insulating film capacitance, epsilon ₀ is the vacuum dielectric constant,
χox represents the relative dielectric constant of the gate insulating film, s represents the area of the gate insulating film in plan view, and dox represents the film thickness of the gate insulating film. )

Therefore, it can be understood from the above equation (1) that the capacitance Cox of the gate insulating film increases as the film thickness dox of the gate insulating film decreases. Here, when the variation amount Δφm of the minimum potential φm when the gate voltage of the adjacent channel is varied by Δφ is calculated, Δφm is (2)
It can be expressed as an expression.

[0007]

[Formula 2] Δφ m = [C ₄ / (C ₁ + C ₂ + C ₃ + C ₄ )] · Δψ (2) (where, C ₁ + C ₂ is the capacitance below the gate insulating film, C ₃ +
C ₄ is a capacitance in the transfer direction adjacent to one gate electrode, C ₄
Represents the transfer direction capacitance on one side adjacent to one gate electrode. )

As represented by the above equation (2), the minimum potential fluctuation amount Δφm is small due to the increase of the gate insulating film capacitance Cox, that is, the increase of the capacitance C ₁ + C ₂ below the gate insulating film. Become. That is, the influence of the capacitance C ₁ + C ₂ is larger than the influence of the transfer direction capacitances C ₃ and C ₄ , so that the fringe electric field in the transfer direction is reduced. As a result, the potential dip generated between the electrodes becomes deeper and the transfer efficiency deteriorates.

Here, transfer deterioration will be described with reference to the potential diagram of FIG. 6 and the potential diagram under the electrode array of FIG.

As shown in FIG. 7, the thickness d ₂ of the insulating film 117 between the electrodes 116 in the thickness direction of the electrodes 116 is formed thicker than the thickness d ₁ of the gate insulating film 115.
The potential below the electrodes 116 is rate-controlled by d ₂ , and the potential between the electrodes 116 becomes locally deep.
When a charge is transferred by applying a bias to the electrode 116 under the transfer section of the CCD, a potential dip δφ is locally generated between the electrodes 116 where the thickness of the insulating film becomes thick.

This potential dip δφ is pulled and weakened by the fringe electric field in the transfer direction. However, thinning the gate insulating film 115 weakens the effect of the fringe electric field and deepens the potential dip δφ. When such a deep potential dip δφ occurs, a large amount of transfer charge is left behind, resulting in large transfer deterioration. This is the main cause of transfer deterioration. Therefore, it is important to reduce the potential dip δφ in order to thin the gate insulating film in order to increase the amount of charge handled.

An object of the present invention is to provide a charge-coupled device which is excellent in increasing the amount of charge handled in the transfer section and preventing deterioration of transfer efficiency.

[0013]

SUMMARY OF THE INVENTION The present invention is a charge-coupled device made to achieve the above object. That is,
A charge-coupled device in which a plurality of electrodes are arranged above a diffusion layer via a gate insulating film, and the gate insulating film is formed to have a film thickness within a range of 20 nm to 60 nm. Further, in the charge-coupled device in which a plurality of electrodes are arranged above the diffusion layer, the potential of the charge-coupled device when a voltage for accumulating charges in the diffusion layer directly under the electrode is applied is the depletion layer in the diffusion layer. It is in the range of not less than 10 V and not less than the potential formed.

In the above charge coupled device, a plurality of electrodes are arranged above the diffusion layer via the gate insulating film, and the gate insulating film is formed to have a film thickness within the range of 20 nm to 60 nm. Therefore, the handling charge amount of the transfer unit is increased. On the other hand, if the gate insulating film is thinner than 20 nm, a tunnel current will flow and it will no longer function as an insulating film. That is, in order to secure the gate breakdown voltage, 2
A film thickness of 0 nm or more is required. On the other hand, if the gate insulating film is thicker than 60 nm, the capacity of the gate insulating film is reduced and the amount of charges handled per unit area is reduced. Therefore, the dynamic range becomes smaller. Therefore, the film thickness of the gate insulating film is set within the above range.

Further, a plurality of electrodes are arranged above the diffusion layer, and the potential of the charge-coupled device when a voltage for accumulating charges is applied to the diffusion layer immediately below the electrode forms a depletion layer in the diffusion layer. The potential dip is small and the transfer efficiency is high because the voltage is in the range of not less than the electric potential and not more than 10 V. On the other hand, if the potential is lower than the potential that forms the depletion layer in the diffusion layer, the charge cannot be stored in the diffusion layer. On the other hand, if the potential exceeds 10 V, the transfer efficiency becomes low, which is not practical. Therefore, the potential is set within the above range.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to the schematic sectional view of FIG. In the figure, a so-called MOS (metal-oxide film-semiconductor) type two-phase drive type charge coupled device (hereinafter referred to as CCD) is shown as a representative.

As shown in FIG. 1, the first conductivity type (for example, N
Type) semiconductor substrate (eg, silicon substrate) 11 front surface side
Has a first conductivity type (for example, N⁺Type) impurities
A diffusion layer 12 is formed, and the diffusion layer 12 is formed immediately below the diffusion layer 12 and is opposite to the first conductivity type.
A second conductivity type that is a conductivity type (for example, P⁺Type) impurity diffusion
Furthermore, a second conductivity type (for example, P ^-
(Type) impurity diffusion layer 14 is formed in the depth direction.
Further, the gate insulating film 15 is formed on the surface of the semiconductor substrate 11.
A plurality of electrodes 16 are partially formed on the upper surface thereof.
Arranged in a wrapping manner with the insulating film 17 in between.
You. In the CCD 10 having the above structure, the gate insulation is performed.
The film 15 has a thickness within the range of 20 nm to 60 nm.
Has been established.

By forming the gate insulating film 15 with the above-mentioned film thickness, the amount of charges handled in the transfer portion is increased.

On the other hand, if the gate insulating film 15 is thinner than 20 nm, a tunnel current will flow and it will not function as an insulating film. For example, the maximum applied voltage to the electrode 16 is 15
When V, the electric field in the gate insulating film 15 is about 7 MV /
If it is not less than cm, a tunnel current flows. Therefore,
A film thickness of 20 nm or more is required to secure the gate breakdown voltage. Further, if the gate insulating film 15 is made too thin, the fringe electric field becomes weak and the transfer efficiency decreases. From this point as well, the gate insulating film 15 needs to have a film thickness within the above range. On the other hand, when the gate insulating film 15 is thicker than 60 nm, the amount of charge handled per unit area decreases and the dynamic range decreases. Therefore, the film thickness of the gate insulating film 15 is set within the above range.

Next, a second embodiment of the present invention will be described with reference to FIG. 1 as in the first embodiment. In the CCD 10 having the configuration shown in FIG. 1, the impurity diffusion layer 1 immediately below the electrode 16 is used.
The potential of the CCD 10 when a voltage for accumulating charges in 2 is applied to the electrode 16 is
2 is set so that the depletion layer exists in a range of not less than the potential and not more than 10V. That is, the potential value is lower than the potential value of the conventional CCD. In other words, the impurity diffusion layer 12 is formed with an impurity concentration such that the above potential is in the above range. The potential becomes 10 V when 0 V is applied to the electrode 16, for example.

Now, the relationship between the potential φ and the concentration N _D of the impurity diffusion layer 12 will be described. Potential φ
Is expressed as the equation (3) from the Poisson equation.

[0022]

## EQU3 ## φ = qN _D Xm ² / (2χ _S ε ₀ ) + qN _D Xm / (χ _S ε ₀ ) + VG (3) (wherein, q is an electron charge and N _D is an impurity diffusion layer) 12 is the impurity concentration, Xm is the depth from the potential interface that minimizes, χ _S is the relative permittivity of the gate insulating film 15, ε ₀ is the vacuum permittivity, and VG is the gate voltage applied to the electrode 16.)

Here, q, Xm, and
Since χ _S and ε ₀ are constant, the equation (3) is expressed as the following equation (4).

[0024]

## EQU4 ## φ = cN _D + VG (4) (where, c = qXm ² / (2χ _S ε ₀ ) + qXm / (χ _S
ε ₀ ) = constant. )

Therefore, it can be seen that the potential φ is proportional to the impurity concentration N _D of the impurity diffusion layer 12. Therefore, the potential φ is determined by the impurity concentration N _D of the impurity diffusion layer 12.

In the CCD 10, since the potential is in the range of not less than the potential at which the depletion layer is formed in the impurity diffusion layer 12 and not more than 10 V, the potential dip becomes small and the transfer efficiency becomes high.

FIG. 2 shows an example of the relationship between transfer efficiency and potential. The figure shows the results of examining the transfer efficiency when the potential value is changed with the gate insulating film kept constant. In this figure, the vertical axis represents the transfer efficiency and the voltage representing the horizontal transfer efficiency of the CCD 10 (for example, LL.LINE3).
3), and the horizontal axis shows the potential. LL. LIN
E33 is for determining that the transfer efficiency increases as the voltage approaches 0. As shown in the figure, when the potential was higher than 10 V, the transfer efficiency was significantly lowered, while when the potential was 10 V or less, the practical transfer efficiency was obtained.

On the other hand, if the potential is so low that a depletion layer is not formed in the impurity diffusion layer 12, no charge can be stored in the impurity diffusion layer 12 even if a voltage is applied to the electrode 16. That is, it does not function as a CCD. On the other hand, if the potential exceeds 10 V, the transfer efficiency will be significantly reduced, which is not practical. Therefore, the potential is set within the above range.

Next, the potential dip δφ which causes the transfer deterioration of the CCD will be described with reference to the potential diagram of FIG. In the figure, the solid line indicates the potential distribution in the depth direction below the electrodes 16, and the broken line indicates the potential distribution in the depth direction below the electrodes 16.

As shown in the figure, in the impurity diffusion layer 12, the minimum potential φ 2m in the potential distribution below the insulating film 17 thicker than the gate insulating film 15 is the minimum potential in the potential distribution below the gate insulating film 15. It is deeper than φ1m. The minimum potential φ1m is located at the depth X1m from the interface, and the minimum potential φ2m is located at the depth X2m from the interface. If φ2m-φ1m is the potential dip δφ, then δ
φ is expressed by equation (5).

[0031]

[Number 5] _{δφ = φ2m-φ1m = qN D} (X2m 2 -X1m 2) / (2χ S ε 0) + qN D (d2 X2m-d1 X1m) / (χ S ε 0) ··· (5) ( formula Where q is the electric charge of electrons, N _D is the impurity concentration of the impurity diffusion layer 12, d ₁ is the film thickness of the gate insulating film 15, and d ₂ is the film thickness of the insulating film 17 between the electrodes 16 in the film thickness direction of the electrodes 16. , Χ _S represents the relative permittivity of the gate insulating film 15, and ε ₀ represents the vacuum permittivity.)

Here, the depths X1m and X2m from the interface of the respective minimum potentials hardly depend on the thickness of the gate insulating film 16. Therefore, since it can be approximated as X1m≅X2m, the first term of the equation (5) can be ignored. As a result, the equation (5) has only the second term, and the equation (6) is obtained by modifying the equation (5) with X1m = X2m = Xm.

[0033]

[6] _{δφ = φ2m-φ1m = qN D} (d2 -d1) Xm / (χ S ε 0) ··· (6)

Here, as the film thickness d ₁ of the gate insulating film 15 changes, the film thickness d ₂ of the insulating film 17 also changes by the same amount, and therefore d ₂ −d ₁ = constant. Further, since the electric charge q of the electron, the depth Xm from the interface of the minimum potential, the relative permittivity χ _S of the gate insulating film 15 and the vacuum permittivity ε ₀ are constant, the above equation (6) is represented by the following equation (7). Represented by.

[0035]

Equation 7] _{δφ = cN D ··· (7)} ( _{where, c = q (d 2 -d} 1) Xm / (χ S ε 0) is. For a constant)

Therefore, it can be seen that the potential dip δφ is proportional to the impurity concentration N _D of the impurity diffusion layer 12. Therefore, the potential dip δφ is reduced by reducing the impurity concentration N _D. If the potential dip can be reduced, the residual charge amount is reduced and transfer deterioration is improved.

Therefore, if the potential of the CCD 10 when a voltage for accumulating charges is applied to the impurity diffusion layer 12 directly below the electrode 16 is equal to or higher than the potential at which a depletion layer is formed in the impurity diffusion layer 12, The lower the potential is, the more preferable it is, but if the potential is too low, the dynamic range becomes low. Therefore, considering the dynamic range, it is desirable that the potential is set within the range of 7V to 8V.

As described above, by satisfying the film thickness condition of the gate insulating film of the first embodiment and the potential condition of the second embodiment, as shown in FIG. It is possible to significantly reduce the potential dip δφ below the film 17 to prevent the transfer efficiency from deteriorating and increase the amount of charges handled in the transfer portion. Therefore, the CCD 10 has excellent performance.

In the above description, the CCD of the two-phase driving system has been described. However, even in the three-phase driving system and the four-phase driving system, the transfer deterioration can be improved similarly to the two-phase driving system described above. It is possible.

[0040]

As described above, according to the present invention,
Since the gate insulating film of the charge coupled device is formed to have a film thickness in the range of 20 nm or more and 60 nm or less, it is possible to increase the amount of charges handled in the transfer section. Further, the potential of the charge-coupled device when a voltage for accumulating charges is applied to the diffusion layer immediately below the electrode of the charge-coupled device is within the range from the potential at which the depletion layer is formed in the diffusion layer to 10 V or less. Therefore, the potential dip is reduced and the transfer efficiency can be improved.

[Brief description of drawings]

FIG. 1 is a schematic configuration sectional view of an embodiment of the present invention.

FIG. 2 is a relationship diagram between transfer efficiency and potential.

FIG. 3 is a potential diagram in the depth direction of a CCD transfer unit.

FIG. 4 is an explanatory diagram of an example of improving a potential dip.

FIG. 5 is a schematic cross-sectional view of a conventional CCD transfer unit.

6 is a potential diagram of the CCD transfer unit shown in FIG. 5 in the depth direction.

FIG. 7 is a potential diagram under a CCD electrode array of a conventional example.

[Explanation of symbols]

 10 CCD (charge coupled device) 12 impurity diffusion layer 15 gate insulating film 16 electrode

Claims (4)

[Claims] 1. A charge-coupled device in which a plurality of electrodes are arranged above a diffusion layer via a gate insulating film, wherein the gate insulating film is formed to a film thickness within a range of 20 nm or more and 60 nm or less. Charge coupled device. 2. A charge-coupled device having a plurality of electrodes arranged above a diffusion layer, wherein the potential of the charge-coupled device when a voltage for accumulating charges is applied to the diffusion layer directly below the electrode is A charge-coupled device, characterized in that the depletion layer is formed in the diffusion layer in a range of not less than a potential and not more than 10V. 3. The charge coupled device according to claim 2, wherein the charge coupled device has a MOS structure in which a gate insulating film is provided between the diffusion layer and the electrode. 4. The charge coupled device according to claim 3, wherein the gate insulating film is formed with a film thickness within a range of 20 nm or more and 60 nm or less.