JPH0946382A - Method for regenerating clock in fsk demodulator and clock regenerator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a stable regenerated clock, regardless of the number of the frequency shift of a multivalued FSK signal. SOLUTION: The sampling signals between one-symbol rate are held in a shift register 3 by sampling the FSK signal demodulated by an FM demodulator 1 at the speed which is 8 times as fast as a symbol rate by a first sampling circuit 2 and inputting the FSK signal in the shift register 3 having 8 registers 3a to 3h. In differentiating circuit 4, the changed quantity of the signal corresponding to a differential value and the changed width of the FSK signal at one-symbol rate space are calculated by the subtraction of the prescribed signals with each other of the shift register 3. In an edge detection circuit 5, it is detected that these become prescribed values. As a result, an edge pulse is outputted from the edge detection circuit 5, the synchronization in a PLL oscillation circuit 6 is taken and a reproduced clock is inputted from the PLL oscillation circuit 6 for a second sampling circuit 8.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to FSK (Freqency).
The present invention relates to a clock reproducing method and a device thereof used for demodulating a shift keying (Signal) signal, and in particular, when the FSK signal to be demodulated is multi-valued, the FSK demodulation for stabilizing the reproduced clock regardless of the value. The present invention relates to a reproduction clock generation method and a reproduction clock generation device in an apparatus.

[0002]

2. Description of the Related Art The FSK signal is a typical signal used for data transmission. For example, the most basic signal structure has two kinds of frequencies (for example, a mark and a space of a digital signal). , 1200Hz and 2200H
There is a so-called binary format corresponding to z).

When demodulating such a binary FSK signal, a clock is required for synchronization with the transmitting side, and therefore various methods have been proposed as clock recovery techniques. For example, in the case of the binary FSK signal as described above, a pulse signal is generated at this point by detecting a point approximately midway where the signal frequency changes from 1200 Hz to 2200 Hz, that is, a point where the signal frequency becomes 1700 Hz. In some cases, a signal synchronized with this pulse signal is generated as a reproduced clock signal by the PLL circuit by inputting it to a PLL (Phase Locked Loop) circuit (see FIG. 6).

[0004]

By the way, in the FSK signal receiving system, in addition to the system capable of receiving only the FSK signal having a predetermined number of frequency shifts, a plurality of FSK signals can be received within a predetermined range. In some cases, a device that can receive the multi-valued FSK signal is necessary. However, in such a multi-valued FSK signal other than binary, the FSK signal transmitted from the outside is not known in advance. For example, four-valued F (when frequency change is 1200Hz, 1533Hz, 1867Hz, 2200Hz)
If the SK signal changes as shown in FIG. 7, then 2
Two signal change points, namely 1367Hz, which is the midpoint between 1200Hz and 1533Hz, and 1867, which is the midpoint between 1533Hz and 2200Hz.
We have to detect two points at Hz.

Furthermore, as the number of multi-values, such as 8-values and 16-values, increases, the number of change points that must be detected increases, and the plurality of change points occur at random. With the detection method such as the case of the value, a stable and reliable recovered clock cannot be obtained.

The present invention has been made in view of the above situation, and it is possible to obtain a stable reproduced clock regardless of the number of frequency shifts of a multilevel FSK signal received with a simple structure, that is, the multilevel value. A method of generating a recovered clock in a demodulator and a recovered clock generator are provided. Another object of the present invention is to provide a recovered clock generator having high versatility.

[0007]

A method for generating a reproduced clock in an FSK demodulator according to claim 1 is a method for generating a reproduced clock in an FSK demodulator which reproduces a clock from a demodulated multi-level FSK signal. Immediately after the optimum sampling point at the rising edge or the rising edge due to the symbol change is detected for the held sampling signal of the 1-symbol rate section while sequentially repeating sampling and holding of the multi-level FSK signal corresponding to the 1-symbol rate section. Then, a pulse signal for synchronizing the reproduction clock is output, and the reproduction clock is generated in synchronization with this pulse signal.

Therefore, for example, in FIG. 5, an example of a temporal change of the multi-valued FSK signal sampled and held (an example in the case of rising) is shown in FIG. ), But where
FIG. 11B shows an example in which the optimum sampling point is detected at the rising edge of the multilevel FSK signal in the 1-symbol rate section. That is, the optimum sampling point E6 which is the start point of a new symbol at time t1 in FIG. 5B and the optimum sampling point E5 which is the point immediately before the stable state of the new symbol is detected at time t2 are detected. It is in the state of being.

Immediately after the optimum sampling point is detected, that is, when the optimum sampling points E6 and E5 are slightly deviated from the times t1 and t2, as shown in FIG. A signal is output, and a reproduction clock is generated in synchronization with this pulse signal. However, since the generation timing of this pulse signal is in synchronization with the symbol rate, it is possible to obtain a stable and reliable reproduction clock. Is something that can be done.

The recovered clock generator according to claim 2 is
The demodulated multi-level FSK signal is sampled at a speed of a predetermined multiple with respect to the symbol rate of the multi-level FSK signal, and the sampling holding means holds the sampling signal in one symbol rate section, and the sampling holding means. A signal operation means for calculating a value corresponding to a differential value of the held signal and a variation amount of the signal during one symbol rate, and a sampling operation held by the sampling holding means based on an operation result of the signal operation means. An edge detection unit that detects the presence or absence of an optimum sampling point for the signal and outputs a pulse signal when the optimum sampling point is detected, and a clock generation unit that generates a clock synchronized with the pulse signal of the edge detection unit. It is equipped with.

In such an apparatus, the sampling and holding means samples the multi-valued FSK signal at a speed which is a predetermined multiple of the symbol rate, and holds the sampling signal in one symbol rate section. Then, in the signal calculation means, the differential value of this signal and the amount of change of the signal in the 1-symbol rate interval are calculated from the signal held in the sampling holding means, and in the edge detection means, determination based on this calculation result is performed. The output timing of the pulse signal is determined.

For example, in FIG. 5, an example of a temporal change (an example in the case of rising) of the original multi-valued FSK signal held in the sampling holding means is shown in FIG. It is shown up to (c). Here, FIG. 6B is an example in which the optimum sampling point is detected at the rising edge of the multi-valued FSK signal in the 1-symbol rate section. In the case of such a signal change, the value corresponding to the differential value at time t1 calculated by the signal calculation means and the value corresponding to the differential value at time t2 are
A change corresponding to a signal change is shown.

For example, the optimum sampling points E6 and E5 of the multi-valued FSK signal as shown in FIG.
When detected at 1 and t2, the values corresponding to the differential value at each point are the same. FIG. 5 (c)
When the signal detected at the times t1 and t2 is a portion just past the optimum sampling point of the multi-valued FSK signal as shown in (1), (value corresponding to the differential value at the time t1)>
(Value corresponding to the differential value at time t2).

The edge detecting means detects the optimum sampling point by comparing the values corresponding to the differential values in this way, and immediately after that, that is, in the example of FIG. 5, the state of FIG. , Under certain conditions, that is,
If the difference between the sampling value at time t1 and the sampling value at time t2 is greater than or equal to a predetermined value, the value corresponding to the differential value is considered to be reliable and a pulse signal is generated.

The clock generating means outputs the reproduction clock in synchronization with this pulse signal. The pulse signal output from the edge detecting means as described above is output in synchronization with the symbol rate of the multi-valued FSK signal, and is stable and surely output regardless of what value the multi-valued is. As a result,
In the clock generating means, the reproduced clocks are synchronized accurately and stably, and a stable reproduced clock can be obtained.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the invention of a reproduced clock generating method and a reproduced clock generating apparatus in an FSK demodulating device according to the inventions of claims 1 and 2 will be described below with reference to FIGS. explain. The members, arrangements, and the like described below do not limit the present invention and can be variously modified within the scope of the gist of the present invention. First, the recovered clock generator according to the embodiment of the present invention uses an FM demodulator (“FM D
1), a first sampling circuit (abbreviated as "SAMP1" in FIG. 1) 2, a shift register 3, a differentiating circuit 4, an edge detection circuit 5, and a PLL oscillation circuit (in FIG. 1). "PLL OSC") 6, a second sampling circuit (abbreviated as "SAMP2" in FIG. 1) 8,
Is the main constituent element (see FIG. 1).

The FM demodulator 1 is designed to output the input multi-valued FSK signal as an analog or digital voltage signal, and is constructed by using a circuit which is already known or well known. Since this circuit configuration itself is not directly related to the gist of the present invention, detailed description thereof will be omitted here. In consideration of the ease of signal processing in the subsequent stage, the FS configured to output a digitized voltage signal is actually used.
A K demodulator is preferred.

The first sampling circuit 2 samples and outputs the output signal of the FM demodulator 1 at a timing of a predetermined sampling clock. In the embodiment of the present invention, the sampling rate is the symbol rate of the FSK signal. It is set to 8 times. That is, FSK
If the symbol rate of the signal is 1 / (fs (Hz)), the sampling frequency is set to 8 × fs (Hz).

It should be noted that, when the input signal is a binary or octal FSK signal, this sampling frequency does not cause jitter of the sampling signal in any of the FSK signals, and is experimentally set as a proper frequency. Was sought after.

In reality, even if the sampling frequency is slightly lower than this, it does not mean that the sampling frequency does not function at all, but as the value becomes multivalued, the jitter of the sampled signal increases and the stability is impaired. So 8 × fs (Hz)
The following is not preferable. Further, the sampling frequency is not necessarily 8 × fs (Hz), and setting the sampling frequency higher than this will further increase the stability of the PLL oscillation circuit 6 described later.
z) or more.

The shift register 3 receives the sampling signal output from the above-mentioned first sampling circuit 2 as a first sampling signal.
Shift register is performed in synchronism with the sampling of the sampling circuit 2 of FIG. 1 and has first to eighth registers 3a to 3h, which makes it possible to hold eight sampling signals. It is what The number of sampling signals held by the shift register 3 is determined by the sampling frequency of the first sampling circuit 2. That is, when the sampling frequency is N × fs (Hz), the shift register 3 can hold the sampling signal in exactly one symbol rate section by providing N registers.

The differentiating circuit 4 is for calculating a value corresponding to a differential value of a predetermined portion of the signal held in the shift register 3 (details will be described later), and in the embodiment of the present invention, Three first to third adder / subtractors 7a-
7c.

The signal values held in the first register 3a and the third register 3c of the shift register 3 are input to the first adder / subtractor 7a, and the third register 3c is input.
The result (S1) obtained by subtracting the signal value of the first register 3a from the signal value of 1 is output (see FIG. 1).
reference). The signal values of the sixth register 3f and the eighth register 3h are input to the second adder / subtractor 7b, and the signal value of the sixth register 3f is subtracted from the signal value of the eighth register 3h. The result (denoted as S2) is output (see FIG. 1).

Furthermore, the signal values of the first register 3a and the eighth register 3h are input to the third adder / subtractor 7c, and the signal values of the eighth register 3h are used to convert the signal values of the first register 3h.
The result (S3) of subtracting the signal value of a is output (see FIG. 1).

By the way, the multi-valued FS input to this device
It is premised that the K signal has a constant symbol rate (1 / fs (Hz)) regardless of the number of multi-valued values. Therefore, as the FSK signal captured in the one symbol rate section, for example, the part of switching from one frequency to the next frequency as shown in FIG. 3 or the one from the certain frequency to the next frequency as shown in FIG. It is possible to capture an object that once switches to the frequency and then returns to the original frequency.

In the embodiment of the present invention, as described above, the sampling rate of the first sampling circuit 2 is set to 8 times the symbol rate of the FSK signal. For example, in FIGS. 3 and 4, a signal corresponding to the FSK signal in the portion defined as the one-symbol rate section is divided into eight is held.

As a result, the output signals of the first to third adder / subtractors 7a to 7c constituting the differentiating circuit 4 have the meaning described below. For example, shift register 3
Assuming that the signal stored in the FSK signal corresponds to the FSK signal shown in FIG. 3, the magnitude of the calculated value S1 of the first adder-subtractor 7a is the same as that of the FSK signal shown in FIG. It is proportional to the slope of the tangent line a at the optimum sampling point E1.

That is, the signal held in the shift register 3 is the latest signal in time with respect to the signal held in the first register 3a, and goes to the second to eighth registers 3b to 3h. Therefore, the old one is retained. Then, subtracting the signal value of the first register 3a from the signal value of the third register 3c is equivalent to the point E
This is equivalent to obtaining the change amount of the signal in 1, and the differential value is obtained by dividing this change amount by time. Therefore, the value of the calculated value S1 is naturally proportional to the differential value.

In the embodiment of the present invention, the point E is obtained by using the signal values of the first and third registers 3a and 3c.
Although the calculated value corresponding to the differential value of 1 is obtained, the present invention is not limited to this. That is, the first
If a signal at a time closer to the signal held in the register 3a is used, theoretically, a value corresponding to a differential value in a stricter sense can be obtained. In consideration of the fact that the use of two signals that are extremely close to each other in time causes the output of an incorrect value when noise is superimposed, in the embodiment of the present invention, the first and the first The values of the registers 3a and 3c of No. 3 are used.

On the other hand, the output signal S2 of the second adder / subtractor 7b
If the signal corresponding to the FSK signal shown in FIG. 3 is held in the shift register 3, the magnitude of is proportional to the slope of the tangent line B at the point E2 which is the optimum sampling point. That is, the signal held in the eighth register 3h corresponds to the FSK signal in the vicinity of the point E2 which is the optimum sampling point.
The subtraction of the signal value held in the register 3f, that is, the operation value sampled after the point E2 in time is performed in the vicinity of the point E2 as in the case of the operation value S1 of the first adder / subtractor 7a. A value proportional to the differential value of will be obtained. In other words, the magnitude of the calculated value S2 is proportional to the differential value which is the slope of the tangent line B.

Further, the calculated value S3 of the third adder / subtractor 7c
Is for determining whether the FSK signal has truly changed. That is, when the signal corresponding to the FSK signal in the 1-symbol rate section as shown in FIG. 4 is held in the shift register 3, the calculated value S1 of the first adder / subtractor 7a of the differentiating circuit 4 and the second value It is the same as the calculated value S2 of the adder / subtractor 7b (the absolute value of the slope of the tangent C at the point E3 and the absolute value of the slope of the tangent D at the point E4 match). For this reason, only comparing the two calculated values S1 and S2 actually causes FSK
Unable to determine if the signal has changed. Further, although the FSK signal itself does not change, there is a possibility that the calculated value S1 of the first adder / subtractor 7a and the calculated value S2 of the second adder / subtractor 7b may be different due to noise superposition.

Therefore, the calculated value S3 by the third adder / subtractor 7c is used as an index for making a determination in the above case. For example, when the signal held in the shift register 3 corresponds to the FSK signal as shown in FIG. 3, the calculated value S3 is the change amount between two symbols (corresponding to A in FIG. 3). It becomes a corresponding value. When the signal held in the shift register 3 corresponds to the FSK signal shown in FIG. 4, the calculated value S3 becomes zero. Therefore, by observing the calculated value S3 together with the calculated values S1 and S2, the calculated value S1,
It is possible to judge the authenticity of the value of S2.

Next, the edge detection circuit 5 is for determining the output timing of the edge pulse output to the PLL oscillation circuit 6 based on the calculated value of the differentiating circuit 4 described above. The edge detection circuit 5 may be configured by so-called hardware so as to perform edge detection processing which will be described later based on FIG. 2, but in consideration of simplicity of the configuration, processing time, etc., a so-called CPU is used. Those configured by software that executes the algorithm shown in 2 are suitable.

The PLL oscillation circuit 6 is a so-called Phase Lock.
This is an oscillating circuit composed of an ed loop, and the reproduced pulse to be outputted is synchronized by the edge pulse outputted from the edge detecting circuit 5. The circuit configuration of the PLL oscillation circuit 6 is publicly known and well known, and detailed description thereof will be omitted.

The second sampling circuit 8 is for sampling the multi-level FSK signal output from the FM demodulator 1 and outputting it as an output symbol string. The sampling clock of the second sampling circuit 8 is P
The reproduced clock generated by the LL oscillator 6 is used.

Next, referring to the flow chart shown in FIG. 2 and the schematic diagram shown in FIG. 5, the edge detection circuit 5
The operation of the recovered clock device according to the embodiment of the present invention will be described with a focus on the above operation. The description of the operation of this device will be replaced with the description of the method of generating the reproduced clock in the FSK demodulation device.

First, the output timing of the edge pulse by the edge detection circuit 5 will be briefly described with reference to FIG. FIGS. 5A to 5C schematically show the temporal change of the signal held in the shift register 3 by the FSK signal, which are temporally new in order from FIG. There is.

The processing for outputting the edge pulse in the edge detection circuit 5 is basically performed when the signal held in the shift register 3 is represented by the original FSK signal, for example.
When changing as shown in FIGS. 5A to 5C, the differential value at the time t1 and the differential value at the time t2 are compared to obtain (differential value at the time t1)> (time t2
(Differential value in)), the edge pulse is output.

To determine the edge pulse output, for example, in the case of the FSK signal as shown in FIG. 5, the slope K1 of the tangent line at time t1 is compared with the slope K2 of the tangent line at time t2. Done.

That is, in the case of a signal as shown in FIG. 5A, the relationship between the inclinations of the two tangent lines is K2>
It is K1. In the case of the signal as shown in FIG. 5B, K2 = K1, and at time t1, the optimum sampling point E6, which is the start point of a new symbol, becomes new at time t2. The optimum sampling point E5, which is the point immediately before the stable state of the symbol, is detected. Further, in the case of the signal shown in FIG. 5C, K2 <K1.

Therefore, by comparing K1 and K2 in this way, the timing of edge pulse output can be judged. In the embodiment of the present invention, K2 <
The timing at which K1 is detected is the output timing of the edge pulse. This is basically the same also in the case of the fall of the FSK signal, but in the case of the fall, in the comparison of the absolute values of the values corresponding to K1 and K2, the same as above. It can be said that.

Next, the specific operation of the edge detection circuit 5 will be described with reference to the flow chart shown in FIG. First, it is determined whether or not the absolute value of the calculated value S3 of the third adder / subtractor 7c of the differentiating circuit 4 is a predetermined value K or more (see step 100 in FIG. 2), and the absolute value of the calculated value S3 is the predetermined value. If it is determined to be smaller than K (in the case of NO),
The processing is re-executed assuming that it is not the timing for generating the edge pulse, but when it is determined that the absolute value of the calculated value S3 is equal to or greater than the predetermined value K (in the case of YES), the process proceeds to the next step 102 and the differentiation circuit 4 First adder / subtractor 7a
Sign of the calculated value S1 input from the second adder / subtractor 7
It is determined whether or not the sign of the calculated value S2 input from b is the same.

Note that the value of the predetermined value K in step 100 is, for example, the minimum step width in the maximum multi-valued FSK signal among the multi-valued FSK signals which this reproduction clock generator is supposed to handle. About 70% of (that is, the minimum value of the change width between the two symbols) is preferable.

When it is determined in step 102 that the sign of the operation value S1 and the sign of the operation value S2 are not the same (in the case of NO), it is determined that it is not the timing to generate the edge pulse, and the process is restarted from step 100. On the other hand, when it is determined that the sign of the calculated value S1 and the sign of the calculated value S2 are the same (in the case of YES), the process proceeds to the next step 104.

In step 104, it is judged whether or not the absolute value of the calculated value S2 exceeds the absolute value of the calculated value S1, and it is judged that the absolute value of the calculated value S2 does not exceed the absolute value of the calculated value S1. If it is (NO), it is determined that it is not the timing of the edge pulse generation yet, and the process returns to the previous step 100 and the above-mentioned processing is repeated again.

On the other hand, when it is determined that the absolute value of the calculated value S2 exceeds the absolute value of the calculated value S1 (in the case of YES),
An edge pulse is output from the edge detection circuit 5 to the PLL oscillation circuit 6 (step 106 in FIG. 2).
reference). By this edge pulse, the PLL oscillation circuit 6
Then, the output timing of the reproduction clock is synchronized.

After the edge pulse is output as described above, dead time processing is performed (FIG. 2).
Step 108). That is, after the output of the edge pulse, a predetermined time has elapsed, and then the above-described step 10 is performed.
The operation timings of the first sampling circuit 2 and the shift register 3 and the edge detection circuit 5 are adjusted by repeating the processing after 0 again. In the embodiment of the present invention, the above-mentioned predetermined time is set to 3 / (4 × fs) sec in consideration of the result of the experiment.

As described above, the edge detection circuit 5 outputs an edge pulse signal at the rising and falling edges of the symbol of the multi-level FSK signal. The edge pulse synchronizes the reproduced clock output in the PLL oscillation circuit 6, and the reproduced clock is supplied to the second sampling circuit 8.

In the second sampling circuit 8, sampling is performed in synchronization with the input reproduction clock, and the sampling signal is finally demodulated FSK.
The signal is output to the outside as an output symbol string. The phase relationship between the output symbol string output from the second sampling circuit 8 and the reproduced clock is such that the signal output from the second sampling circuit 8 corresponds to, for example, the FSK signal shown in FIG. If so, the reproduced clock is output from the PLL oscillation circuit 6 at an approximately midpoint between the time when the point E2 appears and the time when the point E1 appears.

In the above-described embodiment of the invention, the sampling holding means is the first sampling circuit 2 and the shift register 3, the signal calculating means is the differentiating circuit 4, and the clock generating means is the PLL oscillating circuit 6.
Each has been realized. Further, the edge detecting means is realized by the edge detecting circuit 5 executing the respective processes shown in FIG.

[0051]

As described above, according to the present invention,
At the rising edge and the falling edge of the FSK signal, the reproduction clock is generated in synchronization immediately after the optimum sampling point is detected, which is different from the conventional case, and the multi-valued value (frequency shift) of the multi-valued FSK signal is different. The value of (number) has nothing to do with the generation of the reproduction clock, so that the reproduction clock can be stably and reliably synchronized, and an accurate reproduction clock can be obtained. is there. In addition, a plurality of multivalued FSs
Since it can handle K signals, it is possible to provide a highly versatile recovered clock device.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a configuration example of a recovered clock generation device according to a second aspect of the invention.

FIG. 2 is a flowchart showing a method of generating a regenerated clock in the FSK demodulator according to the invention of claim 1 and a processing procedure in an edge detection operation in the regenerated clock generator of the invention in claim 2;

FIG. 3 is a waveform diagram showing an example of an FSK signal sampled by a sampling circuit which constitutes the recovered clock generator in the embodiment of the invention shown in FIG.

FIG. 4 is a waveform diagram showing another example of the FSK signal sampled by the sampling circuit which constitutes the recovered clock generating device in the embodiment of the invention shown in FIG.

FIG. 5 is a schematic diagram schematically showing the temporal change of the FSK signal corresponding to the signal held in the shift register that constitutes the recovered clock generator in the embodiment of the invention shown in FIG.

FIG. 6 is a schematic diagram for explaining a generation timing of a reproduction clock when a reproduction clock is obtained from a binary FSK signal.

FIG. 7 is a schematic diagram for explaining a reproduction clock generation timing when a reproduction clock is obtained from a four-level FSK signal.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... FM demodulator 2 ... Sampling circuit 3 ... Shift register 4 ... Differentiation circuit 5 ... Edge detection circuit 6 ... PLL oscillation circuit 7a ... 1st addition / subtraction device 7b ... 2nd addition / subtraction device 7c ... 3rd addition / subtraction device

Claims (2)

[Claims] 1. A method for generating a recovered clock in an FSK demodulating apparatus for recovering a clock from a demodulated multi-level FSK signal, which comprises sequentially repeating sampling and holding of the multi-level FSK signal corresponding to one symbol rate section. , For the held sampling signal in the 1-symbol rate section,
Immediately after the rising edge or the optimum sampling point at the rising edge due to the symbol change is detected, a pulse signal for synchronizing the reproduced clock is output, and the reproduced clock is generated in synchronization with this pulse signal.
A method for generating a recovered clock in a K demodulator. 2. Sampling holding means for sampling the demodulated multi-level FSK signal at a speed of a predetermined multiple with respect to the symbol rate of the multi-level FSK signal, and for holding a sampling signal in one symbol rate section, A signal calculation means for calculating a value corresponding to a differential value of the signal held in the sampling holding means and a variation amount of the signal between 1 symbol rates, and the sampling holding means based on a calculation result of the signal calculating means. An edge detection unit that detects the presence or absence of an optimum sampling point of the sampling signal held in the output, and outputs a pulse signal when the optimum sampling point is detected, and a clock that generates a clock synchronized with the pulse signal of the edge detection unit. A reproduction clock generation device comprising: a generation unit.