JPH0945889A - Chemical compound semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a chemical compound semiconductor device having an ohmic electrode which is low in resistance, excellent in evenness, and hardly deteriorates in contact resistance even at high temperatures, whereby a compound semiconductor integrated circuit is enhanced in reliability and manufacturing cost. SOLUTION: In a process where the ohmic electrode of a chemical compound semiconductor device is formed, an Ni thin film 10 and a Ti thin film 11 are successively deposited on a GaAs substrate 1, and the substrate 1 and the films 10 and 11 are subjected to a thermal treatment for the formation of intermetallic compound, whereby an ohmic electrode which is high in thermal stability and uniform in characteristics can be formed.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a compound semiconductor device having an ohmic electrode, and more particularly to a GaAs FET.

[0002]

2. Description of the Related Art Conventionally, an ohmic contact electrode (ohmic electrode) formed in a compound semiconductor device is generally A.
It was formed by alloying the compound semiconductor substrate with the alloy of u. For example, an example using n-type GaAs is “An Improved AuGe Ohmic Contact To n-GaAs” by Marshall I. Nathan and Mordehai Heiblum.
(Solid State Electronics, Vol.25, pp1063 ~ 1065 (19
82)), a GaAs FET (field-effect transistor) is manufactured by first depositing Au on the n-type GaAs3 surface in the ohmic electrode formation planned region as shown in FIG.
Ge13 / Ni10 / Au14 is deposited and heat-treated at a temperature higher than the eutectic temperature (356 ° C.) of the AuGe alloy. By this heat treatment, GaAs and AuGe are alloyed, and a high concentration of Ge is contained in GaAs recrystallized in the cooling process. Thus, a layer containing a large amount of Ge donor impurities is formed at the electrode-semiconductor interface, and ohmic properties are obtained. Further, for p-type GaAs, a metal such as Mg, Zn, or Be that serves as an acceptor in GaAs and Au are used.
Similar to the n-type, alloying is performed to form an ohmic electrode.

On the other hand, as a gate electrode material of GaAsFET, a heat resistant material such as W or Mo and their nitrides or silicides is often used, and a stable Schottky electrode which is not deteriorated even at a high temperature is obtained.

Ohmic materials such as Ni / In / Ge have also been developed (Murakami et al. J. Appl. Phys.
75 (5), 1, 1994, NiGe-based Ohmic contacts to n-ty
pe GaAS I. Efects of In addition). In this method, an intermetallic compound is generated by heat treatment, and the reaction between the electrode material and the substrate is accurately controlled.

[0005]

However, the Au-based ohmic electrode used in the above compound semiconductor device has the following problems.

First, in an Au-based ohmic electrode, the electrode metal reacts nonuniformly to cause island-like aggregation, and
In some cases, the ohmic contact portion with and becomes uneven in the electrode region. Therefore, there are problems that the contact resistance is not sufficiently reduced and the electrode surface is not smooth, which is insufficient for application to an LSI or the like that requires miniaturization.

Further, even if a thermally stable metal is used for the gate electrode, there is a problem in that the ohmic contact electrode is first deteriorated when kept at a high temperature. For example, n-type GaA
After forming the AuGe / Ni / Au ohmic electrode for s, if there is a heat treatment at 400 ° C. or higher, the alloying reaction proceeds excessively, and the flatness and the contact specific resistance deteriorate. Thus, the reliability of the device was limited by the reliability of the ohmic electrode.

Further, when ohmic contacts are made to the n layer and the p layer, respectively, different electrode structures are required, and there is a problem that the number of steps is increased.

Further, regarding the interconnection with the Al-based wiring used in the LSI process, there is a problem that the connection is difficult because Au reacts with Al to increase the resistance.

Further, regarding the ohmic material such as In / Ni / Ge, since it is an intermetallic compound of three or more kinds of materials, it is necessary to precisely control the composition of each metal and deposit it. There is a high possibility that the intermetallic compound cannot be reproduced even if it shifts to, and there is a problem that the reproducibility is difficult.

In view of these problems, the present application provides a compound semiconductor device having an ohmic electrode having low contact resistance, good flatness, and contact resistance that does not deteriorate even at high temperatures, and a method for manufacturing the same.

[0012]

In order to solve the above problems, in the compound semiconductor device of the present application, in a compound semiconductor device having an ohmic electrode on a compound semiconductor substrate, the ohmic electrode is formed of a metal between at least nickel and titanium. It is characterized by being composed of a compound. Further, it is characterized in that it has a metal wiring containing Al on the ohmic electrode, and has a wiring made of the same intermetallic compound made of at least nickel and titanium as the ohmic electrode forming material.

Further, in a compound semiconductor device having an ohmic electrode in each region on a compound semiconductor substrate having an n-layer region and a p-layer region, the ohmic electrodes in each region have the same structure and are made of a metal containing at least nickel and titanium. It is characterized by being composed of intermetallic compounds.

Further, in the method of manufacturing a compound semiconductor device of the present application, a step of forming a nickel thin film on a compound semiconductor substrate, a step of forming a titanium thin film on the nickel thin film, and a heat treatment of the nickel thin film and the titanium thin film. Reaction to form an intermetallic compound of nickel and titanium to form an ohmic electrode.

Further, a step of forming a nickel thin film on the n layer and the p layer area of a compound semiconductor having an n layer area and a p layer area, a step of forming a titanium thin film on the nickel thin film, and the nickel thin film. And a step of reacting the titanium thin film by heat treatment to form an intermetallic compound of nickel and titanium to simultaneously form ohmic electrodes of the n-layer and the p-layer.

Further, a step of implanting ions for forming a conductive layer on a compound semiconductor substrate, a step of forming a nickel thin film on the substrate, a step of forming a titanium thin film on the nickel thin film, And a step of simultaneously performing a heat treatment for activating the implanted ions and a heat treatment for forming the intermetallic compound of nickel and titanium.

Further, a step of forming a nickel thin film on the compound semiconductor substrate, a step of forming a titanium thin film on the nickel thin film, a step of etching the nickel thin film and the titanium thin film into a wiring shape, and the nickel A step of reacting the thin film and the titanium thin film by heat treatment to form an intermetallic compound, and the ohmic electrode and the wiring are simultaneously formed in the same process.

[0018]

DETAILED DESCRIPTION OF THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. However, the numerical values, materials, etc. are not limited to these.

FIG. 1 is a diagram illustrating a process of forming a MESFET according to the present application. First, as shown in FIG.
In order to form the n-GaAs region 2 serving as the operating layer, S
i ⁺ is an accelerating voltage of 30 KeV and a dose of 9 × 10 ¹² cm ^-2
Inject with.

Next, as shown in FIG. 1B, the drain,
In order to form the n ⁺ -GaAs region 3 for lowering the source resistance, a photoresist pattern 20 is formed, and Si ⁺ is selectively applied at an acceleration voltage of 50 KeV and a dose of 2 × 10 ^13.
Two-stage ion implantation of cm ⁻² , 80 KeV, 3 × 10 ¹³ cm ⁻² is performed.

After that, as shown in FIG. 1C, the photoresist 20 is removed and annealed at 950 ° C. for 4 seconds (RT
A: fast lamp heating) is performed to activate the implanted ions. Subsequently, as shown in FIG. 1D, a photoresist pattern 20 is formed on the n ⁺ -GaAs region, and the Ni thin film 10 is vapor-deposited by 200 Å by a resistance heating method.
The Ti thin film 11 is vapor-deposited by 1000 Å by the EB vapor deposition method, and the photoresist film is removed to form a desired electrode shape.

Thereafter, as shown in FIG. 1 (e), 700 Å of silicon nitride 21 is deposited on the surface by a plasma CVD method or the like, and then heat treatment is performed at 600 ° C. for 1 minute in a nitrogen atmosphere. The ohmic electrode 12 containing the intermetallic compound is formed.

Finally, as shown in FIG. 1 (f), Al / T
The gate electrode 15 is formed of i / Pt / Au. This gate is formed by forming a photoresist film on a portion other than forming the gate, etching the silicon nitride film, vapor depositing metal at the etched location, and finally removing the photoresist film.

Thus, Ni and T are formed on the compound semiconductor substrate.
As a result of reacting i at a high temperature, a thermally stable intermetallic compound TiNi ₃ is formed, and an excessive reaction between Ti and the substrate can be suppressed. Furthermore, Ti, whose reaction with the substrate is appropriately controlled, forms an ohmic contact because it makes a level on the surface of the GaAs substrate, and the Ni / Ti metal layer structure of the present invention is thermally stable with respect to the nGaAs layer. As a result, it becomes a uniform ohmic electrode.

FIG. 3 shows that in the Ni / Ti / nGaAs junction, the current Id with respect to the voltage Vds gradually becomes a straight line as the heat treatment temperature rises, and changes from the Schottky junction to the ohmic junction. Ti and Ga
When As reacts, local morphology deterioration occurs on the surface of the substrate and the electrode, and the resistance is increased like the conventional AuGe / Ni / Au electrode. In the present application, the intermetallic compound TiNi ₃ due to the reaction between Ti and Ni suppresses the excessive reaction between Ti and GaAs and prevents the resistance from increasing, so that ohmic contact with low resistance is achieved up to a high temperature.

FIG. 4 shows the contact resistivity of the conventional AuGe / Ni / Au electrode with respect to the nGaAs layer, and the Ni / N of the present application.
It is a figure which shows the heat processing temperature dependence of the contact specific resistance with respect to the nGaAs layer and pGaAs layer of Ti metal layer structure. A
While the contact specific resistance of the uGe / Ni / Au electrode increases as the heating temperature increases, the contact specific resistance of Ni / Ti is stable even when the heating temperature increases. This means that Ni / Ti of the present application is thermally stable.

FIG. 5 shows AuGe / Ni / Au (400 ° C.
FIG. 3 is a diagram showing the contact area dependence of the contact resistivity of Ni) and n / Ti (heat treated at 600 ° C.) with respect to nGaAs. In AuGe / Ni / Au, the contact specific resistance increases significantly as the contact area decreases, but in Ni / Ti, the contact specific resistance hardly changes even if the contact area decreases. This means that Ni / Ti forms a uniform ohmic electrode.

The above results indicate that Ni and Ti are heated by the heat treatment.
Due to the formation of a thermally stable and uniform intermetallic compound. In addition, as shown in FIG.
Similarly to the contact resistivity for nGaAs, the contact resistivity for n does not significantly increase even when heat treatment is performed at high temperature. That is, the Ti / Ni metal layer structure of the present application is a uniform and thermally stable ohmic electrode even for the pGaAs layer.

FIG. 6 shows an LDD-MESFET according to the present application.
FIG. 6 is a diagram illustrating a forming process of FIG. First, as shown in FIG. 6A, in order to form the n-GaAs region 2 which becomes the operating layer, Si ^{+ is used} for the acceleration voltage of 30 KeV and the dose amount of 9 × 10.
Ion implantation is performed at ¹² cm ^-2 . Next, as shown in FIG. 6B, a heat-resistant metal such as WN is deposited at 3000 Å, and the gate electrode 16 is processed by the RIE method.

Subsequently, as shown in FIG. 6C, 5000 Å of silicon nitride 21 is deposited by the plasma CVD method, and then, as shown in FIG. 6D, the silicon nitride film is formed with an etching gas such as CHF ₃ . Perform anisotropic etching.

Next, as shown in FIG. 6E, Si ^{+ is used} as an etching mask to form the n ⁺ layer 3.
Is subjected to two-stage ion implantation at an acceleration voltage of 50 keV, a dose amount of 2 × 10 ¹³ cm ⁻² , an acceleration voltage of 80 keV and a dose amount of 3 × 10 ¹³ cm ⁻² .

Next, as shown in FIG. 6F, after removing the side wall with buffered hydrofluoric acid or the like, the gate electrode is used as a mask to form an n'layer 4 for reducing the source resistance. Si ⁺ was implanted at 50 keV and 6 × 10 ¹² cm ^-2 , and then, as shown in FIG. 6 (g), a Ni thin film 10 was vapor-deposited by 200 Å by a resistance heating method, and then a Ti thin film 11
Is vapor-deposited by 1000Å by EB vapor deposition method.

Next, as shown in FIG. 6 (h), after forming an ohmic electrode pattern with the photoresist 20, as shown in FIG. 6 (i), RIE etching is performed with CF ₄ gas or the like to form a desired electrode. The shape 12 is formed.

Finally, as shown in FIG. 6 (j), after depositing 200 Å of silicon nitride film 21 by plasma CVD method,
LDD-M by annealing at 50 ° C for 8 seconds
Form ESFET. In this embodiment, the activation of implanted ions and the formation of the ohmic electrode can be simultaneously performed by one heat treatment, so that the manufacturing process can be simplified.

FIG. 7 is a diagram for explaining a JFET forming process according to the present application. Here, an example in which the gate electrode and the ohmic electrode can be simultaneously formed will be described by the present application.

First, as shown in FIG. 7A, Si ⁺ is implanted at an accelerating voltage of 120 KeV and a dose of 4 × 10 ¹² cm ^-2 in order to form an n-GaAs region 2 to be an operating layer. Next, as shown in FIG. 7B, p which becomes a gate region is formed.
^In order to form the ⁺ −GaAs region 5, Zn ⁺ is implanted at an acceleration voltage of 30 keV and a dose of 1 × 10 ¹⁴ cm ⁻² .

Next, as shown in FIG. 7C, the drain,
In order to form the n ⁺ -GaAs region 3 for lowering the source resistance, Si ⁺ is selectively 2 × 10 at 180 KeV.
Perform ¹³ cm ^-2 ion implantation.

Thereafter, as shown in FIG.
Annealing is performed at 4 ° C. for 4 seconds to activate the implanted ions.
Next, as shown in FIG. 7E, p ⁺ -GaAs region, n ⁺
A window is opened with a photoresist pattern 20 on the -GaAs region, and the Ni thin film 10 is first heated to 200 Å by resistance heating.
Evaporate. Further, a Ti thin film 11 is formed by EB vapor deposition 10
00Å vapor deposition. Then remove the photoresist film,
A desired electrode shape is formed.

Subsequently, as shown in FIG. 7 (f), silicon nitride 21 is deposited to 700 Å by a plasma CVD method or the like.
Then, by performing heat treatment at 600 ° C. for 1 minute in a nitrogen atmosphere, a JFET having the ohmic electrode 12 can be formed.

FIG. 8 is a diagram illustrating a process of forming a complementary IC according to the present application. Ni / Ti is n of the GaAs substrate
It is possible to form an ohmic electrode for each region of the layer and the p layer.

[0041] First, as shown in FIG. 8 (a), the drain of the n-channel, in order to form the n ⁺ -GaAs region 3 to be a gate region of the n ⁺ -GaAs region 3 and the p-channel for lowering the source resistance , Si ⁺ at 180 KeV 1 × 10
Perform ¹³ cm ^-2 ion implantation. Subsequently, as shown in FIG. 8B, Si ⁺ is implanted at an acceleration voltage of 120 KeV and a dose of 1 × 10 ¹³ cm ^-2 in order to form an n-GaAs region 2 serving as an n-channel operating layer.

Next, as shown in FIG. 8C, in order to form a p-GaAs region 6 which will be a p-channel operating layer,
Mg ⁺ , acceleration voltage 80 KeV, dose 5 × 10 ¹³ cm
Inject at ^-2 . Then, as shown in FIG. 8D, p ⁺ -GaA for lowering the drain and source resistances of the p-channel
s region 5 and p ⁺ -GaAs to be an n-channel gate region
In order to form the region 5, Mg ^{+ is used} for accelerating voltage 30 ke
Implant with V and a dose of 5 × 10 ¹³ cm ⁻² .

Then, annealing is performed at 950 ° C. for 4 seconds to activate the implanted ions. Then, as shown in FIG. 8 (e), a window is opened with a photoresist pattern 20 on all p ⁺ -GaAs regions and n ⁺ -GaAs regions, and N
The i thin film 10 is vapor-deposited by 200 Å by the resistance heating method, and the Ti thin film 11 is further vapor-deposited by 1000 Å by the EB evaporation method.
After that, the photoresist film is removed to form a desired electrode shape.

Next, as shown in FIG. 8 (f), plasma C
By depositing 700 Å of silicon nitride 21 by the VD method or the like and subsequently performing heat treatment at 600 ° C. for 1 minute in a nitrogen atmosphere, the ohmic electrodes 12 for both n ⁺ GaAs and p ⁺ GaAs can be formed at the same time.

Next, an example of joining with Al wiring will be described with reference to FIG.

First, as shown in FIG. 9A, LDD-M
After forming a transistor in the same process as ESFET,
A silicon nitride film 21 is deposited to 2000 Å by plasma CVD method. Next, as shown in FIG. 9B, a window is opened with the photoresist pattern 20 and the silicon nitride film is etched.

Then, as shown in FIG. 9 (c), an Al thin film 17 of 5000 Å is deposited by the EB vapor deposition method, a photoresist pattern is formed on the wiring shape, and Al is etched by Cl ₂ gas or the like. Remove the photoresist. FIG. 7 shows an example in which two FETs are connected by Al wiring.

The Ni / Ti ohmic electrode of the present invention, even when connected to an Al-based wiring, does not cause a reaction that causes a high resistance at the interface like Au conventionally used for an ohmic electrode. LSI that uses Al wiring because it does not exist
It is possible to use the wiring technology of the process as it is.

FIG. 10 shows an example in which the Ni / Ti metal layer structure of the present application is applied to wiring. The formation of the transistor is LD
The same process as in D-MESFET is performed. Figure 1
As shown in 0, after depositing the Ni thin film 10 and the Ti thin film 11, a photoresist pattern is formed in a wiring shape,
This is the point of etching with CF ₄ or the like. The subsequent steps are performed in the same manner as the LDD-MESFET formation step.

FIG. 10 shows an example in which two FETs are connected by wiring. In this embodiment, the metal layer structure of the present invention is used as a wiring, but since the portion in contact with the n ⁺ -GaAs region becomes an ohmic contact, it functions as an ohmic electrode. On the other hand, since the GaAs substrate is semi-insulating and functions as a pure wiring in the portion in contact with the region other than n ⁺ -GaAs, it is possible to form the ohmic electrode and the wiring with the same material. The same material has excellent thermal stability and can be manufactured in the same step, so that the manufacturing process can be simplified.

[0051]

According to the compound semiconductor device of the present invention, a compound semiconductor device having an ohmic electrode having excellent thermal stability and high reliability can be obtained. In addition, Ni / Ti
In the intermetallic compound according to (1), the contact specific resistance does not increase even with a minute contact area, so that the area of the element can be reduced and the manufacturing cost per element can be reduced.

Further, according to the present invention, by using the intermetallic compound of Ni / Ti as the ohmic electrode and the wiring, the manufacturing process of the compound semiconductor device can be simplified and can be miniaturized. Can be reduced.

Further, Ni / Ti is used as an ohmic electrode.
By using the intermetallic compound of, it becomes possible to simultaneously form the n-layer and p-layer ohmic electrodes,
The manufacturing process of the compound semiconductor device can be simplified and the manufacturing cost can be reduced.

Further, since the activation of implanted ions and the formation of the ohmic electrode can be performed by one heat treatment, the manufacturing process can be simplified and the manufacturing cost can be reduced.

Further, by using the metal layer structure of the present invention as an ohmic electrode, it becomes possible to form an Al wiring on the ohmic electrode. Therefore, the wiring technology of SiLSI, which has a proven track record in reliability and miniaturization, can be used as it is. Can be used.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a manufacturing process of a MESFET according to the present application.

FIG. 2 is a diagram showing a structure of an ohmic electrode according to the present application.

FIG. 3 is a diagram showing current-voltage characteristics (heat treatment temperature dependency) of Ni / Ti electrodes.

FIG. 4 is a diagram showing the heat treatment temperature dependence of the contact specific resistance of the ohmic electrode.

FIG. 5 is a diagram showing a contact area dependency of a contact specific resistance of an ohmic electrode.

FIG. 6 is a diagram illustrating a manufacturing process of the LDD-MESFET according to the present application.

FIG. 7 is a diagram illustrating a manufacturing process of the JFET according to the present application.

FIG. 8 is a diagram illustrating a manufacturing process of a complementary IC according to the present application.

FIG. 9 is a diagram illustrating an example of joining with an Al wiring in the manufacturing process of the IC according to the present application.

FIG. 10 is a diagram illustrating the formation of wiring in the process of manufacturing the IC according to the present application.

FIG. 11 is a diagram illustrating formation of an ohmic electrode in a conventional example.

[Explanation of symbols]

 1 Semi-insulating GaAs substrate 2 nGaAs layer 3 n + GaAs layer 4 n'GaAs layer 5 p + GaAs layer 6 pGaAs layer 10 Ni thin film 11 Ti thin film 12 Ni / Ti thin film 13 AuGe thin film 14 Au thin film 15 Al / Ti / Pt / Au gate electrode 16 WN gate electrode 17 Al thin film 20 Photoresist 21 Silicon nitride film

Claims (8)

[Claims] 1. A compound semiconductor device having an ohmic electrode on a compound semiconductor substrate, wherein the ohmic electrode is composed of an intermetallic compound composed of at least nickel and titanium. 2. A compound semiconductor device having an ohmic electrode on each region of a compound semiconductor substrate having an n-layer region and a p-layer region, wherein the ohmic electrodes of the n-layer region and the p-layer region have the same structure, and at least nickel and A compound semiconductor device comprising an intermetallic compound made of titanium. 3. The compound semiconductor device according to claim 1, further comprising a metal wiring containing Al on the ohmic electrode. 4. The compound semiconductor device according to claim 1, further comprising: on the ohmic electrode, a wiring made of an intermetallic compound including at least nickel and titanium which is the same as the ohmic electrode forming material. And a compound semiconductor device. 5. A method of manufacturing a compound semiconductor device according to claim 1, wherein a nickel thin film is formed on the compound semiconductor substrate,
A step of forming a titanium thin film on the nickel thin film, and a step of reacting the nickel thin film and the titanium thin film by heat treatment to form an intermetallic compound of nickel and titanium to form an ohmic electrode. A method of manufacturing a compound semiconductor device having the characteristics. 6. The method of manufacturing a compound semiconductor device according to claim 2, wherein a nickel thin film is formed on the n layer and the p layer region of the compound semiconductor having the n layer region and the p layer region, and the nickel thin film. A step of forming a titanium thin film thereon, a step of reacting the nickel thin film and the titanium thin film by heat treatment to form an intermetallic compound of nickel and titanium, and simultaneously forming ohmic electrodes of an n layer and ap layer, A method for manufacturing a compound semiconductor device, comprising: 7. The method of manufacturing a compound semiconductor device according to claim 1, wherein a step of performing ion implantation for forming a conductive layer on a compound semiconductor substrate, a step of forming a nickel thin film on the substrate, A compound semiconductor device comprising: a step of forming a titanium thin film on a nickel thin film; and a step of simultaneously performing a heat treatment for activating the implanted ions and a heat treatment for forming the intermetallic compound of nickel and titanium. Manufacturing method. 8. The method of manufacturing a compound semiconductor device according to claim 4, wherein a nickel thin film is formed on the compound semiconductor substrate,
A step of forming a titanium thin film on the nickel thin film, a step of etching the nickel thin film and the titanium thin film into a wiring shape, and a step of reacting the nickel thin film and the titanium thin film by heat treatment to form an intermetallic compound And a step of simultaneously forming an ohmic electrode and a wiring in the same process.