JPH0945858A - Semiconductor integrated circuit and manufacture thereof - Google Patents
Semiconductor integrated circuit and manufacture thereofInfo
- Publication number
- JPH0945858A JPH0945858A JP7214087A JP21408795A JPH0945858A JP H0945858 A JPH0945858 A JP H0945858A JP 7214087 A JP7214087 A JP 7214087A JP 21408795 A JP21408795 A JP 21408795A JP H0945858 A JPH0945858 A JP H0945858A
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- Prior art keywords
- film
- lower electrode
- electrode film
- integrated circuit
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明はキャパシタを一体に
有する半導体集積回路に関し、特にＭＩＭ（Ｍｅｔａｌ
−Ｉｎｓｕｌａｔｏｒ−Ｍｅｔａｌ）キャパシタを備え
る半導体集積回路及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit integrally having a capacitor, and more particularly to a MIM (Metal).
-Insulator-Metal) A semiconductor integrated circuit including a capacitor and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】半導体集積回路で所要の回路を構成する
場合、受動素子としてのキャパシタを構成することが要
求されることがあり、従来では半導体基板の表面に導電
膜−絶縁膜−導電膜を積層形成したスタック構成のＭＩ
Ｍキャパシタが提案されている。このようなＭＩＭキャ
パシタを用いて図３に示すような回路を構成する場合、
ＦＥＴ１０のソースに接続したＭＩＭキャパシタの他端
を接地する必要がある。このような回路が構成されるマ
イクロ波半導体集積回路では、接地は半導体基板の裏面
側に設けた金属膜で構成されるため、ＭＩＭキャパシタ
の他端をこの裏面金属に接続する必要があり、このため
従来のＭＩＭキャパシタは図４に示す構造がとられてい
る。2. Description of the Related Art When a required circuit is formed by a semiconductor integrated circuit, it is sometimes required to form a capacitor as a passive element. Conventionally, a conductive film-insulating film-conductive film is formed on the surface of a semiconductor substrate. MI with a stacked structure formed by stacking
M capacitors have been proposed. When a circuit as shown in FIG. 3 is constructed using such an MIM capacitor,
The other end of the MIM capacitor connected to the source of the FET 10 needs to be grounded. In a microwave semiconductor integrated circuit having such a circuit, the ground is composed of a metal film provided on the back surface side of the semiconductor substrate, and therefore it is necessary to connect the other end of the MIM capacitor to this back surface metal. Therefore, the conventional MIM capacitor has the structure shown in FIG.
【０００３】図４（ａ），（ｂ）はこのようなＭＩＭキ
ャパシタの平面配置図とそのＢＢ線断面図である。ま
た、図５はその製造方法を工程順に示す断面図である。
まず、図５（ａ）のように、半絶縁性基板２１上に金属
膜３１を形成し、この金属膜３１をドライエッチング技
術によりキャパシタの容量値に対応した面積に形成し、
キャパシタ下部電極膜２２を形成する。このとき、バイ
アホールを形成する領域では下部電極膜２２の一部を除
去しておく。ついで、図５（ｂ）のように、全面にＳｉ
Ｏ2 等の絶縁膜２３を全面に形成する。そして、前記下
部電極膜２２に対応した領域を覆っている絶縁膜２３を
除去し、下部電極膜２２を露呈させた後、図５（ｃ）の
ように、全面にキャパシタの誘電体膜となる絶縁膜３２
を形成し、かつ下部電極膜２２に対応した領域の絶縁膜
３２を残してその他は取り除き、キャパシタ誘電体膜２
４を形成する。4 (a) and 4 (b) are a plan layout view of such an MIM capacitor and a cross-sectional view taken along line BB thereof. Further, FIG. 5 is a sectional view showing the manufacturing method in order of steps.
First, as shown in FIG. 5A, a metal film 31 is formed on the semi-insulating substrate 21, and this metal film 31 is formed in an area corresponding to the capacitance value of the capacitor by a dry etching technique.
The capacitor lower electrode film 22 is formed. At this time, part of the lower electrode film 22 is removed in the region where the via hole is formed. Then, as shown in FIG.
An insulating film 23 such as O 2 is formed on the entire surface. Then, after removing the insulating film 23 covering the region corresponding to the lower electrode film 22 and exposing the lower electrode film 22, a dielectric film of a capacitor is formed on the entire surface as shown in FIG. 5C. Insulation film 32
Is formed, and the insulating film 32 in the region corresponding to the lower electrode film 22 is left, and the others are removed to remove the capacitor dielectric film 2
4 is formed.
【０００４】さらに、図５（ｄ）のように、バイアホー
ル形成領域の周辺に沿って前記絶縁膜２３にスルーホー
ル２９を形成して前記下部電極膜２２をスルーホール２
９により電気接続した状態とし、その上から金属膜３３
を形成する。そして、図５（ｅ）のように、この金属膜
３３をドライエッチング技術により選択除去すること
で、前記誘電体膜２４の上に上部電極膜２５を形成し、
前記スルーホール２９を含むバイアホール形成領域に表
面金属膜２８を形成する。その後、図５（ｆ）のよう
に、半絶縁性基板２１の厚さを薄くした後、裏面から選
択的にエッチングしてバイアホール２６を開口し、かつ
この開口内面を含む半絶縁性基板２１の裏面に金属膜を
形成することでバイアホール金属膜２７を形成する。Further, as shown in FIG. 5D, a through hole 29 is formed in the insulating film 23 along the periphery of the via hole forming region to form the lower electrode film 22 through the through hole 2.
9 and the metal film 33 from above.
To form Then, as shown in FIG. 5E, the metal film 33 is selectively removed by a dry etching technique to form an upper electrode film 25 on the dielectric film 24.
A surface metal film 28 is formed in the via hole formation region including the through hole 29. After that, as shown in FIG. 5F, after the thickness of the semi-insulating substrate 21 is reduced, the back surface is selectively etched to open the via hole 26, and the semi-insulating substrate 21 including the inner surface of the opening is formed. A via hole metal film 27 is formed by forming a metal film on the back surface of the.
【０００５】このＭＩＭキャパシタでは、図４のよう
に、上部電極膜２５、誘電体膜２４、及び下部電極膜２
２によりＭＩＭキャパシタＣが構成される。そして、下
部電極膜２２はスルーホール２９を介して表面金属膜２
８に接続され、さらにバイアホール金属膜２７に電気接
続されることになる。したがって、ＭＩＭキャパシタＣ
の一端はＦＥＴ１０のソースに接続され、他端は接地さ
れることになる。In this MIM capacitor, as shown in FIG. 4, the upper electrode film 25, the dielectric film 24, and the lower electrode film 2 are formed.
2 constitutes the MIM capacitor C. The lower electrode film 22 is formed on the surface metal film 2 through the through hole 29.
8 and further electrically connected to the via hole metal film 27. Therefore, the MIM capacitor C
Will be connected to the source of the FET 10 and the other end will be grounded.
【０００６】[0006]
【発明が解決しようとする課題】この従来のＭＩＭキャ
パシタの構成では、バイアホールの領域とＭＩＭキャパ
シタの領域が個別にチップ基板内に形成されるため、Ｍ
ＩＭキャパシタの下部電極膜の接地配線とバイアホール
の接地配線がそれぞれ必要となり、半導体集積回路のチ
ップサイズが大きくなるという問題がある。特に、ＦＥ
Ｔのソースに直接キャパシタを接続するようなマイクロ
波回路においては、ＦＥＴのソースに低周波を十分に接
地するために大きな容量が必要であるため、キャパシタ
の専有面積は大きく、チップサイズが大きくなるという
問題がある。In this conventional MIM capacitor structure, since the via hole region and the MIM capacitor region are separately formed in the chip substrate, M
There is a problem that the ground wiring of the lower electrode film of the IM capacitor and the ground wiring of the via hole are required respectively, which increases the chip size of the semiconductor integrated circuit. In particular, FE
In a microwave circuit in which a capacitor is directly connected to the source of T, a large capacitance is required to sufficiently ground the low frequency to the source of the FET, so that the area occupied by the capacitor is large and the chip size is large. There is a problem.
【０００７】また、従来のＭＩＭキャパシタの構成で
は、バイアホール金属膜とＭＩＭキャパシタとを電気接
続するためにスルーホールを形成する必要があり、その
ための製造工数が独立して必要であり、製造工程数が増
加する原因となっている。本発明は、キャパシタの専有
面積を低減してチップの小型化を可能とし、かつ製造工
数を削減して製造の容易化を可能にした半導体集積回路
及びその製造方法を提供することを目的とする。Further, in the conventional MIM capacitor structure, it is necessary to form a through hole for electrically connecting the via-hole metal film and the MIM capacitor, and the number of manufacturing steps for that is required independently. This is the cause of the increase in the number. SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor integrated circuit and a method of manufacturing the same that can reduce the area occupied by a capacitor to reduce the size of a chip and reduce the number of manufacturing steps to facilitate the manufacturing. .
【０００８】[0008]
【課題を解決するための手段】本発明の半導体集積回路
は、基板上に下部電極膜、誘電体膜、上部電極膜の積層
構造からなるＭＩＭキャパシタが形成され、かつ基板に
は下部電極膜の直下にバイアホールが形成され、バイア
ホール金属膜が下部電極膜に接続されている構成とされ
る。この場合、バイアホール金属膜は基板の裏面に形成
され、半導体集積回路の接地電極として構成される。In a semiconductor integrated circuit of the present invention, an MIM capacitor having a laminated structure of a lower electrode film, a dielectric film, and an upper electrode film is formed on a substrate, and the substrate has a lower electrode film. A via hole is formed immediately below, and the via hole metal film is connected to the lower electrode film. In this case, the via-hole metal film is formed on the back surface of the substrate and serves as the ground electrode of the semiconductor integrated circuit.
【０００９】また、本発明の製造方法は、半導体集積回
路の基板の表面に設けた下地の絶縁膜上に所要パターン
の金属膜からなる下部電極膜を形成し、この下部電極膜
上を含む基板の表面上に絶縁膜を形成し、この絶縁膜を
選択エッチングして下部電極膜の所要領域を開口し、全
面に誘電体膜を形成し、この誘電体膜上に金属膜を形成
し、誘電体膜と金属膜を個々に或いは同時に選択エッチ
ングして誘電体膜と上部電極膜を形成し、下部電極の直
下の基板に下部電極膜に達するまでの開口を基板の裏面
側から形成し、この開口を含む基板の裏面側に金属膜を
形成してバイアホールを形成する工程とを含んでいる。Further, according to the manufacturing method of the present invention, a lower electrode film made of a metal film having a desired pattern is formed on an underlying insulating film provided on the surface of a substrate of a semiconductor integrated circuit, and the substrate including the lower electrode film is formed. An insulating film is formed on the surface of the, the insulating film is selectively etched to open a required region of the lower electrode film, a dielectric film is formed on the entire surface, a metal film is formed on the dielectric film, and a dielectric film is formed. The body film and the metal film are selectively etched individually or simultaneously to form the dielectric film and the upper electrode film, and an opening is formed in the substrate immediately below the lower electrode until the lower electrode film is reached. Forming a via hole by forming a metal film on the back surface side of the substrate including the opening.
【００１０】[0010]
【発明の実施の形態】次に、本発明の実施形態を図面を
参照して説明する。図１（ａ），（ｂ）は本発明のＭＩ
Ｍキャパシタの平面配置図とそのＡＡ線断面図であり、
図３に示した回路を構成した例である。また、図２はこ
のＭＩＭキャパシタの製造方法を工程順に示す断面図で
ある。以下、製造工程に従ってＭＩＭキャパシタの構成
を説明する。先ず、図２（ａ）のように、半絶縁性基板
１上に金属膜１１を形成し、ドライエッチング技術によ
りこの金属膜１１をキャパシタの容量値に対応した面積
に選択エッチングし、キャパシタの下部電極膜２を形成
する。このとき、下部電極膜２は後工程で形成するバイ
アホールの直上を含む領域に矩形または円形等に形成す
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. 1A and 1B show the MI of the present invention.
FIG. 2 is a plan view of the M capacitor and a cross-sectional view taken along the line AA,
It is an example which constituted the circuit shown in FIG. 2A to 2D are sectional views showing a method of manufacturing this MIM capacitor in the order of steps. The configuration of the MIM capacitor will be described below according to the manufacturing process. First, as shown in FIG. 2A, a metal film 11 is formed on the semi-insulating substrate 1, and the metal film 11 is selectively etched by a dry etching technique to have an area corresponding to the capacitance value of the capacitor. The electrode film 2 is formed. At this time, the lower electrode film 2 is formed in a rectangular shape, a circular shape, or the like in a region including immediately above a via hole formed in a later step.
【００１１】次いで、図２（ｂ）のように、ＳｉＯ2 等
の絶縁膜３を全面に形成する。さらに、ＭＩＭキャパシ
タの下部電極膜２に対応した領域を覆っている絶縁膜３
を除去し、下部電極膜２を必要とされる面積だけ露呈さ
せる。その後、図２（ｃ）のように、キャパシタの誘電
体膜となる絶縁膜１２を形成する。さらに、図２（ｄ）
のように、その上に金属膜１３を形成し、これらの絶縁
膜１２と金属膜１３とを選択エッチングにより下部電極
膜２に対応した領域だけ残し、不要部を取り除くこと
で、所要面積の誘電体膜４と上部電極膜５とが形成さ
れ、これらでＭＩＭキャパシタＣが形成される。Next, as shown in FIG. 2B, an insulating film 3 of SiO 2 or the like is formed on the entire surface. Further, the insulating film 3 covering the region corresponding to the lower electrode film 2 of the MIM capacitor
Are removed to expose the lower electrode film 2 in a required area. After that, as shown in FIG. 2C, the insulating film 12 which becomes the dielectric film of the capacitor is formed. Furthermore, FIG. 2 (d)
As described above, the metal film 13 is formed thereon, and the insulating film 12 and the metal film 13 are selectively etched to leave only a region corresponding to the lower electrode film 2, and unnecessary portions are removed. The body film 4 and the upper electrode film 5 are formed, and these form the MIM capacitor C.
【００１２】しかる後、図２（ｅ）のように、全面半絶
縁性基板１の厚さを薄くした後、裏面にバイアホール６
を開口し、この開口内に前記下部電極膜２を裏面側から
露呈させる。ついで、この開口を含む半絶縁性基板１の
裏面に金属膜を形成し、バイアホール金属膜７を形成す
る。なお、前記誘電体膜４と上部電極膜５とはそれぞれ
独立したエッチング工程で選択エッチングしてもよい。After that, as shown in FIG. 2E, after the thickness of the whole semi-insulating substrate 1 is reduced, the via hole 6 is formed on the back surface.
Is opened, and the lower electrode film 2 is exposed in the opening from the back surface side. Then, a metal film is formed on the back surface of the semi-insulating substrate 1 including the opening, and a via hole metal film 7 is formed. The dielectric film 4 and the upper electrode film 5 may be selectively etched in independent etching steps.
【００１３】このように形成されたＭＩＭキャパシタＣ
では、下部電極膜２、誘電体膜４、上部電極膜５により
ＭＩＭキャパシタＣが形成され、かつ上部電極膜５はＦ
ＥＴ１０のソースに電気接続される。また、下部電極膜
２はバイアホール金属膜７に直接接続されて接地され、
これにより図３の回路が構成される。したがって、ＭＩ
ＭキャパシタＣの下部電極膜２を接地するための配線構
造を別個に設ける必要がなく、構造の簡略化が実現でき
る。また、このＭＩＭキャパシタＣでは、バイアホール
６の領域とＭＩＭキャパシタＣの領域とが平面上で重ね
られた状態で形成されるため、従来のように両者を個別
に形成した場合に比較して、半導体集積回路に占める面
積を低減することができる。換言すれば、同一平面面積
において、より大面積のＭＩＭキャパシタを形成するこ
とが可能となる。The MIM capacitor C thus formed
Then, the MIM capacitor C is formed by the lower electrode film 2, the dielectric film 4, and the upper electrode film 5, and the upper electrode film 5 is F
Electrically connected to the source of ET10. Further, the lower electrode film 2 is directly connected to the via-hole metal film 7 and grounded,
This constitutes the circuit of FIG. Therefore, MI
Since it is not necessary to separately provide a wiring structure for grounding the lower electrode film 2 of the M capacitor C, the structure can be simplified. Further, in this MIM capacitor C, the region of the via hole 6 and the region of the MIM capacitor C are formed in a state of being overlapped with each other on a plane, and therefore, as compared with the conventional case where the both are individually formed, The area occupied by the semiconductor integrated circuit can be reduced. In other words, it is possible to form a larger area MIM capacitor in the same plane area.
【００１４】すなわち、図１のＭＩＭキャパシタを、図
４の従来構成と同じ平面面積に形成した場合、図４に示
されるバイアホール２６及びスルーホール２９の面積の
和が図１のキャパシタの容量面積として利用できる。一
般に、バイアホールに１００μｍ角程度の面積が必要さ
れるとすると、スルーホールを含め１５０μｍ角程度の
面積がバイアホール形成に必要となり、誘電体膜の誘電
率５、厚さ２５００Åとしたとき、Ｃ＝５．６〔ｐＦ〕
程度のキャパシタ面積に等しくなる。したがって、キャ
パシタの容量として１０〔ｐＦ〕必要とされる場合に
は、本発明のキャパシタ面積が４００００μｍ2 に対
し、従来のキャパシタ面積は６２５００μｍ 2 となり、
約１．６倍であることが理解できる。That is, the MIM capacitor of FIG.
4 is formed in the same plane area as the conventional configuration of No. 4 shown in FIG.
Of the area of the via hole 26 and the through hole 29
The sum can be used as the capacitance area of the capacitor of FIG. one
Generally, a via hole requires an area of about 100 μm square.
If it is about 150 μm square including through holes,
Area is required to form via holes, and the dielectric
When the rate is 5 and the thickness is 2500 Å, C = 5.6 [pF]
Equal to the capacitor area. Therefore,
When 10 [pF] is required as the capacity of Pashita
Has a capacitor area of 40,000 μm of the present invention.2Against
However, the conventional capacitor area is 62500 μm. 2Becomes
It can be seen that it is about 1.6 times.
【００１５】したがって、これから同じ容量のキャパシ
タを構成する場合、従来構成に比較して本実施形態では
その平面専有面積を縮小することが可能となる。すなわ
ち、前記した１０〔ｐＦ〕のＭＩＭキャパシタを構成す
るとした場合、本実施形態ではキャパシタの面積を従来
に比較して６０％に低減でき、半導体集積回路の小型化
が実現できる。Therefore, when capacitors having the same capacitance are to be constructed, the area occupied by the plane can be reduced in this embodiment as compared with the conventional configuration. That is, when the above-mentioned 10 [pF] MIM capacitor is configured, in the present embodiment, the area of the capacitor can be reduced to 60% as compared with the conventional case, and the semiconductor integrated circuit can be downsized.
【００１６】また、本実施形態の製造方法では、工程の
途中でスルーホールを形成する工程が不要であるため、
このスルーホールの形成に必要とされる開口のエッチン
グ、開口内への導電材の充填等の工程が不要となり、製
造工程数を削減して製造の容易化が可能となる。Further, in the manufacturing method of this embodiment, the step of forming the through hole is not required during the process,
The steps of etching the openings and filling the openings with a conductive material, which are necessary for forming the through holes, are not necessary, and the number of manufacturing steps can be reduced to facilitate the manufacturing.
【００１７】[0017]
【発明の効果】以上説明したように本発明は、ＭＩＭキ
ャパシタの直下にバイアホールを配置しており、ＭＩＭ
の下部電極膜をバイアホール金属膜に電気接続して接地
回路を構成しているため、所定の容量を得るためのＭＩ
Ｍキャパシタの専有面積を低減でき、半導体集積回路の
小型化が実現できる。また、ＭＩＭキャパシタの下部電
極膜をバイアホール金属膜に直接接続して接地すること
ができるため、ＭＩＭキャパシタに対する接地配線を独
立して形成する必要がなく、構造の簡略化が実現でき
る。As described above, according to the present invention, the via hole is arranged immediately below the MIM capacitor.
Since the lower electrode film of is electrically connected to the via-hole metal film to form a ground circuit, MI for obtaining a predetermined capacitance is required.
The area occupied by the M capacitor can be reduced, and the semiconductor integrated circuit can be downsized. Further, since the lower electrode film of the MIM capacitor can be directly connected to the via-hole metal film and grounded, it is not necessary to separately form the ground wiring for the MIM capacitor, and the structure can be simplified.
【００１８】また、本発明の製造方法では、ＭＩＭキャ
パシタの下部電極膜とバイアホール金属膜とを電気接続
するためのスルーホールの製造工程が不要となり、製造
工程数を削減し、製造を容易に行うことができる。Further, according to the manufacturing method of the present invention, the manufacturing process of the through hole for electrically connecting the lower electrode film of the MIM capacitor and the via-hole metal film is unnecessary, the number of manufacturing processes is reduced, and the manufacturing is facilitated. It can be carried out.
【図１】本発明のＭＩＭキャパシタの一実施形態の平面
配置図とそのＡＡ線断面図である。FIG. 1 is a plan layout view and an AA line sectional view of one embodiment of an MIM capacitor of the present invention.
【図２】図１のＭＩＭキャパシタの製造方法を工程順に
示す断面図である。2A to 2D are cross-sectional views showing a method of manufacturing the MIM capacitor of FIG. 1 in process order.
【図３】図１のＭＩＭキャパシタを含む半導体集積回路
の等価回路図である。FIG. 3 is an equivalent circuit diagram of a semiconductor integrated circuit including the MIM capacitor of FIG.
【図４】従来のＭＩＭキャパシタの一例の平面配置図と
そのＢＢ線断面図である。FIG. 4 is a plan layout view of an example of a conventional MIM capacitor and a cross-sectional view taken along line BB thereof.
【図５】図４のＭＩＭキャパシタの製造方法を工程順に
示す断面図である。FIG. 5 is a cross-sectional view showing the method of manufacturing the MIM capacitor of FIG. 4 in order of steps.
１ 半絶縁性基板 ２ 下部電極膜 ４ 誘電体膜 ５ 上部電極膜 ６ バイアホール ７ バイアホール金属膜 １０ ＦＥＴ 1 semi-insulating substrate 2 lower electrode film 4 dielectric film 5 upper electrode film 6 via hole 7 via hole metal film 10 FET
Claims (4)
部電極膜、誘電体膜、上部電極膜の積層構造からなるＭ
ＩＭキャパシタを備える半導体集積回路において、前記
基板には前記下部電極膜の直下にバイアホールが形成さ
れ、バイアホール金属膜が前記下部電極膜に接続されて
いることを特徴とする半導体集積回路。1. An M having a laminated structure of a lower electrode film, a dielectric film and an upper electrode film formed on a substrate of a semiconductor integrated circuit.
A semiconductor integrated circuit comprising an IM capacitor, wherein a via hole is formed in the substrate immediately below the lower electrode film, and a via hole metal film is connected to the lower electrode film.
形成され、半導体集積回路の接地電極として構成される
請求項１の半導体集積回路。2. The semiconductor integrated circuit according to claim 1, wherein the via-hole metal film is formed on the back surface of the substrate and serves as a ground electrode of the semiconductor integrated circuit.
成または搭載された素子の接地端との間に介挿され、上
部電極膜は前記素子に接続され、下部電極膜がバイアホ
ールに接続される請求項２の半導体集積回路。3. The MIM capacitor is inserted between a ground end of an element formed or mounted on a semiconductor integrated circuit, the upper electrode film is connected to the element, and the lower electrode film is connected to a via hole. Item 2. The semiconductor integrated circuit of item 2.
地の絶縁膜上に所要パターンの金属膜からなる下部電極
膜を形成する工程と、この下部電極膜上を含む前記基板
の表面上に絶縁膜を形成する工程と、この絶縁膜を選択
エッチングして前記下部電極膜の所要領域を開口する工
程と、全面に誘電体膜を形成する工程と、この誘電体膜
上に金属膜を形成する工程と、前記誘電体膜と金属膜を
個々に或いは同時に選択エッチングして誘電体膜と上部
電極膜を形成する工程と、前記下部電極の直下の前記基
板に下部電極膜に達するまでの開口を基板の裏面側から
形成する工程と、この開口を含む基板の裏面側に金属膜
を形成してバイアホールを形成する工程とを含むことを
特徴とする半導体集積回路の製造方法。4. A step of forming a lower electrode film made of a metal film having a required pattern on an underlying insulating film provided on the surface of a substrate of a semiconductor integrated circuit, and on the surface of the substrate including the lower electrode film. Forming an insulating film, selectively etching the insulating film to open a required region of the lower electrode film, forming a dielectric film on the entire surface, and forming a metal film on the dielectric film And a step of selectively etching the dielectric film and the metal film individually or simultaneously to form a dielectric film and an upper electrode film, and an opening in the substrate immediately below the lower electrode until reaching the lower electrode film. And a step of forming a metal film on the back surface side of the substrate including the opening to form a via hole, a method of manufacturing a semiconductor integrated circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7214087A JPH0945858A (en) | 1995-07-31 | 1995-07-31 | Semiconductor integrated circuit and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7214087A JPH0945858A (en) | 1995-07-31 | 1995-07-31 | Semiconductor integrated circuit and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0945858A true JPH0945858A (en) | 1997-02-14 |
Family
ID=16650022
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7214087A Pending JPH0945858A (en) | 1995-07-31 | 1995-07-31 | Semiconductor integrated circuit and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0945858A (en) |
-
1995
- 1995-07-31 JP JP7214087A patent/JPH0945858A/en active Pending
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