JPH0945775A - Wiring method and its automatic wiring method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce crosstalk without using a useless wiring region by arranging a wiring path having a first signal small in wiring load capacity and through time and a wiring path having a second signal large in wiring load capacity and through time so that they may run parallel. SOLUTION: Wiring is made so that a wiring path (first net) having a first signal small in wiring load capacity and through time, and a wiring path (second net) having a second signal large in wiring load capacity and through time of may run parallel. To be more preferable, the wiring is so made as to fulfill the condition that the signals of the first and second nets n1 and n2 do not change at the same time. Hereby, the signal line of the first net n1 is easy to generate a noise, but since the wiring load capacity of the paths running in parallel is large, the influence of the crosstalk becomes small. On the other hand, the signal line of the second net n2 is hard to generate a noise, so the influence of the crosstalk to the paths running in parallel becomes small.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic wiring system for a semiconductor integrated circuit, and more particularly to a wiring system in which crosstalk noise between parallel wirings does not exceed a permissible range, and a method for automatically searching a route thereof.

[0002]

2. Description of the Related Art With the progress of semiconductor technology, as the speed and density of LSIs increase, the crosstalk noise generated between adjacent wirings deteriorates the signal waveform and cannot be ignored as a cause of malfunction. . Crosstalk noise is noise that is induced in one signal line (hereinafter, referred to as a noise source line) of wirings running in parallel to the other signal line (hereinafter, referred to as a noise receiving line). When the mutual capacitance between the noise source line and the noise receiving line is Cm, the wiring capacitance of the noise receiving line is C, and the signal change rate of the noise source line is dV / dt, the crosstalk noise (Vn) is

[Equation 1] In a relationship.

The following methods have been reported so far as methods for reducing such crosstalk noise.

(1) A method for limiting the length of wirings running in parallel in a circuit (hereinafter referred to as prior art 1; JP-A-3-334)
No. 7, JP-A-2-78248), (2)
A method of providing a control wiring (hereinafter, referred to as a shield) fixed to a predetermined potential such as a power supply potential between the wiring and the element (hereinafter, collectively referred to as a circuit component) (hereinafter, referred to as Prior Art 2).
Japanese Patent Laid-Open No. 6-29393, Japanese Patent Laid-Open No. 6-16
No. 3694), and (3) a method of increasing the distance between circuit components (hereinafter referred to as prior art 3; JP-A-5-82).
644).

[0005]

However, the conventional techniques 1, 2, and 3 of the related art have the following problems.

(1) According to the prior art 1, bending occurs due to the limitation of the wiring length, and the wiring rate decreases. (2) In the case of the conventional technique 2, the existence of the shield causes the wiring resource to be compressed and the wiring rate is lowered. (3) In the case of the conventional technique 3, the wiring resource that can be used is reduced by increasing the interval, and the wiring rate is reduced. The problem is that it decreases. This is because these conventional techniques are designed to be safer than necessary, considering only spatial elements.

In view of the above problems, the present invention provides a wiring method for reducing crosstalk noise within a predetermined reference range without using unnecessary bending of wiring or a wasteful wiring area due to a shield and its automatic wiring. The purpose is to provide a method.

[0008]

In order to achieve the above object, the automatic wiring system according to the present invention, as shown in FIG. 1A, has a condition that a wiring load capacitance and a signal through time are small (hereinafter referred to as condition 1- 1) under the condition that the first signal wiring path (hereinafter referred to as the first net) n1 and the wiring load capacitance and the signal through time are large (hereinafter referred to as condition 1-2). The second signal wiring line (hereinafter referred to as the second net) n2 is wired on the semiconductor chip in parallel. Here, the wiring load capacitance refers to the capacitance of the wiring itself plus the input capacitance of the element connected before the signal flows.The signal through time is the signal rise time or fall time. Say. In FIG. 1A, the solid line and the dotted line forming the first net n1 and the second net n2 mean that the line segments of the signal line exist in different wiring layers, and the crosses indicate wiring in different layers. Vias for connecting line segments, and ○ marks are input / output terminals of the device. In the following description, the conditions 1-1 and 1-2 are collectively referred to as the condition 1
Say.

Preferably, in addition to the condition 1, FIG.
As shown in (b), wiring is performed so as to satisfy the condition (hereinafter, referred to as condition 2) that the signals of the first and second nets do not change at the same time. The solid line in FIG. 1B is the net n.
The case where the signals of 1 and the net n2 both rise is shown, and the broken line shows the case where the signals of the net n1 and the net n2 both fall, but in both cases, there is no change at the same time. More preferably, the second net n2
The first net n1 is wired so as to run in parallel on both sides of. According to the above configuration, a net satisfying the condition 1-1, that is, a signal line having a small wiring load capacitance and a small slew time is likely to become a noise source for wirings running in parallel, but the wiring load capacitances of the paths running in parallel. Is large, the influence of crosstalk is small. On the other hand, a net satisfying the condition 1-2, that is, a signal line having a large wiring load capacitance and a large slew time is unlikely to be a noise source for parallel running wires, and the influence of crosstalk on parallel running paths is small. In addition, as shown in the timing chart of FIG. 1B, the two signal lines that satisfy the condition 2 have a heavy period (hereinafter, referred to as a signal change period) during which the signals of the wirings in the parallel running portions may change. Since one does not change, the other is stable when one is changing. Further, wiring according to the method of the present invention can be easily performed automatically according to the flow charts shown in FIGS. 2, 4, 5, 6, 9 and 10. Therefore, by performing the automatic wiring in accordance with these flowcharts, it is possible to determine the wiring route in which the crosstalk amount is suppressed to the predetermined allowable value or less without wasting the wiring resources.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a configuration diagram of the automatic wiring method according to the first embodiment of the present invention. As shown in FIG. 2, the automatic routing method according to the first embodiment of the present invention includes a rough routing process 1, a net information creation process 2, and a net classification process 3.
And noise net wiring processing 4 and wiring processing 5.

In the rough wiring processing 1, wiring length, wiring congestion, delay constraint required at the time of designing (hereinafter referred to as timing constraint), etc. are considered based on the logical connection of the input electric circuit. , Find the approximate route of each net. The method of obtaining the rough route is not particularly limited.

In the net information creation process 2, for all the nets obtained in the rough wiring process 1, the wiring load capacitance, the signal change period, the through time, and the wiring length of each parallel running portion (hereinafter referred to as parallel running wiring length). ). Hereinafter, the wiring load capacitance, the signal change period, and the through time will be collectively referred to as net information. The wiring load capacitance is obtained by multiplying the wiring length expected from the result of the rough wiring processing 1 (hereinafter, referred to as virtual wiring length) by the wiring capacitance per unit length of the signal wiring, and the signal of the net is input. It is the sum of the input capacitances of the elements. The virtual wiring length corresponds to the sum of the lengths connecting the centers of the rough grids, for example, in the case of the rough wiring length for dividing the layout area into the rough grids.

A method of obtaining the signal change period in the net information creating process 2 will be described with reference to FIG. Signals on normal wiring except for clocks and power supply wiring are flip-flops (F) controlled by the clock within one cycle of the clock.
F) must be propagated between. Find the time required to transfer a signal for each path and element between all FFs (the output of the gate may rise or fall) and determine the maximum deviation of the arrival time of the clock that controls the FFs. A value (clock skew) (here, assuming 0.5 ns, for example) is added to obtain the signal change period. Here, the time when the clock arrives at the FF is regarded as 0. For example, the signal change period of the net n4 is [0.6n
s + 0.8ns, 0.6ns + 1.3ns + 0.5ns
+0.5 ns] = [1.4 ns, 2.9 ns].

The net classification process 3 shown in FIG. 2 is liable to generate noise or is easily damaged by noise based on the wiring load capacity and the through time of the net obtained in the net information creation process 2. A net that applies to -1
Condition 1-2 with strong noise resistance and less noise generation
(Hereinafter, the nets that meet the conditions 1-1 and 1-2 are collectively referred to as noise nets) are extracted, and the nets are classified and distinguished from the other nets.

In the noise net wiring processing 4, for the classified noise nets, a net that satisfies the condition 1-1 by keeping the crosstalk amount within the reference range within the range that satisfies the timing constraint such as delay between FFs. Condition 1 on both sides of
Wiring is performed so that the nets satisfying −2 run in parallel and the nets satisfying the condition 1-1 are dispersed.
For example, this is to enumerate candidates of a set of nets that can run in parallel within the noise net with the crosstalk amount within a reference range, and actually run in parallel from the position of the input / output terminals of the device. It can be realized by a method such as determining a set.

In the wiring process 5, the remaining wiring is wired while determining the crosstalk amount. In this processing, the determination of the amount of crosstalk may be performed at the same time as the route search, or
It may be performed every time a route is searched for one net. The process for simultaneously determining the route search will be described in the second embodiment of the present invention, and the process for determining the route search for one net will be described later in the third embodiment. As an example of obtaining the crosstalk amount, it is possible to adopt a method of multiplying the crosstalk coefficient obtained by the experiment by the parallel wiring length and the time change rate of the signal (operating voltage divided by the through time). it can.

That is, according to the first embodiment of the present invention, a net which meets the condition 1-1, that is, a net which is apt to receive noise or becomes a noise source and a condition 1-
After classifying into 3 types of nets conforming to 2, that is, noise-resistant nets and other normal nets, and wiring that protects nets that are susceptible to noise or easily generated by noise-resistant nets Then, a normal net is wired to keep the crosstalk amount within the allowable value.

FIG. 4 is a block diagram of an automatic wiring method according to the second embodiment of the present invention. The automatic wiring method according to the second embodiment of the present invention, as shown in FIG.
And a net information creation process 2 and a wiring process 6. The schematic wiring process 1 and the net information creation process 2 in FIG. 4 are the same as in the case of the first embodiment of the present invention shown in FIG. In the wiring process 6, the crosstalk amount from the parallel wiring and the crosstalk amount to the parallel wiring are calculated when searching the route of the net. This is added to the so-called cost (hereinafter referred to as the search cost), which is an evaluation index when searching for this, and when the relationship with the parallel wiring satisfies the above condition 1 or condition 2, the search cost is less than 1. The wiring route is searched for by multiplying by the coefficient of or by reducing a certain constant. The search cost is preferably small, and the search is performed so that the cost is minimized. That is, the second embodiment of the present invention is to calculate the crosstalk amount with the parallel wiring at the same time as the route search and add the crosstalk amount to the cost as an index of goodness.

FIG. 5 is a block diagram of an automatic wiring method according to a third embodiment of the present invention. As shown in FIG. 5, the automatic wiring method according to the third embodiment of the present invention includes a rough wiring process 1,
Net information creation processing 2, search cost creation processing 7, wiring route search processing 8, crosstalk violation determination processing 9,
The wiring route determination process 10 and the search cost update process 11 are included. The general wiring process 1 and the net information creation process 2 are the same as those in the first embodiment of the present invention. In the search cost creation process 7, using the net information obtained in the net information creation process 2, a search cost is created so as to meet the condition 1 for the wiring running in parallel. For example, three types of search costs are prepared for a net that satisfies the condition 1-1, a net that satisfies the condition 1-2, and a net other than that, and a wiring that allows the net satisfying the condition 1-1 and the net satisfying the condition 1-2 to pass through. A desired search cost can be obtained by making the regions alternate and allowing other nets to pass through.

In the wiring route search process 8, the route of one unprocessed net is searched based on the search cost obtained in the search cost creation process 7. At this time, the search is performed while simultaneously evaluating whether the signal change period of the parallel running net is the same as that of the net under search. For example, when the signal change periods are the same, the search is performed while adding a certain constant to the search cost.

In the crosstalk violation determination processing 9, first,
The net information is temporarily updated according to the actual wiring length of the searched route. At this time, not only the searched net but also related net information is temporarily updated. For example, if the net n4 is searched for in FIG.
The net information of 5 and n6 is also updated. Next, the parallel running wire length of the net running parallel to this route is obtained, and the crosstalk amount of each of the searched route and the net running parallel thereto is found using these net information and the parallel running wire length, and the net is obtained. , And whether it is less than or equal to the allowable value imposed on parallel running nets.

In the wiring route determination process 10, if the calculated amount of crosstalk noise is less than or equal to the allowable value imposed on the net and the parallel running nets, the selected route is determined as the wiring route of the net. And update the net information. If the allowable value is exceeded, the net information temporarily updated in the crosstalk violation determination processing 9 is returned to the original, and the search cost associated with the selected route is temporarily updated. This increases the search cost of a portion having a large amount of crosstalk in a straight line portion (hereinafter referred to as a line segment section) that constitutes the searched route, and a net that does not share a signal change period with the searched net. This is realized by the search cost update processing 11 or the like that reduces the cost of the wiring areas running in parallel. After that, the wiring route search process 8, the crosstalk violation determination process 9, and the wiring route determination process 10 are repeated until the crosstalk noise amount becomes equal to or less than the allowable value.

FIG. 6 is a block diagram of an automatic wiring method according to the fourth embodiment of the present invention. As shown in FIG. 6, the automatic wiring method according to the fourth embodiment of the present invention includes a wiring process 12,
The crosstalk violation determination processing 13 and the rewiring processing 14 are included. In the wiring process 12, a detailed route of each net is obtained on the basis of the input logical connection of the electric circuit in consideration of the wiring length, the wiring congestion degree, the timing constraint and the like.
The method of obtaining the route is not particularly limited.

In the crosstalk violation determination processing 13, first, for all nets obtained in the wiring processing 12, similar to the net information creation processing 2 in the first to third embodiments of the present invention, the actual wiring length is calculated. Net information and parallel wiring length of each are obtained. Subsequently, based on the obtained net information and the parallel running wire length, the crosstalk amount received by the net itself and the crosstalk amount exerted on the parallel running nets are calculated,
Determine if each amount violates the restrictions imposed on each net. Hereinafter, a net that violates such a restriction is called a violating net.

In the rewiring processing 14, the violating net is peeled off and rewiring is performed. If there is almost no area to wire the stripped net, or if the net does not meet the timing constraint as a result of rewiring, there is no particular limitation, but for example, the following method is used. deal with. That is, (1) a virtual wiring area is generated in an area that cannot be originally wired, and the search cost on the virtual wiring area is changed so as to satisfy the conditions 1 and 2 or the condition 1. If you want to shift the other wiring after searching the route above, deviate to determine the route. Here, the generation of a virtual wiring area means that the wiring area is divided into a plurality of grids, and in the case of a labyrinth method in which each grid is sequentially wired according to a predetermined rule, virtual grid areas are formed between the grids gr1 as shown in FIG. It means to generate the grid gr2. The change of the search cost will be described later.

(2) Alternatively, as shown in FIG. 8, it is checked in advance how much is left when the processed wiring is displaced so as to be pushed back, and the same cost as the above (1) is set in the information. Then, rewiring is performed based on it. FIG. 8A is a diagram showing a wiring result and a portion 84 where the wiring is displaced or a wiring width can be widened.
FIG.8 (b) is a figure which shows the margin degree which can push away wiring. 8A and 8B, the hatched rectangular portion is the wiring prohibited area 81, and the vertical line is the processed wiring path 82. The white rectangle of the vertical line in FIG. 8A is the push-out possible area 84, and FIG. 8B shows the wiring 85 in which the push-out possible area 81 is pushed away. The black squares in FIG. 8 are vias 83 for connecting wirings in different layers.

The above method (1) or (2) will be dealt with, but regarding the search cost, if the net to be rerouted is a net having the condition 1-1, the condition 1-
2) If the net to be rerouted satisfies condition 1-2, a constant is subtracted from the search cost of the wiring region running in parallel with the net of condition 2. The desired cost is obtained by subtracting a constant. Further, at the time of search, the signal change period of the parallel running net and that of the rerouted net are compared, and if there is a common part, a route satisfying the condition 2 is searched for by adding a constant to the cost of the net under search. To do so.

FIG. 9 is a block diagram of an automatic wiring method according to the fifth embodiment of the present invention. As shown in FIG. 9, the automatic wiring method according to the fifth embodiment of the present invention includes a wiring process 12,
Crosstalk violation determination processing 13 and wiring width adjustment processing 15
Consists of The wiring process 12 and the crosstalk violation determination process 13 are the same as those in the fourth embodiment of the present invention.

In the wiring width adjustment processing 15, the wiring load capacities of the violating net and the net running in parallel with the violating net are compared, and the one having the smaller wiring load capacity is selected.
As shown in (a), a portion 84 in which the wiring width can be widened is extracted, and the crosstalk of the net satisfies the standard by the wiring capacitance and the through time which are increased by widening the portion, thereby eliminating the crosstalk violation. .

FIG. 10 is a block diagram of the automatic wiring method according to the sixth embodiment of the present invention. According to the automatic wiring method of the sixth embodiment of the present invention, as shown in FIG.
Crosstalk violation determination processing 13 and rewiring processing 14
And the wiring width adjustment processing 15. The sixth embodiment of the present invention is a combination of the fourth and fifth embodiments of the present invention. The order of the rewiring process 14 and the wiring width adjustment process 15 is not particularly limited.

[0031]

As described above, if two types of signal lines having different conditions for noise are wired in parallel according to the method of the present invention, the signal line having a small wiring load capacitance and a short through time is likely to become a noise source. However, the influence of crosstalk is less effective on a signal line having a large wiring load capacitance and a long slew time. On the other hand, since a signal line having a large wiring load capacitance is unlikely to become a noise source, it is unlikely to be a source of crosstalk to a signal line having a small wiring load capacitance.
Therefore, according to the present invention, the wiring rate is reduced due to the occurrence of unnecessary bending, which is a problem in the conventional technique, or the waste of the wiring resources such as the use of a wasteful wiring area for the shield is generated. In addition, it is possible to determine a wiring path in which the amount of crosstalk is suppressed to a permissible value or less, and further, since the malfunction due to the occurrence of noise is eliminated, the circuit operation at the time of design can be guaranteed.

According to the method of the present invention, the crosstalk noise between the wirings is reduced to within a predetermined reference value. As a result, the malfunction of the circuit is eliminated and the reliability of the LSI is improved. Can be realized.

According to the method of the present invention, it is possible to automatically and easily design a semiconductor integrated circuit in which crosstalk noise is reduced without wasting wiring resources.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a part of a semiconductor integrated circuit laid out by the method of the present invention and a diagram showing changes in signals in its wiring path.

FIG. 2 is a configuration diagram (flow chart) of an automatic wiring method according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a signal change period in each net.

FIG. 4 is a configuration diagram of an automatic wiring method according to a second embodiment of the present invention.

FIG. 5 is a configuration diagram of an automatic wiring method according to a third embodiment of the present invention.

FIG. 6 is a configuration diagram of an automatic wiring method according to a fourth embodiment of the present invention.

FIG. 7 is a diagram showing a virtual grid in a rewiring process according to a fourth embodiment of the present invention.

FIG. 8 is a diagram showing a repulsable area and a margin of repulsion in a rewiring process according to a fourth embodiment of the present invention.

FIG. 9 is a configuration diagram of an automatic wiring method according to a fifth embodiment of the present invention.

FIG. 10 is a configuration diagram of an automatic wiring method according to a sixth embodiment of the present invention.

[Explanation of symbols]

n1 to n6 net ○ I / O terminal of device × via slew1, slew2 through time of net n1 and n2 g3 to g5 device gr1 lattice gr2 virtual lattice 81 wiring prohibited area 82 processed wiring route 83 via 84 evitable area 85 eviction Wiring

Claims (2)

[Claims] 1. A wiring route for a first signal (hereinafter referred to as a first net) having a small wiring load capacitance and a signal through time, and a wiring route for a second signal having a large wiring load capacitance and a signal through time ( (Hereinafter referred to as the second net), the wiring system is characterized in that it runs in parallel. 2. A method of arranging a first net having a small wiring load capacity and a small signal slew time and a second net having a large wiring load capacity and a large signal slew time so as to run in parallel. A) rough wiring processing for obtaining a rough route of a plurality of nets including the first and second nets, and (b) for all nets obtained by the rough wiring processing,
Net information creation processing for obtaining the wiring load capacity, slew time, signal change period and parallel wiring length, (c) The first net, the second net based on the wiring load capacity and slew time obtained in the net information creation processing. Net and a net classification process for classifying the net into a third net other than these, (d) The second net runs in parallel on both sides of the first net, and signals of the first and second nets A noise net wiring process of wiring so as not to change at the same time, and (e) a wiring process of wiring the third net while determining the crosstalk amount, and an automatic wiring method.