JPH0943281A - Counting apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a wider measuring range and higher resolutions simultaneously by arranging a counting clock to allow automatic changeover between a low speed clock and a high speed clock. SOLUTION: This counting apparatus is provided with a pre-scaler 1 to generate a high speed clock and a low speed clock as counting clock signal 13 of a counter 3, a comparing register 4 for a low speed and a comparing register 5 for a high speed. It is also made up of a selector 6 to make a selection on which of the comparing registers 4 or 5 should be used, a comparator 7 to compare values of the counter 3 and the comparing register 5 selected by the selector 6 and a multiplexer 2 or the like to switch a counting clock by a coincidence signal 8 from the comparator 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a counter device.

[0002]

2. Description of the Related Art A counter device, in addition to a function of simply measuring a frequency, has a function of measuring a repeating cycle and a function of measuring the number of pulses of an input signal and reaching a preset predetermined value. Some have a function of outputting as a coincidence signal.

A counter device having this latter function is
In particular, it is incorporated in a computer and used as a timing signal having a desired interval. For example, it is used when the output level of the port is inverted by this timing signal or an interrupt is generated to execute a predetermined process at arbitrary intervals.
The input signal in this case becomes the basic clock signal (fclk) of the computer.

Referring to the block diagram of FIG. 3 showing a first conventional counter device of this kind, this device uses a prescaler 31 for determining a count clock from a basic clock signal 30, and an output from the prescaler 31. For example, a 16-bit counter 33 for counting the generated clock, a 16-bit compare register 32 for determining the cycle of the interval timer operation, a comparator 34 for comparing the values of the counter 33 and the compare register 32, A clear signal generation circuit 37 that generates a clear signal 36 based on the coincidence signal from the comparator 34.
With.

Next, the operation will be described. First, the clock used in the counter 33 is set in the prescaler 31. Also, the cycle of the inter-pulse timer operation is determined by setting an arbitrary value in the compare register 32 from the internal bus 35. The counter 33 starts counting, and when the value of the compare register 32 and the value of the counter 33 match, a match signal 40 is generated.

In this case, the possible count range is constant by the counter 33, and the resolution is also determined by setting the prescaler 31. Therefore, it is necessary to sacrifice the resolution in order to widen the count range. To get high resolution, you have to sacrifice the counting range.

Further, as a second conventional counter device,
There is a counter device that can switch back the resolution according to the number of counts. Referring to the block diagram of FIG. 4 which illustrates such a counter device, the counter device receives a input signal 102 and produces a prescaler 106 that produces a plurality of prescaled signals 112 scaled by different prescale factors. And a counter 100 that counts the input signal 102 or the prescaled signal 112 and generates a scale control signal 110 corresponding to the size of the count value from a plurality of upper digit pits, the prescaler 106, and the counter 100. And the scale control signal 11 connected between
The counter 1 selects one of the input signal 102 or the prescaled signal 112 in response to 0 at any time.
00, the selector 104 selects the prescaled signal 112 that is scaled by a larger prescale count (frequency division ratio) as the count value increases. Characterize.

According to this counter device, the resolution of the counter changes depending on the size of the stored count value.
In other words, the resolution is high while the count value is small, and the resolution is low as the count value is large. Therefore,
It is described that a high resolution can be obtained when the measurement range is wide and the measurement range is narrow (for example, low frequency measurement).

Here, the counter 100 includes a selector 104.
It counts up with the pre-scaled signal 108 output from. The higher digit plural bits of the counted up counter 100 appear on the left side of the counter 100 and the lower digit plural bits appear on the right side thereof. The higher-order bits have two functions, and their value forms a part of the count value and at the same time provides the selector 104 with information used for selecting an appropriate resolution.

That is, while the resolution can be increased while the count value is small, the resolution can be lowered and the measurement range can be expanded as the count value increases. Therefore, the measurement range must be expanded. It is not possible to simultaneously realize high resolution and high resolution.

[0011]

In the above-described first conventional counter device, the number of bits of the counter must be increased in order to achieve both a wide measurement range and high resolution. Therefore, the circuit scale becomes large. There was a flaw.

Further, in the above-mentioned second conventional counter device, by varying the resolution, it is possible to realize a high resolution in a narrow measurement range and to extend the measurement range with a low resolution with a single counter. Has been realized. However, such a counter device has a problem that a wide measurement range and high resolution cannot be realized at the same time.

In view of the above problems and the like, the present invention has the following problems. (1) To be able to measure the number of pulses in multiple digits and increase the measurement range without increasing the number of bits in a register counter or a circuit such as a computer.
At that time, do not sacrifice resolution. (2) To reduce the number of bits of the constituent circuit by almost half, and to speed up the counting function.

[0014]

The counter device of the present invention has a configuration in which a repeating pulse of an original input signal is directly or after being divided by a predetermined value, and is output as a clock signal. The measuring means for sequentially counting the number of pulses of the signal, and the detecting means for outputting a coincidence signal when the number of pulses counted by the counting means reaches a preset setting, the numerical value indicating the set value is a factor. In the case where the first numerical value part has a sum of a first numerical value part and a second numerical value part that is a prime number, the first numerical value part divides the factor into the predetermined value by the selecting means, A value obtained by removing the first numerical part by the factor is set as the set value, and counting is performed by the measuring means until the pulse numbers match, and the second numerical part is the original input by the alternative means. Signal directly to the clock No. and pear, and performs counting with the measuring means to the number of said pulses coincide.

In particular, the first and second numerical values are stored in different conveyor registers, respectively.

Further, in particular, the coincidence signal is used as a reset signal source for the selecting means and the measuring means.

Further, in particular, the predetermined value in the selecting means and the set value in the detecting means are input through an internal bus of the computer.

According to the present invention, since the second numerical value portion is divided by the factor, the count value is reduced, which reduces the bit number configuration and the circuit scale. Since the numerical part of 2 is directly counted without being divided, resolution is not sacrificed.

That is, according to the counter device of the present invention, 1
In particular, two measuring registers are provided for one measuring means, and the clock supplied by the counter is switched from the low law to the high speed by an alternative means by a coincidence signal with each comparing register.

At this time, a wider count range is realized for counting with the low speed clock, and high resolution is realized with the counting with the high speed clock.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to the block diagram of FIG. 1 showing a counter device according to an embodiment of the present invention, this embodiment takes a basic clock signal 12 applied to an input terminal 17 as an input, and inputs it to an arbitrary clock signal. A prescaler 1 that outputs a low-speed clock signal 11 divided into a predetermined value (integer), a basic clock signal 12 and a plurality of low-speed clock signals 11 are selected and output as a counter clock signal 13. Multiplexer 2 (hereinafter abbreviated as MPX)
And counting the number of pulses of the counter clock signal 13
The bit counter 3 and the low-speed conveyor register 4, the high-speed conveyor register 5, or the conveyor registers 4 and 5 for which count values are set in advance via the internal bus 16 are selected and output. The selector 6 which performs the comparison and the set value from the selector 6 and the count value from the counter 3 are compared, and when they match, a match signal 8 is output 8
The bit comparator 7 and the coincidence signal 8 of the comparator 7 are used as the clock input and the inverted output is the data (D).
D-type flip-flop 21 that receives the input, AND gate 15 that receives the coincidence signal and the inverted output of D-type flip-flop 21, and output terminal 1 of AND gate 15.
The delay circuit 20 which delays the output of 4 to be the reset input of the flip-flop 21, the AND gate 19 which receives the output (Q) of the flip-flop 21 and the coincidence signal 8 as two inputs, and the AND gate 19 It comprises a delay circuit 10 for delaying the output, and an OR gate 18 having two inputs, the output of the delay circuit 10 and the output of the delay circuit 20.

Here, the counter 3 is reset to the initial value by the reset signal 9 which is the output of the OR gate 18. The prescaler 1 is reset by the reset signal 9 if necessary. The MPX2 outputs the low speed clock signal 11 when the Q output of the flip-flop 21 is logic 1.
One of them is selected, and when the Q output is a logic O, the basic clock signal 12 is selected. The means for selecting a desired frequency division value from the plurality of low speed clock signals 11 is provided via the internal bus 16 although not shown.
The basic clock signal is a clock signal built in the computer. The counter 3 is an 8-stage connection of a binary binary counter. In the conveyor registers 4 and 5, the set values are divided and stored in advance via the internal bus 16 as described later. First, the conveyor register 4 is selected by the selector 6, and then the conveyor register 5 is selected. That is, the Q of the flip-flop 21
The selector 6 is controlled so that the register 4 is selected when the output is logic 1 and the register 5 is selected when the output is logic 0. The D-type flip-flop 21 is initially reset to have a Q output at logic 1 and an inverted output at logic 0. The output terminal 14 is necessary to output the time when the number of pulses reaches a desired set value to the outside and use it for an interrupt or the like.

Flip-flop 21 activates AND gates 15 and 19 so that reset signal 9 is supplied first from delay circuit 10 and then from delay circuit 20.

Although the basic clock signal of the computer is used as the original input signal in this embodiment, the signal under measurement is not limited to this.

As an alternative means, the prescaler 1 and the MPX 2 are used in this embodiment, but the present invention is not limited to this. In short, an input signal can be directly or arbitrarily divided to form a clock signal. What has a function may be used.

A binary 8-bit counter is used as the measuring means. This is the number of bits corresponding to the conventional circuit of FIG. 3, and the number of bits is about half as described later. In addition to this, a binary coded decimal binary counter may be used, and in this case, there is an advantage that it is possible to directly connect by visual recognition.

As the detecting means, a counter 3 and a common bit comparator are used. It may have any function as long as it has a function of outputting a match signal of logic 1 when all the logic values of each bit match.

In this embodiment, the counter 3, the comparator, and the registers 4 and 5 have an 8-bit structure.
The number of suitable bits is increased or decreased according to the number of pulses to be counted.

Next, the counting capacity according to this embodiment will be described in detail with a specific example, and then will be described as a general theory.

In order to secure a predetermined interval, for example, when the 23rd pulse number is detected, if the first 20 pulses are divided by 4 by the prescaler 1, "5" is stored in the low speed conveyor register 4. Just set it (4 x 5 = 20). Next, for the remaining three, the basic clock signal 12 may be counted as it is, so that “3” may be set in the high-speed conveyor register 5.

Therefore, in this case, the low speed conveyor register 4 has a 3-bit structure, the high speed conveyor register 5 has a 2-bit structure, and the counter 3 and the comparator 7 have a 3-bit structure.

However, in the prior art, the circuit that simply divides the 23rd clock cannot detect it, and the basic clock signal 12
Only will count. Since 2 ⁵ >23> 2 ⁴ , 5 bits are required. That is, all the registers, counters, and comparators need a 5-bit configuration.

As described above, this specific example has the effect that the 5-bit configuration may be a 3-bit configuration, so that not only the configuration is simple, but also high-speed processing of data is possible. In addition, if you configure the count by only dividing by 4,
The remaining three pulses are not counted and the resolution is reduced.

Generally, the numerical value indicating the set value of the pulse number is
It is represented by the sum of the first numerical part having a factor and the second numerical part consisting of a prime number. Here, the first numerical part is 0 when it has only a prime number without a factor. Also, when there is no prime number to be added, the second numerical part is 0.

When the first numerical value portion is present, the factor is counted as the frequency dividing number, so that the number of pulses input to the counter is 1 / the frequency dividing number, that is, the value divided by the factor. . Therefore, the number of bits is small.

The operation will now be described with reference also to FIG. 2 which shows the timing diagram of the embodiment of FIG. In the example of FIG.
A case is shown in which the 13th pulse is counted to secure an interval between them.

The basic clock signal 12 is divided by 2 to become a low speed clock signal 11, which becomes a counter clock signal 13 which is input to the counter 3 and counted. The divide-by-two value is set to MP via the internal bus 16.
The control signal on X2, the Q output of the flip-flop, indicates a logic one. First, the register 4 is selected, and "5" is temporarily stored here.

First, when the counter 3 counts the clock signal 13 as "5", the comparator 7 outputs the coincidence signal 8
Is output. Based on the coincidence signal 8, the signal delayed by the delay circuit 10 is used as a reset signal 9 to reset the counter 3 and the prescaler 1 and set to an initial value. Therefore, the coincidence signal 8 goes down from logic 1 to 0, but the signal at this time inverts the Q output of the flip-flop 21 from logic 1 to 0. Therefore, the delay circuit 10 is
The D gate 19 does not operate, the delay circuit 20 is activated by the AND gate 15, the MPX2 selects the basic clock signal 12, and the selector 6 selects the high speed conveyor register 5. The counter 3 continues counting until the value "3" set in the register 5 is reached. When the count value reaches "3", the coincidence signal 8 is generated, the pulse delayed by the delay circuit 20 is used as the reset signal 9, and the reset signal 9
Resets the counter 3 and prescaler 1 to their initial values. At this time, the coincidence signal 8 immediately disagrees,
A logic 1 to 0 level down causes this signal to cause flip-flop 21 to invert again and return to its original state.

Here, an output appears at the output terminal 14 every time the 13th pulse arrives. The 14th pulse has been reset to become the 1st pulse.

As described above, according to this embodiment, the D-type flip-flop 21 is used to alternately switch between the registers 4 and 5, and the MPX2 is also switched from the low speed clock to the basic clock signal 12 when switching. Counter 3,
The prescaler 1 is reset to the initial state.

In this embodiment, only one low speed conveyor register 4 is used, but two or more low speed conveyor registers 4 may be used, and in this case, a switching function of three stages or more is required. It is preferable to prepare a sufficient number of binary binaries so that the frequency division number of the prescaler 1 can be appropriately selected as needed.

As described above, since the bit configuration can be reduced to about half, the operation can be performed at a higher speed than the conventional one, and the delay of the addition processing based on the other bit configuration can be reduced.

[0043]

As described above, according to the present invention, since the basic clock signal is divided and counted, a large number of pulses can be counted with a small number of bits, and a high-speed clock count can be performed in a portion where resolution is desired. By switching to
It is possible to simultaneously realize a wide measurement range and high resolution with a single counter, which was not possible in the prior art, and as a result, the same resolution and measurement range as in the above-mentioned first prior art can be obtained. When designed, there is an effect that the bit configuration of a circuit such as a counter or a computer that occupies most of the circuit can be reduced to about half, and each of the above problems has been achieved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a counter device according to an embodiment of the present invention.

FIG. 2 is a timing chart showing an operation of one embodiment.

FIG. 3 is a block diagram showing a first prior art counter device.

FIG. 4 is a block diagram showing a second conventional technique.

[Explanation of symbols]

 1,31,106 Prescaler 2 Multiplexer (MPX) 3,33 Counter 4,5,32 Conveyor register 6,108 Selector 7,34 Comparator 8,40 Match signal 9 Reset signal 10,20 Delay circuit 11 Low-speed clock signal 12, 30 basic clock signal 13 counter clock signal 14,38 output terminal 15,19 AND gate 16,35 internal bus 17,39 input terminal 18 OR gate 21 D-type flip-flop 36 clear signal 37 clear signal generating circuit 100 counter

Claims (4)

[Claims] 1. An alternative means for outputting a repeated pulse of an original input signal as a clock signal directly or after dividing by a predetermined value, a measuring means for sequentially counting the number of pulses of the clock signal, A detecting means for outputting a coincidence signal when the number of pulses counted by the counting means reaches a preset setting, wherein the numerical value indicating the set value is composed of a first numerical part having a factor and a second prime number. In the case where the first numerical value part consists of the addition value with the numerical value part of, the first numerical value part is divided into the predetermined value by the alternative means, and the first numerical value part is divided by the factor. Counting is performed by the measuring means until the number of pulses coincides with the set value, and the second numerical value portion makes the original input signal directly the clock signal by the alternative means. Measure until it matches A counter device characterized by performing counting by means. 2. The counter device according to claim 1, wherein the first and second numerical parts are respectively stored in different conveyor registers. 3. The counter device according to claim 1, wherein the coincidence signal is used as a reset signal source for the selecting means and the measuring means. 4. The counter device according to claim 1, wherein the predetermined value in the selecting means and the set value in the detecting means are input via an internal bus of a computer.