JPH0942897A - Electronic type delay detonator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electronic type delay detonator having a high anti-shock characteristic against an explosion in which a plurality of explosives are loaded in an item to be broken and an explosion delay tinme is controlled in a high accurate manner during an explosion work for exploding these explosives in sequence. SOLUTION: There are provided an energy accumulation circuit 5 for accumulating electrical energy supplied from a blasting device, a first oscillator circuit 11 with a crystal oscillator element operated by the electrical energy accumulated in the energy accumulating circuit being applied as a reference value, a second oscillator circuit 13 having an anti-shock characteristic, and a time counting period making circuit 14 for use in making a time counting period by the second oscillator circuit in such a way that the time counting period may coincide with a reference period made by the first oscillator circuit. This electronic type delay detonator is also comprised of trigger signal generating circuits 31, 32 for outputting a trigger signal in reference to the time counting period under an operation of the second oscillator circuit and of an electrical discharging circuit 8 for discharging electrical energy responding against the trigger signal and accumulated in the energy accumulating circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic delay detonator for controlling a detonation delay time with high accuracy in a blasting operation in which a plurality of explosives are charged to a destruction target and the detonations are sequentially initiated.

[0002]

2. Description of the Related Art An electric signal supplied from a blaster is received,
An electronic delay detonator that stores the electric energy in an energy storage circuit, operates by the stored energy, and switches after a desired delay time is disclosed in Japanese Patent Laid-Open No. 5-79.
In Japanese Patent Publication No. 797, etc., the one having extremely high accuracy of initiation time is proposed.

According to the technical configuration proposed in Japanese Unexamined Patent Publication (Kokai) No. 5-79797, in a crystal oscillator-based oscillation circuit, a clocked inverter is used to cause a large current to flow only at the beginning of oscillation. It is said that the oscillation stabilization time of the oscillation circuit can be made extremely short and the accuracy can be maintained even if the time until the start of normal oscillation is reset and held by the analog timer.

In Japanese Patent Laid-Open No. 54-111744, a timing control pulse is transmitted from a position distant from the ignition element, two of the control pulses are used as a delay control signal, and the first control signal is received. Until the reception of the second control signal, the number of pulses of the oscillation circuit built in the ignition element is counted. After that, an electric timing device has been proposed which generates an ignition signal when the number between the first control signal and the second control signal is counted again by internal control.

Further, in Japanese Patent Laid-Open No. 3-251700, a calibration pulse is transmitted, and an error signal is generated due to the relationship between the calibration pulse and the pulse count generated by a built-in variable frequency oscillation circuit. A method of calibrating the frequency of the oscillation pulse of the variable frequency oscillation circuit based on the error signal has been proposed.

According to the technical configurations proposed in the above-mentioned Japanese Patent Laid-Open No. 54-111744 and Japanese Patent Laid-Open No. 3-251700, it is possible to use an oscillation circuit having a high frequency accuracy such as a crystal oscillation circuit. It is said that high time accuracy can be obtained by increasing the accuracy of the constituent pulses.

[0007]

Problems to be Solved by the Invention
In the technique of the publication, in order to obtain a highly accurate delay time, a crystal oscillator must be used as a means for obtaining a reference period.

However, the crystal oscillator is generally poor in mechanical strength, and there is a concern that it cannot withstand the explosive impact of the adjacent explosive.

According to the techniques proposed in Japanese Patent Laid-Open No. 54-111744 and Japanese Patent Laid-Open No. 3-251700, even if an analog type oscillation circuit is used without using a crystal oscillator, transmission is performed from a blaster. It is disclosed that by increasing the accuracy of the reference pulse, it is possible to delay the detonation time with high accuracy. In this case, while maintaining high accuracy, the resistance to the explosion of the adjacent explosive is improved. be able to.

However, it is not always easy to transmit a highly accurate pulse from the blasting device. That is,
When performing electrical blasting in an actual blasting site, unexpected electrical noise and changes in the load resistance of the blasting circuit must be considered. In other words, when performing electric blasting, the controller, that is, the blaster and the electronic delay electric detonator are connected through the blasting bus and the auxiliary bus, but noise may occur due to contact resistance during the connection process. It is expected that the resistance value of the blast circuit will change as the lengths of the blast bus and the auxiliary bus are changed for each blast operation.

[0011]

In order to solve the above problems, an energy storage circuit for storing electric energy supplied from a blaster and a crystal operated by the electric energy stored in the energy storage circuit. A first oscillating circuit with a vibrator as a reference, a second oscillating circuit having impact resistance characteristics, and a second oscillating circuit so that the clock cycle matches a reference cycle created by the first oscillating circuit. A clock cycle generation circuit for generating a clock cycle by an oscillation circuit, a trigger signal generation circuit for outputting a trigger signal based on the clock cycle by the second oscillation circuit, and the energy storage circuit in response to the trigger signal. And an electric discharge circuit for discharging electric energy stored in the electric detonator.

The trigger signal generating circuit generates a pulse signal with the time period as a reference, and a main counting circuit which outputs a trigger signal when the reference pulse is counted a preset number of times. May be composed of

When the clock cycle generation circuit counts the output pulses of the first oscillation circuit by a preset number,
A circuit that generates a time period generation start signal and a time period generation end signal, and when receiving the time period generation start signal, starts counting the second oscillation circuit output pulse and receives the time period generation end signal. And a time period count value data circuit that ends counting of the second oscillation circuit output pulse and fixes the count as the time period count value.

A circuit for generating a time period generation stop signal when the time period generation circuit counts a preset number of output pulses of the first oscillation circuit, and a second circuit for receiving the stop signal. When the trigger signal generation circuit counts a predetermined number of output pulses of the first oscillation circuit, the count signal includes a time period count value data circuit that stops counting the output pulse of the oscillation circuit and fixes the time period count value. A circuit for generating a clocking start signal, and a trigger signal output circuit for starting counting of output pulses of the second oscillation circuit when receiving the start signal and generating a trigger signal when the count value of the clocking period is reached. Good.

Alternatively, a circuit for generating a time period generation stop signal when the time period generation circuit counts a preset number of output pulses of the first oscillating circuit, and a second circuit for receiving the stop signal An up / down counter that stops counting the output pulses of the oscillation circuit and holds the count value at that time, and when the trigger signal generation circuit counts a predetermined number of output pulses of the first oscillation circuit, a clock start signal And the up / down counter, which starts counting in the reverse direction of the output pulse of the second oscillating circuit when the start signal is received and reaches the count value corresponding to the held count value. It may be composed of an up / down counter that generates a trigger signal.

According to the present invention, the reference time is created with reference to the highly accurate oscillation frequency of the crystal oscillator circuit, and thereafter the reference time is used to measure the time with reference to the second oscillator circuit having high impact resistance. .

Therefore, it is not necessary to receive an explosion shock while the crystal oscillation circuit is operating.

Further, the accuracy of the reference time depends on the accuracy of the crystal oscillator circuit, and hardly depends on the accuracy of the oscillation frequency of the second oscillator circuit.

Therefore, it is possible to achieve the same accuracy of initiation time as the electronic delay detonator using only the oscillation circuit based on the crystal oscillator.

[0020]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a timing chart showing the operation timing of FIG.

In FIG. 1, a rectifier circuit 4 is connected to input terminals 1-A and B for receiving electric energy supplied from a blasting machine (not shown) so as to match the input polarities with the internal circuit. An energy capacitor 5 is connected by the rectifier circuit 4 so that the input from both directions can be charged,
A bypass resistor 3 is connected in parallel with the capacitor 5 and to the input side of the rectifier circuit 4. The input terminal of the constant voltage circuit 6 is connected in parallel to the capacitor 5 and is configured to output a constant voltage. The crystal oscillation circuit 11 outputs the oscillation pulse SD to the first counter 21 and the second counter 22.

The first counter 21 is released from reset by the reset circuit 7, counts a predetermined number (m) of crystal oscillation pulses SD, and then outputs the signal S1 to the clock period count value data circuit 14. The second counter 22 is released from reset by the reset circuit 7, counts the crystal oscillation pulse SD by the number (n) set by the count setting switch 23, and then outputs the signal S2 to the clock period count value data circuit 14
Output to Number set in the second counter 22 (n)
Is larger than the number (m) counted by the first counter (n> m).

The second oscillating circuit 13 outputs the oscillating pulse SH to the clock period count value data circuit 14 and the reference pulse output circuit 31. The time count value data circuit 14 is
Reset is released by the signal S1, the oscillation pulse SH of the second oscillation circuit 13 is counted, the counting is stopped by the signal S2, and the count data (ΔT) is held.

The reference pulse output circuits 31 are reset by the signal S2, and the second oscillation circuits 13 are reset by the number corresponding to the count data (ΔT) of the count value count value data circuit 14.
The output pulse SH of is counted, the reference time clock signal SI is output to the main counting circuit 32, and it is reset by the signal SI. The count data (ΔT) is the predetermined number (m) counted by the first counter 21 and the second counter 2
It is the time determined by the difference from the number (n) set by the count setting switch counted by 2.

[0026]

## EQU00001 ## .DELTA.T = (n-m) t (t: period of the crystal oscillation circuit 11) The main counting circuit 32 is released from reset by the signal S2,
The output signal SI of the reference pulse output circuit 31 is counted by the number (N) set by the count setting switch 33,
The trigger signal SJ is output to the electronic switch 8. When the electronic switch 8 receives the trigger signal SJ, it closes to form a discharge circuit and discharges the electric energy of the capacitor 5.

Now referring to the timing diagram of FIG.
The operation of the circuit shown in FIG.

When the output SA from the blaster (not shown) is input to the input terminals 1-A and B, the energy capacitor 5 is charged as shown at SB. With this charging power,
The circuit shown in FIG. 1 operates. Therefore, the crystal oscillator circuit 1
1 is a constant voltage circuit 6 after charging the energy capacitor 5
Oscillation is started after the output voltage is output from (SD).

Further, the reset circuit 7 has a reset release signal S after a predetermined time has passed since the output from the constant voltage circuit 6.
Output R. The reset release signal is input to the first counter 21 and the second counter 22. The predetermined time when the reset release signal is output is the time until the crystal oscillation circuit 11 stably outputs the output pulse SD. By the reset release signal SR, the first counter 21 and the second counter 21
The counter 22 outputs the output pulse SD from the crystal oscillation circuit 11.
Start counting.

When the first counter 21 counts a predetermined number (m) of oscillation pulses from the crystal oscillation circuit 11,
The output signal S1 is output. As a result, the clock cycle count value data circuit 14 starts counting the output pulses SH of the second oscillation circuit 13. Then, from the second counter 22,
When the number (n) set in the setting switch 23 is counted, the output signal S2 is output and the counting is stopped. The time between these times becomes the reference time (ΔT).

The output signal S2 from the second counter is also input to the reference pulse output circuit 31 and the main counting circuit 32 to start the counting operation in these circuits. An output pulse SI is output from the reference pulse output circuit 31 every ΔT, and this pulse is counted by the main counting circuit 32. When the output pulse SI is counted up to the number N set in the setting switch 33, the detonation trigger signal is output. Then, the electronic switch 8 is triggered to form a discharge circuit, and the electric energy of the capacitor 5 is discharged.

Accordingly, when the delay time T from the input of the blaster output to the output of the trigger signal is tr from the input of the blaster output to the output of the reset signal,

[0033]

## EQU2 ## T = tr + n * t + ΔT * N. As can be seen from this, the delay time T is determined by the setting of the second counter 22 and the setting of the main counting circuit 32.

Further, since the pulses of the second oscillating circuit are counted at the time of detonation, it is structurally strong against explosion. The delay between the detonators connected to the same blaster can be set for each ΔT by the number set by the setting switch 33 of the main counting circuit 32. Since this set time is corrected by the crystal oscillation circuit, even if the second oscillation circuit is used, it has the same accuracy as in the case where the crystal oscillation circuit is used.

(Embodiment 2) FIG. 3 is a block diagram showing an embodiment of the present invention, and FIG. 4 is a timing chart showing the operation timing of FIG.

In FIG. 3, input terminals 1-A, B for receiving electric energy supplied from a blasting device (not shown).
Further, the rectifier circuit 4 is connected so as to match the input polarity with the internal circuit. An energy capacitor 5 is connected by a rectifier circuit 4 so that an input from both directions can be charged, and a bypass resistor 3 is connected in parallel with the capacitor 5 and on the input side of the rectifier circuit 4. The input terminals of the constant voltage circuit 6 are connected and configured to output a constant voltage.

The crystal oscillation circuit 11 outputs the oscillation pulse SD to the first counter 21 and the second counter 22.

The first counter 21 is released from reset by the reset circuit 7, counts the crystal oscillation pulse SD by the number (m) set by the count setting switch 23, and then outputs the signal S1 to the clock period count value data circuit 14. Output.

The second counter 22 is released from reset by the reset circuit 7, counts a predetermined number (n) of crystal oscillation pulses SD, and then outputs the signal S2 to the trigger signal output circuit 34. The count value (n) of the second counter 22 is
It is desirable to set the value equal to or more than the maximum count value that can be set by the count setting switch 23.

The second oscillating circuit 13 outputs the oscillating pulse SH to the clock period count value data circuit 14 and the trigger signal output circuit 34.

The counting period count value data circuit 14 is reset by the reset circuit 7, counts the oscillation pulse SH of the second oscillating circuit 13, stops counting by the signal S1, and holds the count data (ΔT). (ΔT = m * t
t: cycle of the crystal oscillator circuit 11).

The trigger signal output circuit 34 is released from reset by the signal S2, counts the output pulse SH of the second oscillation circuit 13 by the number corresponding to the count data (ΔT) of the time count count value data circuit 14, and outputs the electronic pulse. The trigger signal SJ is output to the switch 8. When the electronic switch 8 receives the trigger signal SJ, it closes to form a discharge circuit, and the capacitor 5
To discharge the electrical energy of.

Now referring to the timing diagram of FIG. 4, FIG.
The operation of the circuit shown in FIG.

When the output SA from the blaster (not shown) is input to the input terminals 1-A and B, the energy capacitor 5 is charged as shown at SB. With this charging power,
The circuit shown in FIG. 3 operates. Therefore, the crystal oscillator circuit 1
1 is a constant voltage circuit 6 after charging the energy capacitor 5
Oscillation is started after the output voltage is output from (SD).

Further, the reset circuit 7 outputs the reset release signal S after a predetermined time from the output from the constant voltage circuit 6.
Output R. The reset release signal is input to the first counter 21 and the second counter 22. The predetermined time when the reset release signal is output is the time until the crystal oscillation circuit 11 stably outputs the output pulse SD. By the reset release signal SR, the first counter 21 and the second counter 21
The counter 22 outputs the output pulse SD from the crystal oscillation circuit 11.
Start counting. The reset release signal SR from the reset circuit 7 is also input to the time counting period count value data circuit 14, and the time counting period count value data circuit 14 starts counting the oscillation pulses from the second oscillation circuit 13.

When the first counter 21 counts the number (n) of oscillation pulses set by the setting switch 23 from the crystal oscillation circuit 11, it outputs the output signal S1. As a result, the clock period count value data circuit 14 stops counting the output pulse SH of the second oscillation circuit 13. As a result, the count value data ΔT
Is set and held.

When the second counter 22 counts a predetermined number (n) of oscillation pulses from the crystal oscillation circuit 11, the output signal S2 is output and the trigger signal output circuit 34 starts counting by the second oscillation circuit 13. Then, when the trigger signal output circuit 34 counts up to ΔT set in the time period count value data circuit 14, the trigger signal is output. Then, the electronic switch 8 is triggered to form a discharge circuit, and the electric energy of the capacitor 5 is discharged.

As a result, the delay time T from the input of the blaster output to the output of the trigger signal is tr when the time from the input of the blaster output to the output of the reset signal is tr.

[0049]

## EQU3 ## T = tr + n * t + ΔT = tr + n * t + m *
t = tr + (n + m) * t. As can be seen from this, the delay time T is determined by the setting (m) of the first counter 21 and the predetermined value (m) of the second counter 22.

Further, since the pulses of the second oscillating circuit are counted at the time of detonation, it is structurally strong against the explosion. The delay between the detonators connected to the same blaster can be set by the number set by the setting switch 23 of the first counter 21. Since this set time is corrected by the crystal oscillation circuit, even if the second oscillation circuit is used, it has the same accuracy as in the case where the crystal oscillation circuit is used.

(Embodiment 3) FIG. 5 is a block diagram showing an embodiment of the present invention, and FIG. 6 is a timing chart showing the operation timing of FIG.

In FIG. 5, a rectifier circuit 4 is connected to the input terminals 1-A and 1-B for receiving the electric energy supplied from the blaster so as to match the input polarities with the internal circuit.
An energy capacitor 5 is connected by a rectifier circuit 4 so that an input from both directions can be charged, and a bypass resistor 3 is connected in parallel with the capacitor 5 and on the input side of the rectifier circuit 4. The input terminal of the constant voltage circuit 6 is connected in parallel to the capacitor 5 and is configured to output a constant voltage.

The crystal oscillation circuit 11 outputs the oscillation pulse SD to the first counter 21 and the second counter 22. The first counter 21 is reset by the reset circuit 7 and counts the crystal oscillation pulse SD by the number (m) set by the count setting switch 23, and then outputs the signal S1 to the up / down counter 35. Second counter 2
The reset signal 2 is reset by the reset circuit 7, counts a predetermined number (n) of crystal oscillation pulses SD, and then outputs the signal S2 to the up / down counter 15.

The count value of the second counter 22 is preferably set equal to or more than the maximum count value which can be set by the count setting switch 23.

The second oscillation circuit 13 outputs the oscillation pulse SH to the up / down counter 35.

The up / down counter 35 is reset by the reset circuit 7 and counts the oscillation pulse SH of the second oscillation circuit 13 in the forward direction (up). And
Counting is stopped by the output signal S1 from the first counter 21. Then, the forward count value (ΔT) at that time is held. When the output signal S2 from the second counter 22 is received, the output pulses SH of the second oscillation circuit 13 are counted in the reverse direction (down) by the number corresponding to the forward count value (ΔT). When the count value of the up / down counter 35 becomes “0”, the trigger signal SJ is output to the electronic switch 8.

The electronic switch 8 closes when it receives the trigger signal SJ, forms a discharge circuit, and discharges the electric energy of the capacitor 5.

The third embodiment has a configuration in which the time period count value data circuit 14 and the trigger signal output circuit 34 of the second embodiment are replaced with an up / down counter 35. Therefore, the operation is similar to the operation timing of the second embodiment shown in FIG. 4, as can be seen from the operation timing of FIG.

Therefore, the delay time T is the same as in the second embodiment.

[0060]

(4) T = tr + n * t + ΔT = tr + n * t + m *
t = tr + (n + m) * t.

Further, as in the second embodiment, since the pulses of the second oscillating circuit are counted when detonating, the structure is structurally strong against explosion. Then, the delay between the detonators connected to the same blaster can be determined by the number set by the setting switch 23 of the first counter 21. Since this set time is corrected by the crystal oscillation circuit, even if the second oscillation circuit is used, the same accuracy as when the crystal oscillation circuit is used can be obtained.

In the first to third embodiments, a CR oscillating circuit as a second oscillating circuit, an oscillating circuit using a ceramic oscillator as a reference, an oscillating circuit utilizing a resonance phenomenon, such as an LC oscillating circuit, a crystal, etc. Any structure can be used as long as it has a structure that is more resistant to the impact of explosion than the oscillation circuit.

[0063]

According to the present invention, it is possible to provide an electronic delay detonator having a high impact resistance without degrading the accuracy by only applying electric energy.

As a result, it is possible to carry out the blasting work of the electronic delay detonator that is practical and highly safe, and it is possible to carry out the blasting with a precise firing time control.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a timing chart of the first embodiment of the present invention.

FIG. 3 is a block diagram of a second embodiment of the present invention.

FIG. 4 is a timing diagram of the second embodiment of the present invention.

FIG. 5 is a block diagram of a third embodiment of the present invention.

FIG. 6 is a timing diagram of the third embodiment of the present invention.

Claims (5)

[Claims] 1. An energy storage circuit for storing electric energy supplied from a blasting device, a first oscillating circuit based on a crystal oscillator which operates by the electric energy stored in the energy storage circuit, and a shock resistance. A second oscillating circuit having characteristics, and a time period creating circuit for creating a time period by the second oscillating circuit so that the time period matches a reference period created by the first oscillating circuit, The second oscillation circuit includes a trigger signal generation circuit that outputs a trigger signal based on the time period, and a discharge circuit that responds to the trigger signal and discharges the electric energy stored in the energy storage circuit. An electronic delay detonator characterized by that. 2. A reference pulse output circuit in which the trigger signal generating circuit generates a pulse signal based on the time period, and a main controller which outputs a trigger signal when the reference pulse is counted a preset number of times. The electronic delay detonator according to claim 1, characterized in that it comprises several circuits. 3. A circuit for generating a time period generation start signal and a time period generation end signal when the time period generation circuit counts a preset number of output pulses of the first oscillation circuit, When receiving the time period generation start signal, the counting of the second oscillation circuit output pulse is started, and when receiving the time period generation end signal, the counting of the second oscillation circuit output pulse is ended,
The electronic delay detonator according to claim 2, further comprising: a time period count value data circuit that fixes the time period count value. 4. A circuit that generates a time period generation stop signal when the time period generation circuit counts a preset number of output pulses of the first oscillator circuit, and a second circuit that receives the stop signal. Of the output pulse of the oscillation circuit of (1), and a count period count value data circuit for fixing the count value of the count period, the trigger signal generating circuit counted a predetermined number of output pulses of the first oscillation circuit. And a trigger signal output circuit which, when receiving the start signal, starts counting the output pulses of the second oscillation circuit and generates a trigger signal when the count value of the time period is reached. The electronic delay detonator according to claim 1, wherein: 5. A circuit that generates a time period generation stop signal when the time period generation circuit counts a preset number of output pulses of the first oscillator circuit, and a second circuit when the time signal is received. When the trigger signal generation circuit counts a predetermined number of output pulses of the first oscillation circuit, the up-down counter stops counting the output pulses of the oscillation circuit and holds the count value at that time. A circuit for generating a clocking start signal and the up / down counter, which starts counting in the reverse direction of the output pulse of the second oscillation circuit when the start signal is received, and outputs a count value corresponding to the held count value. An electronic delay detonator according to claim 1, characterized in that it comprises an up-down counter which generates a trigger signal when a numerical value is reached.