JPH0936925A - Demodulation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To properly demodulate data even from an MSK signal having waveform distortion or noise. SOLUTION: A circuit 13 for sampling a signal SMSK to be modulated and a latch circuit 31, to which the sampling result is supplied, are provided. A discrimination circuit 32 is provided for discriminating whether or not the level of a sampling value during a specified period among the sampling values latched by the latch circuit 31 is the level of a sampling value during an important period among the sampling values of the signal SMSK modulated by the data of '0'. A deccission circuit 33 is provided for discriminating whether or not the level of the sampling value during the specified period among the sampling values latched by the latch circuit 31 is the level of a sampling value during an important period among the sampling values of the signal SMSK modulated by the data of '1'. From the respective discriminated results of the discrimination circuits 32 and 33, the demodulated output of the signal SMSK is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a demodulation circuit for a signal modulated by digital data.

[0002]

2. Description of the Related Art In cordless telephones, for example, when a slave unit requests a connection between the two units to make a call, a request is made from the master unit to the slave unit for a connection between them. In the case, a command signal indicating the request, parameter, etc. is transmitted and received between the parent device and the child device.

FIG. 8 shows one form of the signal format of the command signal CMND. This signal CMND has a 16-bit bit synchronization signal BSYN at the beginning, and subsequently has a 16-bit frame synchronization signal FSYN. In this case, the bit synchronization signal BSYN has a bit pattern in which “0” and “1” are alternately repeated, and the frame synchronization signal FSYN has a predetermined bit pattern, but is transmitted from the child device to the parent device. The bit pattern is different between the frame synchronization signal FSYN that is transmitted from the master unit and the frame synchronization signal FSYN that is transmitted from the master unit to the slave unit.

Further, the command signal CMND has a 25-bit system identification code SYID following the signal FSYN, a 12-bit error correction code ECC for this code SYID, and a 5-byte control code CTRL. In this case, the system identification code SYID is data for distinguishing the own device from other devices. The first byte of the control code CTRL is a code indicating the control content of the slave unit and the master unit, and the second to fifth bytes are parameters or data related to the first byte.

When the child device or the parent device receives this command signal CMND, the command signal CMND
It is checked whether the identification code SYID included in the identification code SYID matches the identification code SYID stored in its own machine. Only when they match, the command signal CMND is validated, and when they do not match, the command signal CMND is invalidated.

When this command signal CMND is transmitted and received between the master unit and the slave unit, the MSK of the audio band
It is converted into a signal (modified MSK signal), and the MSK signal is FM-modulated with the main carrier signal and transmitted. Therefore, as shown in FIG. 9, when the bit of the original command signal CMND is “0”, the MSK signal has one cycle that rises in the positive direction at the period τ (A in the figure) or in the negative direction. 1 cycle (B in the figure) when it is "1", the cycle is 2τ and a positive half cycle (C in the figure)
Alternatively, the cycle becomes a negative half cycle (D in the same figure).

The frequency of the MSK signal (= 1 / τ)
Is, for example, 2.4 kHz when the bit is "0" and 1.2 kHz when the bit is "1".

Then, in this way, the original bit "0"
Two MSK signal waveforms are prepared for each of "1" and "1", and as shown in FIG. 10, when two bits are continuous, the waveform of the MSK signal is continuous (the polarity is inverted). 2), the waveform of the MSK signal is selected.

Therefore, the command signal CMND is transmitted / received at a fixed bit rate. Further, there are eight combinations of waveforms of the MSK signal for two consecutive bits of the command signal CMND.

[0010]

By the way, the above-mentioned MS
When demodulating the command signal CMND from the K signal, for example, the processing shown in FIG. 11 may be performed. That is, FIG. 11A shows an MSK signal when the original command signal CMND is “0101”, and this MSK signal is shaped to obtain a rectangular wave signal as shown in FIG. 11B.

Then, for each bit period τ, the time τ1 when the rectangular wave signal is "1" and the time τ0 when the rectangular wave signal is "0".
Is measured, and the bit of the original command signal CMND is “1” or “0” from the ratio of the time τ1 and the time τ0.
It is sufficient to judge whether or not

However, in an actual cordless telephone, the waveform of the received MSK signal may be distorted due to noise or the like. As a result, when the received MSK signal is shaped into a rectangular wave signal, the waveform is changed. For example, in FIG.
As shown in C or D, the times τ1 and τ0 may not be the original values.

However, the demodulation circuit must be able to correctly demodulate the bits of the original command signal CMND even if the times τ1 and τ0 change in this way.

The present invention seeks to satisfy the demand with a simple structure.

[0015]

Therefore, according to the present invention, a modulated signal that is modulated so that the frequency changes depending on whether the original data is "0" or "1" is used. A demodulation circuit for demodulating the data, the circuit for sampling the modulated signal, the latch circuit to which the sampling result is supplied, and the sampling value latched by the latch circuit for sampling in a specific period The first determination circuit for determining whether the value level is the level of the sampling value of the main period of the sampling values of the modulated signal modulated by the “0” data, and the latch circuit. Of the latched sampling values, the level of the sampling value of a specific period is the sampling value of the modulated signal modulated by the data of "1". A second judgment circuit for judging whether or not it is the level of the sampling value in the main period of time, and from the judgment results of the first judgment circuit and the second judgment circuit, The demodulation circuit is adapted to obtain a demodulation output.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In FIG. 1, reference numeral 10 is a clock recovery circuit, and reference numeral 30 is a demodulation circuit. Then, in the clock recovery circuit 10, the MSK signal SMSK transmitted from the master unit or the slave unit of the cordless telephone is supplied to the limiter amplifier 11 through the terminal T11.
As shown in A and B, it is shaped into a rectangular wave signal SB, this signal SB is supplied to the edge detection circuit 12, and as shown in FIG. 2C, a pulse PC for each edge of the signal SB is extracted, and this pulse PC Are supplied to the AND circuit 17.

Further, the signal SB from the limiter amplifier 11
Is supplied to the 16-bit serial input / serial output and parallel output shift register 13 as its shift input.

Further, a crystal oscillating circuit 21 is provided, and an oscillating signal having a stable frequency is taken out from the oscillating circuit 21. At this time, the frequency of the oscillating signal is when the MSK signal SMSK is "0". Frequency (= 2.4k
Hz), for example, 6000 times, that is, 14.4 MHz.

This oscillating signal is supplied to the frequency dividing circuit 22 and, for example, a signal S1 of 192 kHz having a frequency of 1/75.
The frequency is divided by 92, and this signal S192 is supplied to the counter (synchronous frequency dividing circuit) 23.
The signal S384 has a frequency of / 5 and is divided into a signal S384 of 38.4 kHz, and the signal S384 has a frequency of 1/16.
It is divided into 2.4 kHz signal S24. Then, the signal S384 is supplied to the shift register 13 as a clock.

Therefore, the signal SB supplied to the shift register 13 is transferred to the register 23 at the timing of the signal S384.
Will be taken into.

In this case, the frequency of the signal S384 is 38.4 kHz.
Since this frequency is 16 times the frequency of the MSK signal SMSK when CMND = "0", the command signal CMND
The signal SB for 1 bit is decomposed into 16 samples, and each sample is serially taken into the register 13 for each signal S384.

Since the register 13 has a capacity of 16 bits, at a certain point in time, as shown in FIG.
Each sample of the signal SB for one bit period (= τ) of
It is located in each bit b0 to b15 of the register 13.

Also, the signal SB is thus registered 1
Since it is taken in by 3, from the final stage of the register 13,
As shown in FIG. 2D, the signal SD delayed by one bit period τ is output as the signal SD.

This signal SD is the edge detection circuit 1
4 and the pulse PE for each edge of the signal SD is extracted as shown in FIG. 2E, and this pulse PE is supplied to the AND circuit 17.

Further, from the eighth stage (8th bit) of the register 13, as shown in FIG.
The signal SF delayed by / 2 is taken out, and this signal SF is
While being supplied to the exclusive NOR circuit 15,
The signal SB is supplied to the exclusive NOR circuit 15,
As shown in FIG. 2G, a signal SG that becomes "1" is taken out from the exclusive NOR circuit 15 every half period of the latter half of the bit period τ where SMSK = "1".

Then, this signal SG is supplied to the delay circuit 16, and as shown in FIG. 2H, it is made a signal SH delayed by, for example, 3 stages of the register 13, that is, 3/16 · τ, and this signal SH Are supplied to the AND circuit 17 for gate control.

Therefore, from the AND circuit 17, FIG.
As shown by I, when the pulse PC and the pulse PE are simultaneously obtained in the period of SH = "1", the pulse PI is output. That is, at every end time t1, t2, t3, ... Of the bit period τ with SMSK = "1", the pulse PI
Is output.

This pulse PI is the AND circuit 1
8 is supplied as a reset signal to the counter 23, and the count (frequency division) of the counter 23 is reset every pulse PI.

Therefore, when the counter S23 counts (divides) the signal S192 to form the signals S384 and S24, the phase of the signal S24 when the counter 23 is not reset at all is as shown in FIG. 2J, for example. Even in the state, since the counter 23 is reset by the pulse PI at the time point t1, as shown in FIG. 2K,
The count of the counter 23 is restarted from the end time t1 of the bit period τ in which SMSK = "1" is initially set, and the start point of the phase of the signal S24 becomes the time t1.

Furthermore, since the pulse PI is obtained at the time t2, the signal S24 is surely corrected to the phase shown in FIG. 2K.

When the phase of the signal S24 is corrected twice by the pulse PI, at this time, the number of the pulses PI is detected by the detection circuit 19, and the detection output thereof causes the pulse PI obtained after the time t2. Is blocked in the AND circuit 18 and is not supplied to the counter 23.

Thus, as shown in FIGS. 2A and 2K, the counter 23 outputs a signal S24 synchronized with the MSK signal SMSK.
Is output. That is, the signal S24 is the MSK signal SMS.
It is a clock signal synchronized with K.

At this time, in the counter 23,
Since the signal S24 is a signal obtained by dividing the signal S384 by 1/16, the signal S384 is also synchronized with the MSK signal SMSK. Since this signal S384 is supplied to the shift register 13 as a clock, the subsequent processing is performed by the MS.
It will be performed in synchronization with the K signal SMSK.

A 16-bit latch circuit (buffer memory) 31 is connected in parallel to the register 13, and a clock signal S24 is supplied to the forming circuit 24 to form a predetermined latch pulse, and the latch pulse is latched. It is supplied to the circuit 31. In this way, the contents of the register 13 are transferred in parallel to the latch circuit 31 and latched at each end time point of the 1-bit period τ of the MSK signal SMSK.

In this case, 1 of the MSK signal SMSK
At the end of the bit period τ, the signal SB is taken into the shift register 13 as shown in FIG.
The distribution or arrangement of B 16 samples) is also as shown in FIG.

Then, the data transferred to the latch circuit 31 is sent to the judging circuit 32 by the MS of CMND = "0".
It is determined whether it is the K signal SMSK. That is,
For example, as shown in FIG. 4, bit b0 of the latch circuit 31
The non-inverted output and the inverted output are extracted from .about.b15.

Then, bits b2 to b6 of the latch circuit 31
The non-inverted output of the bit b12 and the inverted output of bits b13 are supplied to the AND circuit 41, and the bit b2 of the latch circuit 31
The non-inverted output of b3 and the inverted outputs of bits b9 to b13 are supplied to the AND circuit 42, and bit b3 of the latch circuit 31 is supplied.
.About.b5 non-inverted outputs and bits b10 to b12 inverted outputs are supplied to the AND circuit 43.

The non-inverted outputs of the bits b2 to b5 and the inverted outputs of the bits b10 to b13 of the latch circuit 31 are supplied to the AND circuit 44, and the bits b3 to b6 of the latch circuit 31 are supplied.
The non-inverted output and the inverted outputs of bits b9 to b12 are supplied to the AND circuit 45.

Further, bits b2 to b6 of the latch circuit 31
And the non-inverted outputs of bits b12 and b13 are supplied to the AND circuit 51, and bit b2 of the latch circuit 31
The inverted output of b3 and the non-inverted outputs of bits b9 to b13 are supplied to the AND circuit 52, and bit b3 of the latch circuit 31 is supplied.
The inverted output of .about.b5 and the non-inverted output of bits b10 to b12 are supplied to the AND circuit 53.

Further, the inverted outputs of the bits b2 to b5 and the non-inverted outputs of the bits b10 to b13 of the latch circuit 31 are supplied to the AND circuit 54, and the bits b3 to b6 of the latch circuit 31 are supplied.
And the non-inverted outputs of bits b9 to b12 are supplied to the AND circuit 55.

Therefore, the level of each bit b0 to b15 when the signal SB having the correct waveform is latched in the latch circuit 31 is different from that in the state of FIG. 5A (FIG. 7A shows that the modulating signal CMND is positive). (When the data is "0" rising in the direction), as shown by the solid line in FIG. 5B, if bits b2 to b6 are "1" and bits b12 and b13 are "0", regardless of other bits. , AND circuit 41 output is "1"
Becomes

As shown by the solid line in FIG. 5C, if the bits b2 and b3 are "1" and the bits b9 to b13 are "0", the output of the AND circuit 42 will be irrespective of other bits. It becomes "1". Then, similarly, in any of the states shown by the solid lines in FIGS.
The output of the corresponding AND circuit of ~ 45 becomes "1".

Furthermore, the level of each bit b0 to b15 when the signal SB having the correct waveform is latched in the latch circuit 31 is different from that in the state of FIG. 5G (in FIG. 5G, the modulating signal CMND is negative). (When the data is "0" falling in the direction), if the bits b2 to b6 are "0" and the bits b12 and b13 are "1" as shown by the solid line in FIG. No, the output of the AND circuit 51 is "1"
Becomes

Similarly, as shown by the solid line in FIG. 5I, the bits b2 and b3 are "0", and the bits b9 to b13.
Is "1", the output of the AND circuit 52 is "1" regardless of other bits. Similarly, in any of the states shown by solid lines in FIGS. 5J to 5L, the output of the corresponding AND circuit of the AND circuits 53 to 55 becomes “1”.

That is, if the waveform (level) of the signal latched in the latch circuit 31 is a waveform including any of the waveforms of FIGS. 5B to 5F and H to L, the AND circuits 41 to 45,
The output of the corresponding AND circuit of 51 to 55 is "1"
become. Therefore, at this time, the output S of the OR circuit 46
U becomes "1".

Thus, according to this determination circuit 32, M
Even if the SK signal SMSK is distorted or contains noise, if the waveform of the signal latched by the latch circuit 31 is a waveform including any of the waveforms of FIGS. 5B to 5F and 5 to L. , SU = “1”.

Further, the data transferred to the latch circuit 31 is transferred to the MS of CMND = "1" in the waveform judging circuit 33.
It is determined whether it is the K signal SMSK. That is,
For example, as shown in FIG. 6, bit b4 of the latch circuit 31
The non-inverted outputs of -b11 are supplied to the AND circuit 61, and the non-inverted outputs of the bits b2 to b6 and b9 to b13 are supplied to the AND circuit 62.
And the non-inverted outputs of the bits b5 to b10 are supplied to the AND circuit 63.

Further, bits b4 to b1 of the latch circuit 31
The inverted output of 1 is supplied to the AND circuit 71, and bits b2 ...
The inverted outputs of b6 and b9 to b13 are supplied to the AND circuit 72, and the inverted outputs of bits b5 to b10 are supplied to the AND circuit 73.

Therefore, the level of each bit b0 to b15 when the signal SB having the correct waveform is latched in the latch circuit 31 is higher than that in the state of FIG. 7A (in FIG. 7A, the modulating signal CMND is positive). (When the data is "1" which rises in the direction), as shown by the solid line in FIG. 7B, bits b4 to b11
Is "1", the output of the AND circuit 61 is "1" regardless of other bits.

As shown by the solid line in FIG. 7C, if the bits b2 to b6 and b9 to b13 are "1", the output of the AND circuit 62 becomes "1" regardless of the other bits. Further, as shown by the solid line in FIG. 7D, if the bits b5 to b10 are "1", the output of the AND circuit 63 becomes "1" regardless of other bits.

Further, the level of each bit b0 to b15 when the signal SB having the correct waveform is latched in the latch circuit 31 is higher than that in the state of FIG. 7E (in FIG. 7E, the modulating signal CMND is negative). When the data is "1" falling in the direction), as shown by the solid line in FIG. 7F, if the bits b4 to b11 are "0", the output of the AND circuit 71 is "1" regardless of other bits. Becomes

As shown by the solid line in FIG. 7G, if the bits b2 to b6 and b9 to b13 are "0", the output of the AND circuit 62 becomes "1" regardless of other bits. Further, as shown by the solid line in FIG. 7H, if the bits b5 to b10 are "0", the output of the AND circuit 63 becomes "1" regardless of other bits.

That is, if the waveform of the signal latched by the latch circuit 31 is a waveform including any of the waveforms of FIGS. 7B to D and F to H, the AND circuits 61 to 63, 71 to 73.
The output of the corresponding AND circuit becomes "1". Therefore, at this time, the output SV of the OR circuit 64 is "1".
become.

Thus, according to this judgment circuit 33, M
Even if the SK signal SMSK is distorted or contains noise, if the waveform of the signal latched by the latch circuit 31 is a waveform including any of the waveforms of FIGS. 7B to D and F to H. , SV = “1”.

Then, as shown in FIG.
Is supplied to the AND circuit 35 through the inverter circuit 34, and the signal SV from the determination circuit 33 is supplied to the AND circuit 35.

Therefore, when the original MSK signal SMSK is modulated by the data of "0", SU =
When "1" and SV = "0" and the original MSK signal SMSK is modulated by the data of "1", SU =
Since "0" and SV = "1", the output signal of the AND circuit 35 is the command signal CMN obtained by demodulating the MSK signal SMSK.
It becomes D, and this demodulated command signal CMND is at terminal T12.
Is taken out. Further, the clock signal S24 from the counter 23 is taken out to the terminal T13.

Thus, according to the above demodulation circuit, the MS
The original command signal CMND can be demodulated from the K signal SMSK.

In this case, for example, FIGS.
As shown in, the level of a specific period of the MSK signal SMSK, that is, the level of the period during which the level will not change even if waveform distortion occurs in the MSK signal SMSK, is checked and demodulated from the check result. Since the output is obtained, the command signal CMND can be correctly demodulated even if the duty ratio of the rectangular wave signal SB deviates from the normal value due to the waveform distortion of the MSK signal SMSK.

Moreover, as is clear from FIGS. 4 and 6, the demodulation circuit 30 does not require any special element or circuit. Further, also in the clock reproduction circuit 10, the PLL is not required to form the clock signal S24, the circuit scale can be reduced, and the configuration is simple.

Furthermore, if the MSK signal SMSK is up to about 200 bits, the frequency stability of the oscillation circuit 21 may be about 20 ppm, and therefore, an inexpensive crystal oscillator can be used, and its versatility is wide.

[0061]

According to the present invention, the original data can be demodulated from the MSK signal. And in that case,
Even if the MSK signal has a waveform distortion, the data can be correctly demodulated. Moreover, no special element or circuit is required for that purpose.

[Brief description of drawings]

FIG. 1 is a system diagram showing one embodiment of the present invention.

FIG. 2 is a waveform diagram for explaining the operation of the circuit of FIG.

FIG. 3 is a diagram for explaining the operation of the circuit of FIG.

FIG. 4 is a system diagram showing one form of a part of the circuit of FIG.

FIG. 5 is a diagram for explaining the operation of the circuit of FIG.

FIG. 6 is a system diagram showing one form of a part of the circuit of FIG.

FIG. 7 is a diagram for explaining the operation of the circuit in FIG. 6;

FIG. 8 is a diagram showing an example of a signal format.

FIG. 9 is a waveform diagram showing an example of a signal waveform.

FIG. 10 is a diagram showing a relationship between signal waveforms.

FIG. 11 is a diagram for explaining a signal waveform.

[Explanation of symbols]

 10 clock recovery circuit 11 limiter amplifier 12, 14 edge detection circuit 13 shift register 15 exclusive NOR circuit 16 delay circuit 19 detection circuit 21 oscillator circuit 22 frequency divider circuit 23 counter (synchronous frequency divider circuit) 24 formation circuit 30 demodulation circuit 31 Latch circuit 32, 33 Judgment circuit

Claims (3)

[Claims] 1. A demodulation circuit for demodulating the above-mentioned data from a modulated signal which is modulated so that the frequency changes depending on whether the original data is "0" or "1". A circuit for sampling the modulated signal, a latch circuit to which the sampling result is supplied, and a sampling value level of a specific period among the sampling values latched by the latch circuit is determined by the data of "0". A first judgment circuit for judging whether or not it is a level of a sampling value of a main period among the sampling values of the modulated signal to be modulated, and a specific period among the sampling values latched by the latch circuit The level of the sampling value of is the level of the sampling value of the main period among the sampling values of the modulated signal modulated by the data of "1". A demodulation circuit having a second judgment circuit for judging whether or not the demodulated output of the modulated signal is obtained from each judgment result of the first judgment circuit and the second judgment circuit. 2. The demodulation circuit according to claim 1, wherein the circuit for sampling the modulated signal captures the modulated signal in series by a clock signal synchronized with the serial input / parallel output. Demodulator circuit that is like a shift register. 3. The demodulation circuit according to claim 1, wherein the first determination circuit is a plurality of AND circuits to which sampling values of a specific period among the sampling values latched by the latch circuit are respectively supplied. And a OR circuit to which outputs of the plurality of AND circuits are supplied. The second determination circuit is configured such that among the sampling values latched by the latch circuit, sampling values in a specific period are respectively A demodulation circuit configured to include a plurality of supplied AND circuits and an OR circuit to which outputs of the plurality of AND circuits are supplied.