JPH0936721A - Capacitive load driver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the power loss of a drive current of a capacitive load by utilizing a resonance between the capacitive load and an inductive element. SOLUTION: When a drive signal P1 is at logical H, a switch SW1 closed and a switch SW2 is open and a capacitance Cx of a capacitive load 11 is charged by a DC power supply E via the switch SW1. When the signal P1 goes to logical L, the switch SW1 is open and the SW2 is closed, a current IL flows between the capacitor Cx and a coil 9 and a terminal voltage of the capacitor Cx is oscillated at a natural frequency fo together with the current IL. Then the switch SW1 is closed by a clock leading edge and the capacitance Cx is charged up to the power supply voltage E. In this case, a charging current Is1 is supplied from the power supply E to the capacitor Cx via the switch SW1 at a very small loss of the coil 9, the capacitor Cx and a ground terminal. The current Is1 causes a power loss in the drive current and its can be considerably lowered than the power loss in a push-pull connection.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive device for driving a capacitive load.

[0002]

2. Description of the Related Art FIG. 3 is a diagram showing a conventional example of a drive circuit of this type, in which a driver having a push-pull output stage drives a capacitive load (for example, the gate of an FET). As shown in FIG. 4, the capacitance Cx of the capacitive load is rapidly charged with the charging current I1 at the rising timing of the clock signal CK and rapidly discharged with the discharging current I2 at the falling timing of the clock CK signal. The power loss of the push-pull driver at this time is simplified and shown in FIG. In FIG. 5, the drive current of the push-pull driver is a constant current during the drive period for simplification, and the voltage change of the drive voltage of the capacitive load is assumed to be linear. In this simple model, the drive current Id and the drive voltage Vd have a relationship of Cx · V = Id · T T: rise (fall) time. The power loss Pt per driving cycle is [Id
-V (t)] is integrated by the rise (fall) time. When the power loss at the rise and fall is calculated, Pt = C · (V ^ 2) Note that “^” indicates a power number, and in this simple model, rise (fall)
The power loss of the push-pull driver does not change regardless of time.

[0003]

However, in the above-mentioned conventional example, the power loss of the driver depends on the capacitance value of the load and the drive amplitude, and does not depend on the rise and fall times (in the simple model). To drive a capacitive load with a large amplitude, it may be necessary to use a plurality of push-pull drivers in parallel.

For example, consider a line sensor as a capacitive load. The line sensor has a relatively large dimension compared to the area sensor, and its load capacity is several hundred to several thousand p.
It becomes F. Here, assuming that the load capacitance is 1000 pF, the drive amplitude is 7.5 V, and the drive frequency is 30 MHz, the power loss P of the push-pull driver according to the simple model is about 1.7.
W. In addition, the rise (fall time) is 10
If nsec, the peak value of drive current is 0.75
Become A. Due to the heat generation of the driver due to this power loss and the peak current, the limit of the maximum current, etc., several drivers must be used in parallel, and a large mounting area and
Problems such as increased costs arise.

The present invention solves such a problem.

[0006]

According to the present invention, an inductive element for exchanging a charging / discharging current of a load capacitance with the capacitive load is provided, and most of the charging / discharging current is transferred to the capacitive load. Power loss is reduced by providing a compulsory charging means which does not suffice by exchanging a current with the element and forcibly secures the drive voltage "H" level for an arbitrary period in synchronization with the input signal.

That is, according to the present invention, the capacitive load driving device is constructed as shown in (1) below.

(1) An inductive element that forms a series resonance circuit together with the capacitance of a capacitive load, a DC power source, and a switch means that intermittently connects the DC power source to the capacitive load in synchronization with an input signal. Capacitive load drive equipped with.

[0009]

The present invention will be described in more detail with reference to the following examples.

FIG. 1 is a circuit diagram of a "capacitive load driving device" which is a first embodiment.

In this embodiment, the driving end voltage is fixed to "H" outside the driving period. FIG. 2 is a timing chart for explaining FIG. A clock signal CK that drives the capacitive load 11 is input to the clock input terminal 1. CK is ANDed with the input terminal of the delay circuit 2
It is connected to the input terminal of the gate 3. AND gate 3
The other input terminal of is a negative input terminal and is connected to the output of the delay circuit 2. The output P2 of the AND gate 3 becomes a pulse signal having a pulse width corresponding to the delay amount Td of the delay circuit 2 from the rising edge of CK, and is connected to the input terminal of the OR gate 4. The DFF (D flip-flop) 6 receives the drive signal P1 at the data input terminal,
The output of the delay circuit 2 is input to the clock signal input terminal. The DFF 6 outputs a new drive signal P4 synchronized with the rising timing of the output of the delay circuit 2. The drive signal P4 is connected to the input terminal of the OR gate 4 and the control terminal of the second current switch SW2, and closes the SW2 period P2 of "L". The output P3 of the OR gate 4 is connected to the control terminal of the first current switch SW1, and when P3 is "H", SW1 is "closed" by the current switch.
To One of the current switches SW1 is connected to the DC power source E, and the other is connected to the coil 9 that is an inductive element and the capacitive load 11 that drives it. The other side of the coil 9 is grounded via the current switch SW2.
The capacitance of the capacitive load 11 is represented by Cx, and the inductance of the coil 9 is represented by Lx.

In FIG. 2, when the drive signal P1 is "H", the current switch SW1 is "closed", the current switch SW2 is "open", and the capacitance Cx of the capacitive load 11 (hereinafter referred to as load capacitance) is a current switch. It is charged by the DC power source E via SW1 and is fixed at the drive voltage E. When the drive signal P1 becomes “L” at the time t1, the time t
At the timing of 2, the current switch SW1 is in the "open" state and the current switch SW2 is in the "closed" state. Here, the current IL flows between the load capacitance Cx and the inductance Lx of the coil 9, and accordingly the terminal voltage of the load capacitance Cx, that is, the drive voltage, changes as Vo in FIG. IL and Vo are Lx,
Depending on the value of Cx, it vibrates at the natural vibration frequency fo fo = 1 / (2π · √ (Lx · Cx)). Here, the Lx value is selected from the CK frequency fck and the delay amount Td of the delay circuit 2 so that (1 / fck) −Td = 1 / fo. At time t3, SW1 becomes “closed” at the timing of the rising edge of the clock, and the power supply E is forcibly charged with the load capacitance Cx. At this time, the drive end voltage Vo is the timing at which one cycle of the natural vibration due to Lx and Cx has just ended from time t2. If there is no cause of loss in Lx, Cx, and the grounding end, time t
Vo = E at 3, but due to some loss, Vo <E
E. The charging current Is1 is supplied from the DC power supply E through the current switch SW1 so as to charge the load capacitance Cx with the slight potential difference dV (= E-Vo). Is1 and dV at this time correspond to the power loss of the driver described in the conventional example. When the power loss Ps1 in the current switch SW1 is calculated according to the simple model calculated in the conventional example, it becomes Ps1 = 0.5 · Cx · (dV̂2). The power loss Ppp in the push-pull of the conventional example is Ppp = Cx (E ^ 2), so the ratio is 1 / (2 (E / dV) ^ 2), and the loss can be significantly suppressed. it can.

Since the variations in the load capacitance Cx and the inductance Lx of the coil 9 are not "0", the natural frequency fo
It also varies. If (Lx · Cx) is ± 20%, a variation of √ (0.8) · To <Tx <√ (1.2) · To may occur with respect to the natural vibration period To at the set value fo. . Time t3 due to the variation
The drive end voltage Vo at the point fluctuates. Here, time t2
From time t3 to time t3, if the natural vibration is included for one cycle or more and the drive end voltage drops again, the drive frequency is regarded as fluctuation or noise. Therefore, when it is not desired to adjust the natural vibration frequency, Lx may be designed so that the maximum natural vibration frequency fmax considering the variation is (1 / fck) -Td = 1 / fmax. As mentioned above (Lx
Cx) ± 20% variation, the variation of natural vibration frequency / cycle due to the variation is fmax / fmin = √ (1.2) / √ (0.8) =
1.22 Tmax / Tmin = 0.82, and Vo at the highest natural vibration frequency is shown between time t2 and time t3 in FIG. 2 at Vo at the lowest natural vibration frequency. At this time, the difference of Vo is at time t
When Vo in 3 is E, the drive voltage Vomin at time t3 is Vomin = E · cos (0.82 · 2π) = 0.43.
E In this worst case, the power loss P of the current switch SW1
Calculating wst gives Pwst = 0.5Cx {(1-0.43) E} ^ 2 = CxE2 / 2 / 6.2, which can be suppressed to about 1/6 of the power loss of the conventional push-pull. After the time t3, the operation from t2 to t3 is repeated until the driving signal P1 becomes "H", and the capacitive load 11 is driven. The delay amount of the delay circuit 2 may be set to a time satisfying the required limit of the "H" period of the drive voltage, if necessary.

In this way, according to this embodiment, the power loss can be drastically reduced.

[0015]

As described above, according to the present invention, the dielectric element for exchanging the charge / discharge current with the load capacitance is provided, and most of the drive current of the capacitive load is distributed between the capacitive load and the dielectric element. Since the resonance is used, the power loss can be drastically reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment.

FIG. 2 is a timing chart of the embodiment.

FIG. 3 is a circuit diagram of a conventional example.

FIG. 4 is a timing chart of a conventional example.

FIG. 5 is an explanatory diagram of power loss of a drive circuit.

[Explanation of symbols]

 8 Current switch 9 Coil 11 Capacitive load E DC power supply

Claims (1)

[Claims] 1. An inductive element that forms a series resonance circuit together with a capacitance of a capacitive load, a DC power supply, and a switch means that connects the DC power supply to the capacitive load intermittently in synchronization with an input signal. A capacitive load drive device characterized by the above.