JPH0936314A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor device provided with a capacitance element of large capacity, by constituting a capacitance element of lamination structure sandwiching a dielectric film between a lower electrode and an upper electrode, and making the dielectric film contain Ta oxide, Nb oxide, and one or more kinds of elements selected out of a group of Ca, Sr, etc. SOLUTION: A conducting layer 11 turning to the lower electrode of a capacitor is formed by sputtering a Pt target. Coating solution for forming a dielectric film 12 is obtained by preparing (CH3 OC2 H4 O)2 Sr and Ta(OC2 H5 )5 in solvent CH3 OC2 H4 OH in the manner in which the ratio Sr:Ta is 1:1 and the total concentration is 4mol/l. The electrode conducting layer 11 constituted of a Pt thin film is spin-coated with the coating solution. By repeating three times a heat treatment process wherein heating is performed at about 750 deg.C for about 30 minutes, a dielectric layer 12 of 200nm in thickness is obtained. On the dielectric film 12, an Ni film is formed by sputtering Ni, and patterned into an electrode pad of 20μm square. Thus a conducting layer 13 of an upper electrode is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a capacitive element.

[0002]

2. Description of the Related Art Recently, an integrated circuit (Inte
A gated circuit (IC) is formed by integrating transistors, capacitors (capacitors), and the like on the same semiconductor chip. One of the important factors that determines the cost of an IC is the size of a semiconductor chip, and the smaller the chip size, the lower the cost. Therefore, it is important to reduce the area occupied by each element on the semiconductor chip. is there. Above all, the area occupied by the capacitance is large relative to the entire chip area, and therefore, reducing the area occupied by the capacitance greatly contributes to the chip size reduction.

Further, in a high-frequency element, loss can be reduced by shortening the wiring length, so it is strongly desired to reduce the area occupied by the capacitance in the element from the viewpoint of improving the characteristics. Further, conventionally, a capacitor having a particularly large capacity for noise absorption is not built in a semiconductor chip but is separately mounted together with the semiconductor chip on a circuit board and used by being connected by means such as wire bonding. If it becomes possible to incorporate a capacitor externally attached by wire bonding outside the semiconductor chip on the circuit board, the effect of shortening the wiring length and the effect of simplifying the mounting process will be greater.

In response to such a demand, strontium titanate (SrTiO ₃ ) which is a perovskite-based dielectric material having a high dielectric constant of 200 to 1000 is used in place of the SiO ₂ film and the SiON film which have been conventionally used for ICs. And barium strontium titanate ((Ba, Sr) TiO 3
₃ ), PZT (Pb (Zr, Ti) O ₃ ) and other dielectric thin films have been tried, and they are expected to have an area reduction effect.

[0005]

However, since these substances have a large dielectric constant of 200 to 1000,
Capacitance variation within the film or between elements is large, and the temperature coefficient of permittivity is as large as ± 800 ppm / ° C or more in the temperature range from room temperature to 150 ° C, so it is effective as a capacitor for absorbing noise and surge. However, it was not suitable as a capacitor for stopping oscillation or adjusting the phase.

A further practical problem is the voltage dependence of capacitance in these thin films. The SiO ₂ film and SiON film that have been conventionally used in ICs have no voltage dependence. On the other hand, in a capacitor component made of bulk ceramic, the thickness between electrodes is 100 to 10 times that of the thin film.
Since it is 00 times, the electric field is driven at a very small value, so that the voltage dependence of the high dielectric constant material has hardly been a problem.

However, when a high dielectric constant material is used as a thin film, it corresponds to use under an extremely large electric field even when the driving voltage is 3V to 5V. For example, when a thin film capacitor having a film thickness of 100 nm to 1 μm is used at 5 V, a large electric field of 50 to 500 kV / cm is applied. High-dielectric constant materials inherently have large electric field dependence, but electric field dependence, which is not a problem in bulk materials such as ceramics and single crystals, will be highlighted as an extremely large problem in thin films. For example, the electric field dependence of thin-film capacitors is 30% in conventional high dielectric constant materials.
The above-mentioned size cannot be ignored, and it has been a hindrance when attempting to design capacitors for multiple purposes at the same time.

Further, in the case of an analog element composed of a plurality of passive elements including a capacitive element and an active element, conventionally, a capacitor for all purposes is simultaneously formed on the same substrate with a SiO ₂ film or a SiON film having no voltage dependence. Therefore, forming the above-mentioned material-based film on the IC, which can replace only the capacitor for some applications, requires more than twice the process cost, and is industrially advantageous. There was a problem that it did not come out.

Of course, when an external chip capacitor is to be built in, a process different from that for the internal capacitor is required, which may be disadvantageous in terms of process cost and contribute to the reduction of area. However, in many devices, it was not possible to industrially utilize the above-described material-based dielectric film. Further, the above-mentioned material system contains a Ti element, and TiOx is easily generated during the film production, which causes a problem that the dielectric film is easily converted into a semiconductor.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device having a large-capacity capacitive element despite its small size and high accuracy.

[0011]

A semiconductor device according to the present invention is a semiconductor device provided with, for example, an analog element composed of a plurality of passive elements including a capacitive element and an active element, wherein the capacitive element is a lower electrode and an upper electrode. And a dielectric film sandwiched between them and the dielectric film contains at least one of Ta oxide and Nb oxide, and Ca, Sr,
It is characterized in that it contains at least one element selected from the group consisting of Ba, Mg, and Zn.

A semiconductor device including a plurality of passive elements including a capacitive element and an active element, wherein the capacitive element is 80
The capacitive element has a circuit structure through which a high-frequency signal of 0 MHz or more passes, and the capacitive element has a laminated structure in which a dielectric film is sandwiched between a lower electrode and an upper electrode.
A composite oxide dielectric film of 1 micron or less represented by ak Nb1-k Ox is desirable.

The dielectric film can be represented by the general formula MTak Nb1-k Ox, where M is Ca, Sr, Ba, Mg, Zn.
Of at least one element selected from the group
In particular, the dielectric film is a paraelectric material in the temperature range from room temperature to 150 ° C., and the temperature coefficient of the dielectric constant of the dielectric film is ± 500 ppm / ° C. or less in the temperature range from room temperature to 150 ° C. Is more desirable. This is because the dielectric film MTak Nb1-k Ox has a stable structure as a complex oxide and has a dielectric constant of 20 to 100 when M represents at least one element of Ca, Sr, Ba, Mg and Zn. Film formation is possible within the range. Here, even when the dielectric constant is close to 100, the variation can be kept within ± 3% at most.

Further, although the dielectric film composition does not necessarily have a paraelectric structure and the ferroelectric structure has a sufficiently small loss, even a slight hysteresis loss becomes a problem particularly at a high frequency, so that it is from room temperature to 150 ° C. It is desirable that the material is a paraelectric material in the temperature range of. With these compositions, tan δ representing loss is 1% or less, so that low loss can be achieved. Here, the meaning of being a paraelectric material means that hysteresis loss is extremely small. Therefore, it is sufficient that the material does not have an effective ferroelectric hysteresis even in the composition range of the ferroelectric structure. That is, it suffices if the easy polarization axis is not parallel to the direction of the electric field. For example, an alignment film having the easy polarization axis parallel to the plane is also effective.

Furthermore, the temperature coefficient of the dielectric constant of the dielectric film is ± 500 in the temperature range from room temperature to 150 ° C.
More preferably, the composition range is ppm / ° C. or less. If M of the MTak Nb1-k Ox composition is a single element, another M that induces the opposite temperature coefficient even if it exceeds ± 500 ppm / ° C in the temperature range from room temperature to 150 ° C. ± 50 due to solid solution substitution of elements
It can be 0 ppm / ° C. or less. It should be noted that x represents an integer or a decimal number, and when x is a decimal number, it can be expressed by an integer ratio of Ma (Tak, Nb1-k) aOax with respect to an integer (ax). However, the subscript k is 0 ≦ k ≦ 1
Various values can be taken within the range of. In addition, M /
(Ta + Nb) [atomic ratio] is preferably in the range of 0.6 to 2.4. In this case, M / (Ta + Nb)
When the [atomic ratio] is in the range of 0.9 to 1.1, a dielectric film having a relatively high dielectric constant and a loss of 1% or less can be obtained. Further, when M / (Ta + Nb) [atomic ratio] is in the range of 1.8 to 2.2, temperature characteristics of dielectric constant (small change rate) can be obtained. From the standpoint of physical properties at temperature, it is preferable that Mg and Zn in M be less than 50 atomic%, but due to the high dielectric constant, Sr and Ca.
A composite system of Mg and Zn is preferable.

The method of forming the dielectric film includes sputtering and CV.
There are coating methods such as D, reactive vapor deposition, MOD and sol-gel method. In these dielectric films, control of crystal orientation, that is, promotion of orientation and promotion of epitaxial growth are also effective. In the present invention, the high frequency characteristics are not adversely affected even if other elements are added or replaced in the main component within the range of 5 mol% or less. Elements that can be added include Sn, Hf, Ho, M
There are n, Fe, Pb, etc., and these can delicately control the structural change due to heat treatment.

When the dielectric thin film of the present invention is used as a charge storage layer in an electronic component, the charge storage amount is the conventional SiO ₂
Compared with the film or the SiON film, the same area can be made five times or more, and the chip area can be greatly reduced.

Further, the voltage dependence can be suppressed to less than 5% at the practical voltage of 5 V at most, and capacitors for a plurality of uses can be simultaneously formed. Further, the thin film dielectric component of the present invention does not include a Ti component that causes the film to become a semiconductor, and is extremely stable chemically even in the heat treatment process repeated several times in the device manufacturing process. . Further, the present invention can be implemented in a semiconductor device using a compound semiconductor substrate such as GaAs in addition to the silicon substrate.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Various embodiments of the present invention will be described below. (Example 1) In Example 1, the capacitor 10 shown in FIG.
A case where a circuit having the MOS transistor 20 and the MOS transistor 20 is manufactured will be described as an example.

First, an insulating film 2 made of a silicon oxide film was formed on a silicon substrate 1 and a part of the silicon oxide film was removed by etching to form a hole for a buried channel which became a MOS transistor 20. Next, a conductive layer 11 is formed at a position adjacent to this hole, a dielectric film 12 is laminated on this, and a conductive layer 13 for electrodes is further laminated to form a laminated capacitor structure.

On the other hand, a gate oxide film 21 is formed almost in the center of the buried channel hole, and a conductive layer 22 is formed on the gate oxide film 21.
Were laminated to form a laminated gate structure. Further, an impurity element was implanted into the substrate 1 exposed in the holes to form a p-doped layer 23 and an n-doped layer 24, respectively.

Next, an insulating layer 25 made of a silicon oxide film is formed by a CVD film forming process, and the insulating layer 25 is masked and etched to remove the insulating layer 25 from the peripheral region of the laminated gate structure and the upper region of the laminated capacitor structure. Remove. Further, the conductive layer 26 is formed in the peripheral region of the stacked gate structure.
Is formed, and the conductive layer 27 is further laminated thereon. Finally, the Al wiring 30 is formed to form the electrode conductive layer 13 of the capacitor 10 and the electrode conductive layers 26 and 27 of the MOS transistor 20.
By connecting and, the capacitor / MOS transistor circuit is completed.

Further, the manufacturing method and performance of the capacitor 10 will be described in detail. The conductive layer 11 to be the lower electrode of the capacitor 10 was formed by sputtering a Pt target.

As a coating liquid for forming the dielectric film 12, (CH
In _{3 OC 2 H 4 O) 2} Sr and Ta (OC ₂ H _{5) 5} and CH ₃ OC ₂ H ₄ OH solvent, Sr: the ratio of Ta is 1:
It was adjusted to 1 and the total concentration was adjusted to 0.4 mol / l. This coating liquid is used as an electrode conductive layer 1 made of a Pt thin film.
1 was spin-coated and the heat treatment step of heating at about 750 ° C. for about 30 minutes was repeated three times to obtain a dielectric thin film with a film thickness of 200 nm. When the thin film layer 12 was identified by X-ray diffraction, it was confirmed that Sr ₂ Ta ₂ O ₇ (= SrTaO _3.5 ) was generated.

Ni is sputtered on the dielectric film 12 to form a Ni film, and the Ni film is patterned into a 20 μm square electrode pad by lithography to form a conductive layer 13 serving as an upper electrode.
Was formed.

When the capacitor component between the Pt electrode and the Ni electrode was measured, it was almost constant at 8 pF in the range up to the 10 MHz band. The variation in capacity within the 3-inch diameter wafer was within ± 2%. Furthermore, it was confirmed from the high-frequency impedance measurement up to GHz band using a network analyzer that it works effectively as a capacitance component up to 10 GHz or more. (Example _{2) (CH 3 OC 2 H} 4 O) 2 Sr and Nb
(OC ₂ H ₅ ) ₅ in CH ₃ OC ₂ H ₄ OH solvent in S
A solution having a concentration of r: Nb of 1: 1 and a concentration of 0.4 mol / l was prepared and mixed with the same solution as in Example 1 to prepare the following two types of coating solutions having different Ta: Nb composition ratios. Prepared.

The first coating liquid has a mixing ratio of 1: 9, and the second coating liquid is
The mixing ratio of the coating liquid of (2) was set to 2: 8. Each of these two types of coating solutions was formed into a thin film in the same manner as in Example 1 and
A 5 pF capacitor and a 30 pF capacitor were obtained.
It was also confirmed that the capacitor component worked effectively up to 10 GHz or higher. In the temperature range from room temperature to 150 ° C, the capacity change rate is -200 ppm / ° C (-0.
02% / ° C) and -50 ppm / ° C (-0.005%)
/ ° C). Further, when X-ray diffraction of these dielectric films was performed, it was found that they were oriented in the b-axis, and no hysteresis was observed in the spontaneous polarization-electric field curve.
It was found to be paraelectric with respect to the direction of the electric field. (Comparative Example _{1,2) (CH 3 OC 2 H} 4 O) 2 Sr and Ti (OC ₂ H _{5) 4} and _{CH 3 OC 2 H 4 OH SrTiO} 3 film from a mixed solution in a solvent, (CH ₃ OC ₂ H
₄ O) ₂ Sr, (CH ₃ OC ₂ H ₄ O) ₂ Ba and T
A (Ba, Sr) TiO ₃ film was prepared from a solution of i (OC ₂ H ₅ ) ₄ mixed in a CH ₃ OC ₂ H ₄ OH solvent in Example 1,
Comparative Example 1 and Comparative Example 2 were formed in the same manner as in Example 2. Among these, the voltage dependence of capacitance was compared for capacitors having a film thickness of 200 nm.

In FIG. 2, the horizontal axis represents voltage and the vertical axis represents voltage 0.
FIG. 7 is a characteristic diagram comparing the example and the comparative example with respect to the voltage dependence of the capacitance in a capacitor having a film thickness of 200 nm by taking the capacitance change rate (%) when the capacitance value at V is 100%. In the figure, a curve A shows the result of Example 1, a curve B shows the result of Comparative Example 1, and a curve C shows the result of Comparative Example 2. As is clear from the figure, the capacitor of Example 1 has a lower voltage dependence of capacitance than those of Comparative Examples 1 and 2, and is suitable for being incorporated in an IC circuit as a highly accurate and stable element. did. That is, in the capacitor of Example 1, the capacity reduction rate was only 2% or less even when the capacity reduction rate was 5 V driving, whereas in Comparative Examples 1 and 2, the reduction rate was 15% or more when 5 V driving. .

According to the above-described embodiment, the capacitance change rate of the capacitor becomes extremely small with respect to the voltage fluctuation, so that it is possible to increase the capacity while maintaining the performance of the capacitor with high accuracy. Therefore, if the capacitors have the same rated capacity, the area can be made smaller than in the conventional case, which is advantageous in the design of the IC circuit.

Further, there is an advantage that a capacitor, which has been conventionally connected as an external element of a semiconductor chip by wire bonding or the like, can be incorporated in a chip circuit, and a package can be downsized. (Example _{3) (CH 3 OC 2 H} 4 O) 2 Ca, (CH 3
OC ₂ H ₄ O) ₂ Sr and Ta (OC ₂ H ₅ ) ₅ as C
In H ₃ OC ₂ H ₄ OH solvent, Ca: ratio of Sr is zero.
The ratio was 1: 0.9, the ratio of (Ca + Sr): Ta was 1: 1, and the total concentration was 0.3 mol / l. Each of the coating solutions was thinned in the same manner as in Example 1 to confirm the capacitor component. When the profile in the depth direction was examined by Auger electron spectrum for this capacitor structure, Ca component, Sr component and T
Almost no diffusion of the component a was observed. (Embodiment 4) The MOS transistor 20 shown in FIG. 1 was formed, and the following respective films were formed on the Si wafer after the interlayer film reflow by RF sputtering.

First, 0.5P using a Pt target
RF sputtering was performed at a high frequency power of 500 W in Ar gas of a. Then, using an oxide sintering target of Sr ₂ Ta ₂ O ₇ , Ar / O _{2 of} 0.5 to 1.0 Pa was used.
Sputtering was performed in a gas with a high frequency power of 200 W, and further, sputtering was performed with a high frequency power of 500 W in a N ₂ gas of 0.5 Pa with a high frequency power of 500 W. Upper WNx film, Sr ₂ Ta
_{The 2} O ₇ film and the lower Pt film were patterned by ion milling. S is formed as an interlayer film on the obtained capacitor structure.
An iO ₂ film was formed by CVD, contact holes were formed between the MOS transistor and the capacitor, and Al wiring was further formed. Finally, plasma Si ₃ N ₄ was formed as a protective film. The analog-digital mixed LSI with a built-in bypass capacitor formed in this process has a higher harmonic component of unnecessary radiation than that of a chip with an external bypass capacitor.
It decreased to dB. (Embodiment 5) The same steps as in Embodiment 4 were introduced into the manufacture of a monolithic microwave IC using a GaAs substrate to manufacture a power amplifier for mobile communication. It was possible to reduce the loss in the GHz band by 5 dB as compared with the conventional amplifier in which the capacitor was composed of the SiON film.

By using the capacitor of this embodiment, a circuit having a low inductance can be obtained in a high frequency region. (Example 6) An oxide sintered body containing (Ba, Mg, Ta) in a ratio of 3: 1: 2, or an oxide containing (Ba, Zn, Ta) in a ratio of 3: 1: 2. Targeting each sintered body, laser ablation gives a film thickness of 250n
A thin film of m was formed on the RuO ₂ electrode and the ReO ₃ electrode. When the upper electrode was the same oxide electrode and the capacitor characteristics were measured, the dielectric constant of the former was 25, and the dielectric constant of the latter was 30. Thus, in both cases, the temperature change rate of the dielectric constant was 6 ppm / ° C, which was extremely small in the range from room temperature to 150 ° C.

A semiconductor device could be obtained by mounting such a capacitance portion as an oscillation stopping capacitor, a surge absorbing capacitor, a noise absorbing capacitor, or the like in a bipolar IC.

[0034]

The semiconductor device of the present invention can simultaneously satisfy the requirements of the capacitor component for various purposes.
Not only the cost can be reduced due to the effect of reducing the capacitor area, but also the manufacturing can be performed without adopting a plurality of processes, so that it is not necessary to increase the process cost due to the reduction in area. Therefore, it is extremely effective industrially. Further, in the manufacturing process, it is difficult to affect other parts of the device and the temperature coefficient is small, which is extremely advantageous in the IC design.

[Brief description of drawings]

FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a characteristic diagram showing voltage dependence of capacitor capacitance.

[Explanation of symbols]

 10 ... Capacitor 11, 13 ... Electrode layer 12 ... Dielectric layer 20 ... MOS transistor

Claims (1)

[Claims] 1. A semiconductor device comprising a plurality of passive elements including a capacitive element and an active element, wherein the capacitive element has a laminated structure in which a dielectric film is sandwiched between a lower electrode and an upper electrode. The body film contains at least one of Ta oxide and Nb oxide, and Ca, Sr, Ba, Mg, Z
A semiconductor device comprising at least one element selected from the group n.