JPH0935013A - Ic card reader and ic card writer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that data can not be read out or written on plural kinds of IC card differing in operation clock. SOLUTION: This IC card reader writer 1 contains a control circuit 6, power source 7, SRAM 8, an EEPROM 9, display driving part 10, reset control part 11, power source control part 12, communication control part 13, clock control part 10, reset control part 11, power source control part 12, communication control part 13, clock control part 14, and oscillator 15. In the control circuit 6, a communication speed varying program is registered which holds an operation clock to an IC card constant according to data sent back from the IC card and varies a communication speed to enable a read of plural kinds of IC card differing in operation clock. Consequently, the control circuit 6 automatically varies the communication speed even when IC cards having plural kinds of operation clock are inserted and can read and write data irrelevantly to the operation clocks of the IC cards.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC card reading device and an IC card writing device, and more particularly to an IC card reading device and an IC configured to read / write data in a memory of an IC card at a predetermined clock frequency. The present invention relates to a card writing device.

[0002]

2. Description of the Related Art Memory (EE) for storing personal data
A management system that manages personal data by distributing an IC card having a built-in PROM (PROM) and a one-chip microcomputer for controlling reading and writing of data to each person is being developed. For example, IC card reading /
By installing a writing device, it is possible to store the time of arrival and departure of people at multiple offices, the date, etc. in the IC card, so that each person can carry an IC card with him and the IC card installed in each office. By simply inserting an IC card into the reading / writing device, it is possible to manage the data such as the office work time, leaving time, and work days of each individual.

In the IC card reading / writing device, when the IC card is inserted, a predetermined operation clock and power are supplied through a terminal provided on the surface of the IC card, and data reading / writing is performed. To do.
In the IC card used in this way, the clock frequency for transmitting and receiving data is specified. Therefore, the control device of the IC card reading / writing device is configured to perform communication with a specified operation clock.

Further, the shape and each dimension of the IC card are determined by the ISO standard, but conventionally, plural kinds of IC cards having different operation clocks have been used. Although this operation clock is also standardized by the ISO standard, it is demanded that any IC card can be used in the IC card reading / writing device.

Therefore, in the conventional IC card reading / writing device, a circuit board having a plurality of oscillation circuits for generating respective operation clocks of the IC card is provided so as to be compatible with a plurality of types of IC cards having different operation clocks. It has been provided. Therefore, when the IC card is inserted into the IC card reading / writing device, the I
The operation clock of the C card is detected, and the oscillation circuit of the operation clock detected as a result is selected and switched.

[0006]

However, in the conventional IC card reading / writing apparatus having the above-mentioned structure, the number of oscillation circuits corresponding to a plurality of types of IC cards having different operation clocks is required. As a result, the number of circuit boards increases and the number of parts also increases, so that it takes time and effort to assemble, and when an IC card with a different operation clock is created, a new oscillator circuit must be added. There is.

Furthermore, it is necessary to previously provide a space and a connector for adding an oscillation circuit in the device.
If there is no free space, a new oscillator circuit cannot be added, and an IC card with a new operating clock cannot be used. Therefore, an object of the present invention is to provide an IC card reading / writing device that solves the above problems.

[0008]

In order to solve the above problems, the present invention has the following features. Claim 1
According to another aspect of the present invention, there is provided an IC card reading device having a card insertion section into which an IC card is inserted and a data reading section for reading data stored in a memory of the IC card inserted into the card insertion section. It is characterized by comprising a communication speed changing means for keeping the operation clock to the IC card constant based on the reply data, changing the communication speed, and making it possible to read a plurality of types of IC cards having different operation clocks. It is a thing.

Therefore, according to claim 1, a plurality of types of ICs having different operation clocks by changing the communication speed.
Even if the card is inserted, the data can be read at the communication speed according to the operating clock. Further, the invention of claim 2 has an IC card having a card insertion part into which the IC card is inserted, and a data writing part for storing data in the memory of the IC card inserted into the card insertion part at an operating clock of a predetermined frequency. In the writing device,
A communication speed changing means is provided which keeps the operation clock to the IC card constant based on the reply data from the IC card, changes the communication speed, and enables writing to plural kinds of IC cards having different operation clocks. It is characterized by becoming.

Therefore, according to claim 2, a plurality of types of ICs having different operation clocks by changing the communication speed.
Even if the card is inserted, data can be written at the communication speed according to the operation clock.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. Fig. 1 shows the IC card reading
FIG. 2 is a perspective view of the writing device, and FIG. 2 is a block diagram of the IC card reading / writing device.

The IC card reading / writing device 1 is
When viewed from the side, it is formed in a substantially triangular shape, and the front surface 1a is inclined so that the card insertion operation can be performed easily. At the center of the front surface 1a, a display 2 made of a liquid crystal display is arranged, and card insertion ports 4 and 5 into which an IC card 3 is inserted are arranged on both left and right sides of the display 2.

Inside the IC card reading / writing device 1, a control circuit 6, a power supply 7, an SRAM 8 and an EEPRO are provided.
M (Electrically Erasabie Programmable Read Only M
emory) 9, display drive unit 10, reset control unit 11, power supply control unit 12, communication control unit 13, clock control unit 14,
The oscillator 15 is housed.

The control circuit 6 is a device for controlling the entire apparatus and is composed of a one-chip microcomputer. The power supply 7 supplies power to each device in the apparatus 1 and also supplies power to the IC card 3 inserted in the card insertion ports 4 and 5. The SRAM 8 is a static memory,
When the control circuit 6 performs control, data is temporarily stored. The EEPROM 9 is a non-volatile memory that can be electrically written, and stores a control program for controlling the control circuit 6 and various data. In this control program, the operation clock of the communication control unit 13 is based on the reply data from the IC card 3
A communication speed change program for changing the communication speed to match the operation clock of is registered.

The display drive section 10 displays a message on the display 2 and is also used as an area for passing display data from the control circuit 6. The reset control unit 11 is a control unit that inputs a reset pulse to the IC card 3, and the IC card 3 starts its operation when the reset pulse is input. Further, the power supply control unit 12
The power supply to the C card 3 is controlled, and the IC card 3
The power supply is not shut off during communication with, and the power supply is controlled so as to be shut off when the IC card 3 is ejected.

The communication control unit 13 is in communication with the IC card 3 and transmits / receives transmission data such as attendance time or leaving time. Since the IC card 3 is used for both transmission and reception, the communication control unit 13 switches the IC card 3 between transmission and reception. Therefore, when the transmission / reception switching signal a is output from the control circuit 6, the communication control unit 13 switches the communication mode for the IC card 3 to transmission or reception. Therefore, the communication control unit 13 supplies the transmission data b to the IC card 3 by supplying the transmission / reception switching signal a.
Or the received data b from the IC card 3 is received to read / write data from / to the IC card 3.

The clock controller 14 controls the clock pulse output from the oscillator 15 by the control signal from the control circuit 6. The oscillator 15 is made of, for example, a crystal oscillator and has a constant frequency (in the present embodiment, 3.
It is formed to output a clock pulse of 5795 MHz).

FIG. 3 is a block diagram showing the configuration of the IC card 3. The IC card 3 has a CPU 17 composed of a one-chip microcomputer and an EEPROM 18 inside. Further, on the surface of the IC card 3, external terminals are provided which are connected when the IC card 3 is inserted into the card insertion ports 4 and 5 of the IC card reading / writing device 1. In this embodiment, the power supply terminal (Vcc) 19, the reset terminal (RST) 20, the clock terminal (CLK) 21, and the ground terminal (GND) 2
2, power supply terminal (Vpp) 23, I / O interface (I
/ O) 24 and other external terminals are provided on the IC card 3.

When the IC card 3 having the above structure is inserted into one of the card insertion ports 4 and 5, the power supply terminal (Vcc) 1
9 is connected to the power control unit 12 to supply power to the CPU 17, and the reset terminal (RST) 20 is connected to the reset control unit 11. At the same time, the clock terminal (CLK) 21 is connected to the clock control unit 14 and receives a clock pulse, and the I / O interface (I / O)
O) 24 is connected to the communication control unit 13 and receives the transmission data such as attendance time or leaving time output from the control circuit 6. Therefore, the transmission data transmitted from the communication control unit 13 is supplied to the CPU 17 via the I / O interface (I / O) 24 and stored in the EEPROM 18.

FIG. 4 is a block diagram of communication clock generation which is processed inside the CPU 17. A communication clock generation unit 25 divides the operation clock CLK (3.5795 MHz) supplied from the clock control unit 14 into 1 / n to generate a communication clock CLK / n.

Reference numeral 26 is a communication control section, which is a communication clock CLK / n divided by 1 / n in the communication clock generation section 25.
Communicate in synchronization with. The frequency division value n is 9
It is set to 600 bps (CLK / n = 9600 Hz). Here, the processing of the first embodiment executed by the control circuit 6 will be described with reference to the flowchart of FIG.

The control circuit 6 has a power switch (not shown).
When is turned on, the processing shown in FIG. 5 is executed to communicate with the IC card 3 inserted into one of the card insertion ports 4 and 5. When a power switch (not shown) of the device 1 is turned on, the initial value of the communication speed of the control circuit 6 is set in step S1 (hereinafter "step" is omitted). In the next step S2, the IC card 3
Power is supplied to the power supply terminal (Vcc) 19 of. And S
At 3, the operating clock pulse is supplied. By the processing up to this point, the communication preparation stage with the IC card 3 is completed.

At the next step S4, the reset control unit 11 outputs I
A reset pulse is input to the C card 3 to prompt the start of operation, and at the same time, a communication connection request is made. In response to this request, the CPU 17 of the IC card 3 transmits reply data stored in the EEPROM 18 for specifying the attribute of the IC card 3 from the I / O interface (I / O) 24 to the communication control unit 13. .

The control circuit 6 analyzes the reply data transmitted from the IC card 3 and determines whether the reply data is the specified data (S5). If the reply data is defined data, it is determined that the communication speeds match, and the process proceeds to S6. Then, in S6, communication with the IC card 3 is performed,
The transmission data such as attendance time or leaving time is sent to the EE of the IC card 3 via the I / O interface (I / O) 24.
It is stored in the PROM 18. Or EEP once a month
Data such as attendance time or leaving time stored in the ROM 18 is read.

When the communication with the IC card 3 is completed, S7
Then, the IC card 3 is ejected (discharged) from the card insertion ports 4 and 5, and a series of processing is completed. However, in S5, the reply data is invalid,
If the transmission and reception are not normally performed, it is determined that the communication speeds do not match, the process proceeds to S8, the communication speed is changed to the next communication speed, and the initial connection is performed again. As a method of changing the communication speed in S8, a plurality of communication speeds are stored in advance, and in S5, when the reply data is invalid or the transmission / reception is not normally performed, the communication speed is stored in advance. There is a method in which the communication speed is changed by sequentially selecting from a plurality of communication speeds.

Alternatively, when the type of the IC card 3 used is limited to several types, the communication speed with each IC card 3 can be predicted, so that the control circuit 6 and the communication control unit 13 can be used. Setting values for operating the IC cards 3 at the communication speed are stored in the EEPROM 9 in advance. Then, if the reply data is invalid in S5 or the transmission / reception is not normally performed, the communication speed is changed for each set value stored in S8 to correspond to the target IC card 3. Program to select the communication speed to be used. In this case, the new clock I
When the C card is issued later, the communication speed corresponding to the new clock is stored in the EEPROM 9 each time.

Then, in the next S9, it is checked whether or not all the communication speeds of the plurality of communication speeds stored in advance have been tried. If there is a communication speed that has not been tried yet, in S8. The processing of S4 and S5 is performed at the changed communication speed and it is confirmed whether or not the reply data is valid.
In this way, when the response data is validated by repeating the processes of S4, S5, S8, and S9, the process proceeds from S5 to S6, and the above communication process is performed.

However, in S9, when all the communication speeds have been tried, but the reply data is invalid or the transmission / reception does not operate normally, the process proceeds to S10, and the usable IC card is used. When it is determined that a card other than 3 is inserted, the card is ejected from the card insertion ports 4 and 5, and a series of processing is completed.

As described above, by changing the communication speed, even if a plurality of types of IC cards 3 having different operation clocks are inserted, data reading / writing can be performed at the communication speed according to the operation clocks. Therefore, the control circuit 6 can automatically change the communication speed even when the IC cards 3 having a plurality of types of operation clocks are inserted to read / write data regardless of the operation clocks of the IC card 3. Therefore, the user can insert the device into the device 1 to read / write data regardless of the type of the IC card 3, and thus the IC card 3 can be effectively used. Further, since it is not necessary to provide a circuit board for each operation clock inside the device 1 unlike the conventional device, the configuration can be simplified as compared with the conventional device, and
The manufacturing cost can be kept low.

Here, the method of changing the communication speed executed in S8 will be further described. As another method of changing the communication speed other than the above, for example, when the reply data is invalid in S5 or the transmission / reception cannot be performed normally, the communication speed that can be used by the control circuit 6 is changed from the minimum communication speed. It is conceivable to program to try all communication speeds by changing to the maximum communication speed or from the maximum communication speed to the minimum communication speed.

In this case, since the communication speed can be changed at random, even if an IC card with a new operation clock is issued later, the communication speed of the new operation clock is set as it is. Then, the new communication speed is stored, and when the IC card with the new operation clock is inserted, the new operation clock is programmed so that the communication speed of the new operation clock is selected from the next time. It can be dealt with easily.

For example, it is assumed that there are IC cards 3 having operation clocks of 3.5795 MHz and 4.9152 MHz. Then, the oscillator 15 has 3.5795
As an example, a case in which a clock pulse of MHz is used will be described. As shown in FIG. 4, the IC card 3 receives the operation clock CLK from the clock controller 14.
When (3.5795 MHz) is supplied, the communication clock generation unit 25 divides the operation clock CLK into 1 / n and supplies the communication clock CLK / n to the communication control unit 26.
Here, the frequency division value n is such that the communication speed (the number of bits per second) is 9600 when a prescribed operation clock is supplied.
It is set to be bps (CLK / n = 9600 Hz).

Now, 3.5 is provided in one of the card insertion ports 4 and 5 of the IC card reading / writing apparatus 1 configured as described above.
When the IC card 3 that operates at the operation clock of 795 MHz is inserted, communication with the IC card 3 is performed at the communication speed of 9600 bps as specified.

FIG. 6 is a diagram showing a difference in communication pulse width due to a difference in communication speed. 6A shows the waveform of the clock pulse of 3.5795 MHz output from the oscillator 15, FIG. 6B shows the communication pulse width of the operation clock of 3.5795 MHz, and FIG. Indicates a communication pulse width of 4.9152 MHz.

However, at one of the card insertion ports 4 and 5 of the IC card reading / writing device 1, 4.9152 MHz is provided.
When the IC card 3 which operates with the operation clock of is inserted, the IC card 3 cannot be read or written as it is. In this case, since the frequency of the operation clock is 73% of the specified value, 1 of 4.9152 MHz is set.
Communication pulse width B per bit is C (37%) compared to communication pulse width A per bit at 3.5795 MHz
Only longer.

This is 4.9152 MHz as described above.
This is because the frequency division value n is set in the IC card 3 such that the communication clock generation unit 25 generates the communication clock of 9600 Hz when the specified operation clock is input. Therefore, the communication pulse width B per bit of 4.9152 MHz can be expressed by the following equation (1).

B = (4.9152 MHz / 3.5795 MHz) × 1/9600 Hz ≈143 μs (1) The communication speed (the number of bits per second) in this case is 1
/ 143 μs≈6993 bps. Therefore, the control circuit 6 and the communication control unit 13 communicate with the IC card 3 at the communication speed of 6993 bps.

Therefore, when it is determined in S5 that the reply data transmitted from the IC card 3 is invalid, or when the transmission / reception is not normally performed, the communication speed is changed from the specified value of 9600 bps to 6993 bps in S8. Change to. When the specified value of the operation clock set in the control circuit 6 is 4.9152 MHz, 3.5795
When the MHZ IC card is inserted, the communication speed is calculated as follows.

Communication speed = 9600 bps × 4.9152 MHz / 3.5795 MHz≈13175 bps Therefore, when it is determined in S5 that the reply data transmitted from the IC card 3 is invalid, or the transmission / reception was not performed normally. In this case, set the communication speed to 1317 in S8.
Change to 5 bps.

Next, the processing of the second embodiment executed by the control circuit 6 will be described. FIG. 7 is a flowchart of the second embodiment of the processing executed by the control circuit 6. In addition, S in FIG.
Since 11 to S14 are the same processes as S1 to S4 of FIG. 5 described above, description thereof will be omitted.

In step S15, the contents of the reply data read from the card are analyzed to determine whether the card inserted in the device 1 is a valid IC card 3. When it is determined in S15 that the IC card 3 is valid, the process proceeds to S16, and the communication speed corresponding to the operation clock of the IC card 3 is calculated. Therefore, when the 4.9152 MHz IC card 3 is inserted into the device 1, the communication speed 6993 bps is calculated as described above.

Then, in the next step S17, since the operation clock of the IC card 3 is 4.9152 MHz instead of the specified value 3.5795 MHz from the reply data transmitted from the IC card 3, the above calculation is performed to specify the communication speed. Value 9600
Change from bps to 6993 bps.

After that, in S18, communication with the IC card 3 is performed and the transmission data is stored in the EEPROM 18 of the IC card 3. Alternatively, the data stored in the EEPROM 18 is read. When the communication with the IC card 3 is completed, the process proceeds to S19, and the IC card 3 is inserted into the card insertion ports 4, 5
Then, the series of processes is completed.

However, if it is determined in S15 that the card inserted in the device 1 is not a valid IC card 3, the process proceeds to S20 without communicating with the card and the IC card 3 is inserted into the card insertion slot. Ejection (discharging) from 4 and 5 completes the series of processes.

When the specified value of the operation clock set in the control circuit 6 is 4.9152 MHz, 3.5.
When the 795 MHz IC card is inserted, the communication speed is calculated as follows in S16. Communication speed = 9600 bps × 4.9152 MHz / 3.5795 MHz≈13175 bps Then, from the reply data transmitted from the IC card 3, I
When it is determined that the operation clock of the C card 3 is 3.5795 MHz, the communication speed is 13175 bp in S17.
Set to s.

Further, in the above-mentioned embodiment, the configuration in which the communication speed is changed in order to handle a plurality of types of IC cards having different operation clocks has been described, but the present invention is not limited to this, and one type of IC is used.
When using only the card, it is possible to improve communication efficiency by supplying a clock faster than the operation clock and intentionally increasing the communication speed.

In the above embodiment, when the IC card 3 is inserted, the IC can read or write data.
Although the card reading / writing device 1 has been described as an example, the present invention is not limited to this, and for example, an IC card reading device that only reads data when the IC card 3 is inserted,
Alternatively, it can be applied to an IC card writing device that only writes data when the IC card 3 is inserted.

[0048]

As described above, according to claim 1, even if a plurality of types of IC cards having different operation clocks are inserted by changing the communication speed, data is read at the communication speed according to the operation clocks. It can be performed.
Therefore, even if a plurality of types of IC cards with different operation clocks are inserted, the communication speed is automatically changed so that the pulse widths match, and data can be read regardless of the operation clocks of the IC cards. The person can effectively use the IC card. Further, the structure can be simplified and the manufacturing cost can be suppressed to be lower than the conventional case where a circuit board is prepared for each operation clock.

According to the second aspect, even if a plurality of types of IC cards having different operation clocks are inserted by changing the communication speed, data can be written at the communication speed according to the operation clocks. . Therefore, even if multiple types of IC cards with different operation clocks are inserted, the communication speed is automatically changed so that the pulse widths match.
Data can be written regardless of the operating clock of the card, and the user can effectively use the IC card. Further, similar to the first aspect, the structure can be simplified and the manufacturing cost can be reduced as compared with the conventional case where the circuit board for each operation clock is prepared.

[Brief description of drawings]

FIG. 1 is a perspective view of an IC card reading / writing device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an IC card reading / writing device.

FIG. 3 is a diagram illustrating a configuration of an IC card.

FIG. 4 is a block diagram of communication clock generation that is processed inside the CPU of the IC card.

FIG. 5 is a flowchart of the processing of the first embodiment executed by the control circuit.

FIG. 6 is a diagram showing a difference in communication pulse width due to a difference in communication speed.

FIG. 7 is a flowchart of the process of the second embodiment executed by the control circuit.

[Explanation of symbols]

 1 IC Card Reading / Writing Device 2 Display 3 IC Card 4,5 Card Insertion Port 6 Control Circuit 9 EEPROM 10 Display Drive Unit 11 Reset Control Unit 12 Power Supply Control Unit 13 Communication Control Unit 14 Clock Control Unit 15 Oscillator 17 CPU 18 EEPROM 25 Communication clock generation unit 26 Communication control unit

Claims (2)

[Claims] 1. An IC card reading device having a card insertion section into which an IC card is inserted and a data reading section for reading data stored in a memory of the IC card inserted into the card insertion section, And a communication speed changing means for maintaining a constant operation clock to the IC card and changing the communication speed based on the reply data, and enabling reading of a plurality of types of IC cards having different operation clocks. IC card reading device. 2. An IC card writing device comprising: a card insertion section into which an IC card is inserted; and a data writing section for storing data in a memory of the IC card inserted into the card insertion section at an operating clock of a predetermined frequency. A communication speed changing means is provided which keeps the operation clock to the IC card constant based on the reply data from the IC card, changes the communication speed, and enables writing to plural kinds of IC cards having different operation clocks. An IC card writing device characterized in that