JPH09331669A - Drive circuit for voltage drive type semiconductor element - Google Patents

Drive circuit for voltage drive type semiconductor element

Info

Publication number
JPH09331669A
JPH09331669A JP8147262A JP14726296A JPH09331669A JP H09331669 A JPH09331669 A JP H09331669A JP 8147262 A JP8147262 A JP 8147262A JP 14726296 A JP14726296 A JP 14726296A JP H09331669 A JPH09331669 A JP H09331669A
Authority
JP
Japan
Prior art keywords
voltage
semiconductor element
failure
circuit
igbt
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8147262A
Other languages
Japanese (ja)
Other versions
JP3661813B2 (en
Inventor
Kiyoaki Sasagawa
清明 笹川
Masato Mochizuki
昌人 望月
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP14726296A priority Critical patent/JP3661813B2/en
Publication of JPH09331669A publication Critical patent/JPH09331669A/en
Application granted granted Critical
Publication of JP3661813B2 publication Critical patent/JP3661813B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To improve reliability by surely protecting a voltage drive type semiconductor element from an overcurrect generated by a short-circuit accident or the like thereof. SOLUTION: After turning on an IGBT(Insulated Gate Bipolar Transistor) 4 as a voltage drive type semiconductor element through a one shot circuit 101, a variable voltage source 103 is actuated for only a specified period of time while gradually decreasing its gate voltage, overcurrect trouble is discriminated by a detection circuit 100. At trouble time, through a timer circuit 102 the variable voltage source 103 is operated and the gate voltage is continuously decreased, and at normal time operation of the variable voltage source 103 is stopped. By returning the gate voltage to a regular value, the semiconductor element can be surely protected from element destruction or the like.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】この発明は、絶縁ゲート形バ
イポーラトランジスタ(以下、IGBTとも略記する)
やMOS形FETなどの電圧駆動形半導体素子の駆動回
路、特にインバータ等の電力変換装置において、短絡事
故時などに生じる過電流から半導体素子を保護する機能
を備えた電圧駆動形半導体素子の駆動回路に関する。
The present invention relates to an insulated gate bipolar transistor (hereinafter abbreviated as IGBT).
Drive circuit of voltage drive type semiconductor element such as MOS FET and MOS type FET, especially drive circuit of voltage drive type semiconductor element having a function of protecting the semiconductor element from an overcurrent generated at the time of a short circuit accident in a power converter such as an inverter Regarding

【0002】[0002]

【従来の技術】以下の説明では、電圧駆動形半導体素子
としてIGBTを用いる場合につき、説明する。電力変
換装置において、運転中の過電流故障の中で素子破壊に
つながる故障として、短絡事故がある。すなわち、短絡
事故が発生すると、IGBT素子には直流定格の10倍
程度の短絡電流が流れる。そこで、この短絡電流を通常
のターンオフ動作で遮断すると、その電流遮断時には、
図7(イ)に破線で示すように、IGBTのコレクタ−
エミッタ間電圧VCEの跳ね上がり電圧VCEP が過大とな
り、この電圧VCEP が素子耐圧以上となって素子破壊に
つながるおそれが生じるわけである。このような過電流
保護方式として、出願人は先に図8に示すような回路を
提案している。これは、短絡事故時に、IGBTのゲー
ト−エミッタ間電圧VGEを、図7(ハ)の実線波形のよ
うに一定の時定数で徐々に減少させるもので、こうする
ことにより、コレクタ電流Icの減少速度が図7(ロ)
のように小さくなり、電流遮断時の電圧VCEの跳ね上が
り電圧VCEP を低減することができる。
2. Description of the Related Art In the following description, the case where an IGBT is used as a voltage-driven semiconductor element will be described. In a power converter, a short-circuit accident is a failure that leads to element destruction among overcurrent failures during operation. That is, when a short circuit accident occurs, a short circuit current of about 10 times the DC rating flows through the IGBT element. Therefore, if this short-circuit current is cut off by a normal turn-off operation, when the current is cut off,
As shown by the broken line in FIG. 7A, the collector of the IGBT
The jump voltage V CEP of the emitter-to-emitter voltage V CE becomes excessive, and this voltage V CEP becomes higher than the breakdown voltage of the device, which may lead to device breakdown. As such an overcurrent protection method, the applicant has previously proposed a circuit as shown in FIG. This is to gradually reduce the gate-emitter voltage V GE of the IGBT at a constant time constant as shown by the solid line waveform in FIG. 7C at the time of a short circuit accident. By doing so, the collector current Ic Figure 7 (b)
It decreases as can reduce the jumping voltage V CEP voltage V CE at the time of current interruption.

【0003】図8についてもう少し具体的に説明する。
同図の符号4は主スイッチング素子としてのIGBT、
5は信号絶縁用フォトカプラ、6,7はそれぞれオンゲ
ート電圧(V1)印加用電圧源,オフゲート電圧(V
2)印加用電圧源を示す。ここで、その通常動作につき
説明する。フォトカプラ5がオンするとトランジスタ8
はオフ,トランジスタ9はオン,トランジスタ10はオ
フとなって、IGBT4のゲート−エミッタ間には抵抗
11を介してオンゲート電圧V1が印加される。オンゲ
ート電圧が与えられるとIGBT4はオンし、そのコレ
クタ−エミッタ間電圧はオン電圧(VCE(ON)と記す)ま
で低下する。したがって、 VZD(13)+VBE(14)>V2+VCE(ON)+VF(15) ZD(13):ツェナーダイオード13のしきい値電圧 VBE(14):トランジスタ14のベースエミッタ間電圧
(VBE) VF(15) :ダイオード15の順方向電圧 の関係が成立するように部品を予め選定しておくことに
より、IGBT4のオン状態ではトランジスタ14をオ
フにすることができる。
A more specific description will be given with reference to FIG.
Reference numeral 4 in the figure is an IGBT as a main switching element,
Reference numeral 5 is a signal insulating photocoupler, 6 and 7 are a voltage source for applying an on-gate voltage (V1), and an off-gate voltage (V
2) Indicates a voltage source for application. Here, the normal operation will be described. When the photo coupler 5 turns on, the transistor 8
Is off, the transistor 9 is on, and the transistor 10 is off, so that the on-gate voltage V1 is applied between the gate and the emitter of the IGBT 4 through the resistor 11. When the on-gate voltage is applied, the IGBT 4 turns on, and its collector-emitter voltage drops to the on-voltage (referred to as V CE (ON)) . Therefore, V ZD (13) + V BE (14) > V2 + V CE (ON) + VF (15) V ZD (13) : Zener diode 13 threshold voltage V BE (14) : Transistor 14 base-emitter voltage (V BE ) VF (15) : By selecting components in advance so that the forward voltage relationship of the diode 15 is established, the transistor 14 can be turned off when the IGBT 4 is on.

【0004】次に、フォトカプラ5がオフになるとトラ
ンジスタ8がオンし、トランジスタ9がオフ,トランジ
スタ10がオンとなって、IGBT4のゲート−エミッ
タ間には抵抗11を介してオフゲート電圧V2が印加さ
れIGBT4はオフとなる。さて、IGBT4のオン期
間中に短絡事故が発生した場合には、そのコレクタ−エ
ミッタ間電圧の増加に伴い、 VZD(13)+VBE(14)<V2+VCE(ON)+VF(15) となり、トランジスタ14が導通する。これにより、コ
ンデンサ20の電荷は抵抗18(R2)を介して放電さ
れる。このとき、R1,R2≧R3と選定しておくこと
により、コンデンサ20の両端電圧とV2との差の電圧
がダイオード21およびトランジスタ10を介して、I
GBT4のゲート−エミッタ間に印加される。この電圧
は、時間の経過とともに徐々に減少する。IGBT4に
流れる短絡電流は、ゲート−エミッタ間に印加される電
圧に依存することから、ゲート−エミッタ間電圧の減少
に対応して、短絡電流も減少する。したがって、過電流
をしゃ断する際の電流の減少率(−di/dt)を小さ
な値に抑制できる。
Next, when the photocoupler 5 is turned off, the transistor 8 is turned on, the transistor 9 is turned off, the transistor 10 is turned on, and the off-gate voltage V2 is applied between the gate and the emitter of the IGBT 4 via the resistor 11. Then, the IGBT 4 is turned off. Now, if a short circuit accident occurs during the ON period of the IGBT4, V ZD (13) + V BE (14) <V2 + V CE (ON) + VF (15) due to the increase in the collector-emitter voltage. , The transistor 14 becomes conductive. As a result, the electric charge of the capacitor 20 is discharged through the resistor 18 (R2). At this time, by selecting R1 and R2 ≧ R3 in advance, the voltage difference between the voltage across the capacitor 20 and V2 will be I through the diode 21 and the transistor 10.
It is applied between the gate and the emitter of the GBT 4. This voltage gradually decreases over time. Since the short-circuit current flowing through the IGBT 4 depends on the voltage applied between the gate and the emitter, the short-circuit current also decreases corresponding to the decrease in the gate-emitter voltage. Therefore, the reduction rate (-di / dt) of the current when shutting off the overcurrent can be suppressed to a small value.

【0005】[0005]

【発明が解決しようとする課題】IGBTインバータの
短絡事故では、その短絡経路にインダクタンスLsがあ
り、このインダクタンスLsにより短絡電流が抑制され
る場合がある。図9(イ)はインダクタンスLsがある
場合の短絡回路であり、同(ロ)にその動作波形を示
す。すなわち、IGBTがオンすると短絡現象が発生
し、そのコレクタ電流Icは電源電圧Edと、インダク
タンスLsとによって決まる電流増加率(di/dt=
Ed/Ls・t)で増加し、IGBT素子の流し得る最
大電流値で増加が止まる(図9(ロ)のt=t1参
照)。次に、コレクタ電流Icが一定値(Icp)にな
ると、IGBTのコレクタ−エミッタ間電圧VCEが増加
し、その値はインダクタンスLsに蓄えられたエネルギ
ーによって、電源電圧Ed+ΔVになる(図9(ロ)の
t=t1以降)。ただし、ΔVは、スナバコンデンサ7
03の容量をC1として、 ΔV=√(Ls/C1)・Icp と表わされる。
In a short circuit accident of the IGBT inverter, there is an inductance Ls in the short circuit path, and the short circuit current may be suppressed by the inductance Ls. FIG. 9A shows a short circuit when there is an inductance Ls, and FIG. 9B shows its operation waveform. That is, when the IGBT is turned on, a short-circuit phenomenon occurs, and the collector current Ic of the IGBT increases by a current increase rate (di / dt = distance) determined by the power supply voltage Ed and the inductance Ls.
Ed / Ls · t), and the increase stops at the maximum current value that the IGBT element can flow (see t = t1 in FIG. 9B). Next, when the collector current Ic reaches a constant value (Icp), the collector-emitter voltage V CE of the IGBT increases, and its value becomes the power supply voltage Ed + ΔV due to the energy stored in the inductance Ls (see FIG. ) T = t1 or later). However, ΔV is the snubber capacitor 7
When the capacity of 03 is C1, ΔV = √ (Ls / C1) · Icp.

【0006】上記のような短絡事故では、下記のように
従来の短絡保護方式が有効に働かず素子破壊につなが
る、という問題がある。 (1)従来の短絡保護方式では、VCEの電圧値によって
過電流を検知するようにしているため、コレクタ電流I
cが最大電流値になってから(図9(ロ)のt=t2参
照)、保護機能が働く。保護作用によってコレクタ電流
Icが減衰すると、減衰した電流は図9(イ)のスナバ
回路700に流れ込み、スナバ電圧は増加する。スナバ
電圧はVCEと等しいため、図9(ロ)に示すt=t2時
点におけるVCEは電源電圧Ed以上に過充電されてお
り、保護作用によってさらに充電され、素子耐圧を越え
て素子破壊される可能性がある。 (2)上記過充電による素子破壊を防ぐには、スナバコ
ンデンサ703の容量C1を大きくすれば良いが、そう
するとスナバ回路が大型化し、コストアップになる。 (3)VCE電圧値が過電流の検知レベルに達しない期間
(図9(ロ)のt=t1以前)に通常オフ信号が入り、
大電流(通常過電流レベル以上)を通常遮断したような
場合、素子のいわゆる安全動作領域(ASO)逸脱によ
る素子破壊の可能性がある。したがって、この発明の課
題は、電圧駆動形半導体素子の短絡事故などで生じた過
電流から、確実に素子の保護を図ることにある。
In the above-mentioned short-circuit accident, there is a problem that the conventional short-circuit protection system does not work effectively as described below, leading to element destruction. (1) In the conventional short-circuit protection method, since the overcurrent is detected by the voltage value of V CE , the collector current I
After c reaches the maximum current value (see t = t2 in FIG. 9B), the protection function operates. When the collector current Ic is attenuated by the protection action, the attenuated current flows into the snubber circuit 700 of FIG. 9A, and the snubber voltage increases. Since the snubber voltage is equal to V CE, V CE at t = t2 point shown in FIG. 9 (b) is overcharged or the power supply voltage Ed, is further charged by the protective action, are device destruction beyond the breakdown voltage There is a possibility. (2) The capacitance C1 of the snubber capacitor 703 may be increased in order to prevent the element breakdown due to the above-mentioned overcharge, but if this is done, the snubber circuit becomes large and the cost increases. (3) The normal off signal is input during the period when the V CE voltage value does not reach the overcurrent detection level (before t = t1 in FIG. 9B),
When a large current (usually overcurrent level or higher) is normally cut off, there is a possibility that the device may be destroyed due to deviation from the so-called safe operating area (ASO) of the device. Therefore, an object of the present invention is to surely protect an element from an overcurrent caused by a short circuit accident of a voltage-driven semiconductor element.

【0007】[0007]

【課題を解決するための手段】このような課題を解決す
るため、この発明では、IGBTのターンオン後にゲー
ト電圧を減少させる保護動作を行ない、その一定期間後
に故障の有無を判断し、故障と判断したときは保護動作
を継続させ、正常と判断したときは保護動作を止めて、
正規のゲート電圧値に戻すようにしている。すなわち、
短絡状態のIGBT素子が流せる電流は、図10に示す
出力特性によって決まる。出力特性は飽和領域と活性領
域に区分けされ、短絡状態は活性領域となる。この活性
領域は図示のように、コレクタ−エミッタ間電圧を変化
させてもコレクタ電流Icの変化は小さいが、ゲート電
圧値VGEの変化によってコレクタ電流Icが大きく変化
する領域である。
In order to solve such a problem, according to the present invention, a protection operation for reducing the gate voltage is performed after the turn-on of the IGBT, and after a certain period of time, it is judged whether or not there is a failure, and it is judged as a failure. When it is normal, the protection operation is continued, and when it is judged to be normal, the protection operation is stopped,
It is designed to restore the normal gate voltage value. That is,
The current that can flow in the short-circuited IGBT element is determined by the output characteristics shown in FIG. The output characteristic is divided into a saturated region and an active region, and a short circuit state becomes the active region. As shown in the figure, this active region is a region in which the collector current Ic changes greatly even if the collector-emitter voltage is changed, but the collector current Ic changes greatly due to the change in the gate voltage value V GE .

【0008】そこで、IGBTのターンオン後に保護動
作を働かせて、ゲート電圧を減少させる。IGBTが短
絡状態であれば、ゲート電圧値が正規の電圧値よりも低
いため、素子に流れる短絡電流は正規のゲート電圧値で
決まる最大電圧値まで増加されずに低い電流値に抑制さ
れる。短絡電流の増加が止まるとコレクタ−エミッタ間
電圧が増加し、IGBTは活性領域に入る。つまり、ゲ
ート電圧値を減少させれば、短絡電流値の低い値で強制
的に活性領域に入れることができる。この状態で、故障
判別させて保護動作を継続させれば、短絡電流値を抑制
して過電流保護機能を有効に生かすことができる。IG
BTが短絡状態でなければ、ゲート電圧を減少させても
コレクタ−エミッタ間電圧の増加がないため、故障判別
させて保護動作を中止し、ゲート電圧を正規の電圧値に
戻せば、通常の動作になる。
Therefore, after the IGBT is turned on, the protection operation is activated to reduce the gate voltage. When the IGBT is in the short-circuited state, the gate voltage value is lower than the regular voltage value, so that the short-circuit current flowing through the element is suppressed to a low current value without being increased to the maximum voltage value determined by the regular gate voltage value. When the increase in short-circuit current stops, the collector-emitter voltage increases and the IGBT enters the active region. That is, if the gate voltage value is reduced, it is possible to forcibly enter the active region at a low short circuit current value. In this state, if the failure is determined and the protection operation is continued, the short-circuit current value can be suppressed and the overcurrent protection function can be effectively used. IG
If the BT is not in a short-circuited state, the collector-emitter voltage does not increase even if the gate voltage is decreased. Therefore, if the failure is identified, the protection operation is stopped, and the gate voltage is returned to the normal voltage value, the normal operation is performed. become.

【0009】[0009]

【発明の実施の形態】図1はこの発明の第1の実施の形
態を示す構成図である。図8と比較すれば明らかなよう
に、この例は可変電圧源103と素子電圧を監視して故
障を検出する故障検知回路100とを分離し、その間に
トランジスタ10のオフ信号によって一定の期間可変電
圧源103を動作させるワンショット回路101と、素
子電圧を監視して故障を検出する故障検知回路100の
出力信号を一定期間遅延させるタイマー回路102を付
加した点が特徴である。
1 is a block diagram showing a first embodiment of the present invention. As is clear from comparison with FIG. 8, in this example, the variable voltage source 103 and the failure detection circuit 100 that monitors the element voltage to detect a failure are separated, and in the meantime, the off signal of the transistor 10 changes the voltage for a certain period. A feature is that a one-shot circuit 101 for operating the voltage source 103 and a timer circuit 102 for delaying an output signal of the failure detection circuit 100 for monitoring a device voltage to detect a failure for a certain period are added.

【0010】図1の動作について、図2を参照して説明
する。まず、ターンオン動作から説明する。いま、フォ
トカプラ5がオンするとトランジスタ8がオフする(図
2のt=t0参照)。その結果、トランジスタ9がオン
し、トランジスタ10がオフとなって、IGBT4のゲ
ート−エミッタ間には抵抗11を介してオンゲート電圧
V1が印加され、IGBT4はターンオンする。IGB
T4はターンオン後のt=t1の時点で、トランジスタ
10のオフによってワンショット回路101が動作し、
可変電圧源103のトランジスタ14を動作させる。ト
ランジスタ14がオンすると、コンデンサ20の電荷は
抵抗18(R2)を介して放電され、コンデンサ20の
両端の電圧とV2との差の電圧がダイオード21および
トランジスタ10を介して、IGBT4のゲート−エミ
ッタ間に印加される。すなわち、IGBT4のゲート電
圧VGEは、時間の経過とともに徐々に減少することにな
る。このゲート電圧VGEの低下は、時刻t=t2まで続
く。
The operation of FIG. 1 will be described with reference to FIG. First, the turn-on operation will be described. Now, when the photocoupler 5 is turned on, the transistor 8 is turned off (see t = t0 in FIG. 2). As a result, the transistor 9 is turned on, the transistor 10 is turned off, the on-gate voltage V1 is applied between the gate and emitter of the IGBT 4 via the resistor 11, and the IGBT 4 is turned on. IGB
In T4, at the time of t = t1 after turn-on, the one-shot circuit 101 operates by turning off the transistor 10,
The transistor 14 of the variable voltage source 103 is operated. When the transistor 14 is turned on, the electric charge of the capacitor 20 is discharged through the resistor 18 (R2), and the voltage difference between the voltage across the capacitor 20 and V2 is passed through the diode 21 and the transistor 10 and the gate-emitter of the IGBT 4 is discharged. Applied between. That is, the gate voltage V GE of the IGBT 4 will gradually decrease with the passage of time. This decrease in gate voltage V GE continues until time t = t2.

【0011】トランジスタ10のオフ信号が入力された
時点で、素子電圧を監視して故障を検出する故障検知回
路100の出力側に設けられたタイマー回路102が動
作し、そのタイマー時間後のt=t2時点で故障判別が
行なわれる。故障判別の関係式は下記のようになる。 正常:VZD(50)+VBE(52)>V2+VCE(ON)+VF(15) … 異常:VZD(50)+VBE(52)<V2+VCE(ON)+VF(15) … そして、t=t2時点で、故障判別結果が正常(上記
式の関係を満たす場合)であれば、ゲート電圧VGEの低
下を止め、正規のゲート電圧値V1に戻す。この場合の
IGBT4のコレクタ−エミッタ間電圧VCEと、コレク
タ電流Ic波形を図2(ホ)に示す。
When the OFF signal of the transistor 10 is input, the timer circuit 102 provided on the output side of the failure detection circuit 100 for monitoring the element voltage and detecting the failure operates, and t = after the timer time. Failure determination is performed at time t2. The relational expression for failure determination is as follows. Normal: V ZD (50) + V BE (52) > V2 + V CE (ON) + V F (15) ... Abnormal: V ZD (50) + V BE (52) <V2 + V CE (ON) + V F (15) ... And At t = t2, if the failure determination result is normal (when the relationship of the above equation is satisfied), the reduction of the gate voltage V GE is stopped and the normal gate voltage value V1 is restored. The collector-emitter voltage V CE of the IGBT 4 and the collector current Ic waveform in this case are shown in FIG.

【0012】これに対し、故障判別結果が異常(故障:
上記式の関係を満たす場合)の場合は、ゲート電圧V
GEの低下を継続させる。この場合のIGBT4のコレク
タ−エミッタ間電圧VCEと、コレクタ電流Ic波形を図
2(ヘ)に示す。図2(ニ)にも示すように、時刻t=
t2以降もゲート電圧VGEが低下するため、コレクタ電
流Icが図2(ヘ)のように抑制されることになる。I
GBT4はコレクタ電流が流れなくなると、コレクタ−
エミッタ間電圧が増加する。すなわち、素子の最大電流
値(正規のゲート電圧値VGE=V1印加時)よりも低い
電流値で、活性領域に入るわけである。時刻t=t2で
故障判別し、さらにゲート電圧VGEの低下を継続させる
ことで、安全にIGBT4をオフすることができる。
On the other hand, the failure determination result is abnormal (failure:
In the case of satisfying the relationship of the above formula), the gate voltage V
Continue to lower GE . FIG. 2F shows the collector-emitter voltage V CE of the IGBT 4 and the collector current Ic waveform in this case. As shown in FIG. 2D, time t =
Since the gate voltage V GE also decreases after t2, the collector current Ic is suppressed as shown in FIG. I
When the collector current stops flowing in GBT4, the collector-
The voltage between the emitters increases. That is, a current value lower than the maximum current value of the element (when the normal gate voltage value V GE = V1 is applied) enters the active region. By determining the failure at time t = t2 and continuing the decrease of the gate voltage V GE , the IGBT 4 can be safely turned off.

【0013】図3はこの発明の第2の実施形態を示す回
路図である。同図からも明らかなように、図1との相違
点はゲート電圧VGEを低下させる時定数の異なる可変電
圧源70,80を設けた点にある。図3の動作につい
て、図4を参照して説明する。IGBT4がターンオン
した後、ワンショット回路101が動作すると可変電圧
源70のトランジスタ71がオンする。可変電圧源70
の放電時定数は可変電圧源80よりも小さく、可変電圧
源80よりも速くゲート電圧を低下させる。短絡故障時
には、ゲート電圧を急峻に下げられるため、短絡電流を
図1の例よりも低減できる効果がある。
FIG. 3 is a circuit diagram showing a second embodiment of the present invention. As is apparent from the figure, the difference from FIG. 1 is that variable voltage sources 70 and 80 having different time constants for lowering the gate voltage V GE are provided. The operation of FIG. 3 will be described with reference to FIG. When the one-shot circuit 101 operates after the IGBT 4 is turned on, the transistor 71 of the variable voltage source 70 is turned on. Variable voltage source 70
Has a discharge time constant smaller than that of the variable voltage source 80, and lowers the gate voltage faster than the variable voltage source 80. At the time of a short circuit failure, the gate voltage can be sharply lowered, so that there is an effect that the short circuit current can be reduced as compared with the example of FIG.

【0014】タイマー回路102のタイマー時間後の時
刻t=t2で、故障判別が行なわれるとともに、もう1
つの可変電圧源80のトランジスタ81がオンし、さら
にゲート電圧VGEの低下を継続させる。可変電圧源80
の時定数は大きく、可変電圧源70よりもゆっくりとゲ
ート電圧VGEを低下させる。ゲート電圧VGEが時間の経
過とともに徐々に減少することで、コレクタ電流Icの
変化率が低くなって図9(イ)に示すようなスナバ回路
に流れ込む電流が少なくなるため、スナバ電圧が増加し
なくなり、図1の例よりも安全にIGBT4をオフする
ことができる利点が得られる。
At time t = t2 after the timer time of the timer circuit 102, a failure determination is made and another
The transistors 81 of the two variable voltage sources 80 are turned on, and the gate voltage V GE is further reduced. Variable voltage source 80
Has a large time constant, and lowers the gate voltage V GE more slowly than the variable voltage source 70. Since the gate voltage V GE gradually decreases with the lapse of time, the rate of change of the collector current Ic becomes low and the current flowing into the snubber circuit as shown in FIG. 9A becomes small, so that the snubber voltage increases. The advantage is that the IGBT 4 can be turned off more safely than in the example of FIG.

【0015】図5はこの発明の第3の実施形態を示す回
路図である。図1との相違点は、IGBT4のコレクタ
−エミッタ間電圧を抵抗R100 ,R101 によって分圧し
てIGBT4のゲート駆動回路の電圧検出部200に引
き込み、その検出値によりIGBT4の状態監視を行な
うようにした点にある。この場合のIGBT4の状態監
視は、コレクタ−エミッタ間電圧VCEの抵抗分圧値R
100 /R101 ・VCN(この値は、ゲート駆動回路のグラ
ンドラインを基準にしている。)と、故障設定値(V
ZD(201) +VBE(203) )との比較により行なわれる。す
なわち、 R100 /R101 ・VCN>VZD(201) +VBE(203) … R100 /R101 ・VCN<VZD(201) +VBE(203) … の判定を行ない、式が成立するときは電圧検出部20
0のトランジスタ203がオンし、反転アンプを介して
ハイ(H)レベルの信号を出力する。また、式が成立
するときはトランジスタ203がオフし、反転アンプを
介してロー(L)レベルの信号を出力する。
FIG. 5 is a circuit diagram showing a third embodiment of the present invention. The difference from FIG. 1 is that the collector-emitter voltage of the IGBT 4 is divided by the resistors R 100 and R 101 and drawn into the voltage detection unit 200 of the gate drive circuit of the IGBT 4, and the state of the IGBT 4 is monitored by the detected value. It is in the point that I made it. In this case, the state of the IGBT 4 is monitored by the resistance division value R of the collector-emitter voltage V CE.
100 / R 101 · V CN (This value is based on the ground line of the gate drive circuit) and the failure set value (V
ZD (201) + V BE (203) ). That is, R 100 / R 101 · V CN > V ZD (201) + V BE (203) ... R 100 / R 101 · V CN <V ZD (201) + V BE (203) ... When doing, the voltage detection unit 20
The 0 transistor 203 is turned on and outputs a high (H) level signal through the inverting amplifier. When the expression is satisfied, the transistor 203 is turned off and a low (L) level signal is output through the inverting amplifier.

【0016】その出力とトランジスタ8の出力との排他
的論理和(EXOR:104)をとることにより、表1
の関係から故障か否かが判別できる。故障(1)は、オ
ン信号が入っているのにコレクタ−エミッタ間電圧が低
下しないため図1の場合と同じ判別となり、図1の場合
と同様の保護動作が行なわれる。故障(2)の判別は次
の通りである。つまり、IGBT4がオフの場合、その
コレクタ−エミッタ間電圧には主回路電圧が印加され
る。これに対し、オフ信号を与えても、IGBT4のコ
レクタ−エミッタ間電圧に主回路電圧が出なければ素子
故障である。そこで、この条件によりIGBTの状態監
視を行ない、その情報を外部の制御装置へ出力する。
By taking the exclusive OR (EXOR: 104) of the output and the output of the transistor 8, Table 1
It is possible to determine whether or not there is a failure from the relationship. In the failure (1), since the collector-emitter voltage does not drop even though the ON signal is input, the same judgment as in the case of FIG. 1 is made, and the same protection operation as in the case of FIG. 1 is performed. The determination of the failure (2) is as follows. That is, when the IGBT 4 is off, the main circuit voltage is applied to its collector-emitter voltage. On the other hand, if the main circuit voltage does not appear in the collector-emitter voltage of the IGBT 4 even if the OFF signal is given, it is an element failure. Therefore, the state of the IGBT is monitored under this condition, and the information is output to an external control device.

【表1】 [Table 1]

【0017】図6はこの発明の第4の実施形態を示す回
路図である。これは、図5の状態監視情報を受け、故障
信号が入力された場合は、その信号により短絡保護動作
を行なうものである。また、IGBT素子がオフ時の場
合にはオン信号を受け付けず、オフ状態のままにするイ
ンターロック部300を設置している。このように、直
列接続されたIGBT同志の状態を監視することで、短
絡保護動作を安全かつ瞬時に行なうようにする。さら
に、一方の素子がオフの場合、対向側の素子が故障して
いる場合には、健全な素子にはオン信号を受け付けず、
オフ状態のままにするなどすれば、短絡状態を未然に防
ぐことができる。
FIG. 6 is a circuit diagram showing a fourth embodiment of the present invention. This is to receive the state monitoring information of FIG. 5 and, when a failure signal is input, perform a short-circuit protection operation by that signal. Further, when the IGBT element is in the off state, the interlock part 300 is provided which does not receive the on signal and keeps the off state. In this way, by monitoring the states of IGBTs connected in series, the short-circuit protection operation can be performed safely and instantly. Furthermore, when one element is off, when the element on the opposite side has failed, a sound element does not receive the on signal,
The short-circuit state can be prevented by leaving it in the off state.

【0018】[0018]

【発明の効果】この発明によれば、IGBTのターンオ
ン後にゲート電圧を減少させる保護動作を実行し、その
一定期間後に故障の有無を判断させ、故障と判断したと
きは保護動作を継続させ、正常と判断したときは保護動
作を止めて、正規のゲート電圧値に戻すことで、電圧駆
動形半導体素子の短絡故障などで生じる過電流から確実
に半導体素子を保護することが可能になるという利点が
得られる。
According to the present invention, after the IGBT is turned on, the protection operation for reducing the gate voltage is executed, and after a certain period of time, it is judged whether or not there is a failure. When the failure is judged, the protection operation is continued and the normal operation is performed. If it is determined that the protection operation is stopped and the gate voltage value is returned to the normal value, it is possible to reliably protect the semiconductor element from an overcurrent generated due to a short circuit failure of the voltage-driven semiconductor element. can get.

【図面の簡単な説明】[Brief description of drawings]

【図1】この発明の第1の実施の形態を示す回路図であ
る。
FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

【図2】図1の動作を説明するための波形図である。FIG. 2 is a waveform chart for explaining the operation of FIG.

【図3】この発明の第2の実施の形態を示す回路図であ
る。
FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

【図4】図3の動作を説明するための波形図である。FIG. 4 is a waveform diagram for explaining the operation of FIG.

【図5】この発明の第3の実施の形態を示す回路図であ
る。
FIG. 5 is a circuit diagram showing a third embodiment of the present invention.

【図6】この発明の第4の実施の形態を示す構成図であ
る。
FIG. 6 is a configuration diagram showing a fourth embodiment of the present invention.

【図7】従来例を説明するための波形図である。FIG. 7 is a waveform diagram for explaining a conventional example.

【図8】従来例を示す回路図である。FIG. 8 is a circuit diagram showing a conventional example.

【図9】短絡故障時の模擬回路とその電圧,電流波形の
説明図である。
FIG. 9 is an explanatory diagram of a simulated circuit and its voltage and current waveforms at the time of a short circuit failure.

【図10】IGBTの出力特性例を示す特性図である。FIG. 10 is a characteristic diagram showing an output characteristic example of an IGBT.

【符号の説明】[Explanation of symbols]

1,3,11,12,17,18,19,22,51,
53,54,55,72,82,202,204,R
100 ,R101 …抵抗、2,13,50,201…ツェナ
ーダイオード、15,21…ダイオード、4,41,4
2…IGBT、5…フォトカプラ、6,7…電源、8,
9,10,14,23,52,71,81,203…ト
ランジスタ、20…コンデンサ、24…加算点、70,
80,103…可変電圧源、100…故障検知回路、1
01…ワンショット回路、102…タイマー回路、10
4…排他的論理和(EXOR)、200…電圧検出部、
300…インターロック部。
1, 3, 11, 12, 17, 18, 19, 22, 51,
53, 54, 55, 72, 82, 202, 204, R
100 , R 101 ... Resistance, 2, 13, 50, 201 ... Zener diode, 15, 21 ... Diode, 4, 41, 4
2 ... IGBT, 5 ... Photo coupler, 6, 7 ... Power supply, 8,
9, 10, 14, 23, 52, 71, 81, 203 ... Transistor, 20 ... Capacitor, 24 ... Addition point, 70,
80, 103 ... Variable voltage source, 100 ... Failure detection circuit, 1
01 ... One-shot circuit, 102 ... Timer circuit, 10
4 ... Exclusive OR (EXOR), 200 ... Voltage detection unit,
300 ... Interlock part.

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 信号絶縁器を有し1対のトランジスタを
出力段として用いてなる駆動部と、電圧駆動形半導体素
子の状態を監視する状態監視部と、その監視電圧が所定
値を越えたとき過電流故障として判断する判断手段と、
前記半導体素子に印加される電圧を徐々に降下させる可
変電圧源を持つ過電流保護部とからなる電圧駆動形半導
体素子の駆動回路において、 前記半導体素子がターンオンしたのちの一定期間だけ前
記可変電圧源を動作させ、半導体素子に印加されている
電圧を徐々に降下させて過電流故障の判断を行ない、故
障と判断したときは半導体素子に印加している電圧を徐
々に降下させる一方、正常と判断したときは可変電圧源
の動作を停止させて、半導体素子に印加されている電圧
を正規の電圧に戻すことを特徴とする電圧駆動形半導体
素子の駆動回路。
1. A drive unit having a signal isolator and using a pair of transistors as an output stage, a state monitor unit for monitoring the state of a voltage-driven semiconductor device, and the monitor voltage exceeds a predetermined value. And a determination means for determining an overcurrent failure,
A drive circuit for a voltage-driven semiconductor device comprising an overcurrent protection unit having a variable voltage source that gradually drops the voltage applied to the semiconductor device, wherein the variable voltage source is provided for a certain period after the semiconductor device is turned on. To gradually decrease the voltage applied to the semiconductor element and judge the overcurrent failure.When it is judged as a failure, the voltage applied to the semiconductor element is gradually decreased, but it is judged to be normal. In this case, the drive circuit for the voltage-driven semiconductor element is characterized in that the operation of the variable voltage source is stopped and the voltage applied to the semiconductor element is returned to the normal voltage.
【請求項2】 前記可変電圧源を、前記半導体素子がタ
ーンオンした後の一定期間だけ動作する第1の可変電圧
源と、過電流故障の判別後の故障時に動作する第2の可
変電圧源とに分け、両可変電圧源の時定数を互いに異な
らせることを特徴とする請求項1に記載の電圧駆動形半
導体素子の駆動回路。
2. A first variable voltage source that operates the variable voltage source only for a certain period after the semiconductor element is turned on, and a second variable voltage source that operates when a failure occurs after an overcurrent failure is determined. 2. The drive circuit for a voltage-driven semiconductor device according to claim 1, wherein the time constants of both variable voltage sources are different from each other.
【請求項3】 前記状態監視部を、前記半導体素子の電
圧を抵抗分圧によって検出し、その検出値と入力信号と
の排他的論理和をとって半導体素子の状態を監視する構
成とすることを特徴とする請求項1に記載の電圧駆動形
半導体素子の駆動回路。
3. The state monitoring unit is configured to detect the voltage of the semiconductor element by resistance voltage division, and obtain the exclusive OR of the detected value and an input signal to monitor the state of the semiconductor element. The drive circuit for a voltage-driven semiconductor element according to claim 1,
【請求項4】 前記状態監視部の出力を、電力変換装置
を構成する1対の半導体素子の対向する駆動回路に互い
に入力し、故障信号が入力されたときはその信号によっ
て短絡保護動作をさせるとともに、一方の半導体素子が
故障している場合は、オン信号を受け付けずにオフ状態
のままとすることを特徴とする請求項3に記載の電圧駆
動形半導体素子の駆動回路。
4. The output of the state monitoring unit is mutually input to drive circuits facing each other of a pair of semiconductor elements constituting the power conversion device, and when a failure signal is input, a short circuit protection operation is performed by the signal. 5. The drive circuit for a voltage-driven semiconductor device according to claim 3, wherein when one of the semiconductor devices has a failure, the semiconductor device remains in the off state without receiving the on signal.
JP14726296A 1996-06-10 1996-06-10 Drive circuit for voltage-driven semiconductor element Expired - Fee Related JP3661813B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14726296A JP3661813B2 (en) 1996-06-10 1996-06-10 Drive circuit for voltage-driven semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14726296A JP3661813B2 (en) 1996-06-10 1996-06-10 Drive circuit for voltage-driven semiconductor element

Publications (2)

Publication Number Publication Date
JPH09331669A true JPH09331669A (en) 1997-12-22
JP3661813B2 JP3661813B2 (en) 2005-06-22

Family

ID=15426263

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP3661813B2 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002300019A (en) * 2001-04-02 2002-10-11 Fuji Electric Co Ltd Drive circuit for power converter
JP2008054481A (en) * 2006-08-28 2008-03-06 Tokyo Electric Power Co Inc:The Inspection arrangement and method of power converter
CN102347603A (en) * 2011-09-21 2012-02-08 深圳市英威腾电气股份有限公司 Drive and protection circuit for IGBT (Insulated Gate Bipolar Transistor)
JP2014079037A (en) * 2012-10-09 2014-05-01 Fuji Electric Co Ltd Gate drive circuit having failure detection circuit for semiconductor switch element
KR20180084892A (en) * 2015-11-20 2018-07-25 젯트에프 프리드리히스하펜 아게 Safe control of consumer devices
US11029365B2 (en) 2016-11-09 2021-06-08 Rohm Co., Ltd. Semiconductor device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002300019A (en) * 2001-04-02 2002-10-11 Fuji Electric Co Ltd Drive circuit for power converter
JP2008054481A (en) * 2006-08-28 2008-03-06 Tokyo Electric Power Co Inc:The Inspection arrangement and method of power converter
CN102347603A (en) * 2011-09-21 2012-02-08 深圳市英威腾电气股份有限公司 Drive and protection circuit for IGBT (Insulated Gate Bipolar Transistor)
JP2014079037A (en) * 2012-10-09 2014-05-01 Fuji Electric Co Ltd Gate drive circuit having failure detection circuit for semiconductor switch element
KR20180084892A (en) * 2015-11-20 2018-07-25 젯트에프 프리드리히스하펜 아게 Safe control of consumer devices
JP2018536353A (en) * 2015-11-20 2018-12-06 ツェットエフ、フリードリッヒスハーフェン、アクチエンゲゼルシャフトZf Friedrichshafen Ag Safety control of consumer devices
US11029365B2 (en) 2016-11-09 2021-06-08 Rohm Co., Ltd. Semiconductor device

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