JPH09326996A - Digital video recorder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain quick reproduction and ease of editing by recording still image video data to a semiconductor memory and using the data for editing a still image with respect to a recording medium. SOLUTION: One frame of a still image or a moving image recorded on a magnetic tape 10 is reproduced and a 2nd changeover switch 16 is used to select it as video data via an error correction circuit 14 and a 3rd switch 51 selects video data D3. A shutter button 5 is operated while observing a monitor screen in this state to write one frame of a displayed still image or moving image to a semiconductor memory 17. In the case of reproducing the still image, the 2nd changeover switch 16 is thrown to the position of the semiconductor memory 17, the still image data written in the semiconductor memory 17 are fed to an image expansion processing circuit 15, which reproduces the still image. The still image video data are recorded in the semiconductor memory 17 in this way and used for editing the still image, then quick reproduction and ease of edit are attained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention records digital video data sent from an image pickup system such as a CCD on a recording medium such as a magnetic tape or reproduces the video data from the recording medium and outputs it to a monitor or the like. The present invention relates to a digital video recorder that

[0002]

2. Description of the Related Art HD (High Definition) Digital VCR
In a digital VTR complying with the DV format standardized by the council, one frame of digital video data of a moving image is recorded over 10 tracks in the case of the NTSC system. Further, in the digital VTR, by pressing the shutter button, it is possible to record the video data of one frame obtained at that time as a still image on the magnetic tape (Magazine "Video α" 1995 November).
(See pages 42-48 of the monthly issue).

In recording a still image, in order to record one frame of video data on a magnetic tape, 10
It is sufficient to provide a track and a recording area for 1/30 seconds,
In consideration of ease of retrieval, prevention of image quality deterioration due to damage to the tape, and the like, the same video data is repeatedly recorded a plurality of times in units of 10 tracks for a predetermined time T (for example, 7 seconds). FIG. 10 shows a state in which a moving image and a still image are mixedly recorded on a magnetic tape, and a plurality of moving image recording areas having an arbitrary length and the predetermined time T are recorded according to the shooting order. A plurality of still image recording areas are formed. Such a magnetic tape is a digital VTR
When reproduced by, the moving image and the still image are reproduced in the order of recording.

[0004]

However, in the conventional digital VTR, when the desired one still image is to be reproduced, the fast forward or rewind operation is performed,
Since it is necessary to search the area in which a desired still image is recorded, the operation is complicated and time-consuming. For example, in the case of a 1-hour tape in DV format, it takes 36 seconds to search from the beginning to the end of the tape, even if fast-forwarding at 100 times speed is performed. In addition, when collecting and recording still images distributed and recorded on a magnetic tape in one place of the magnetic tape or rearranging the order and rerecording, an editing machine becomes indispensable, and editing work is troublesome, There was a problem that it took time.

An object of the present invention is to provide a digital video recorder which can quickly and easily reproduce a desired still picture. Another object of the present invention is to provide a digital video recorder capable of easily performing desired editing when recording a still image on a recording medium without using a special editing machine.

[0006]

A digital video recorder according to the present invention comprises an image pickup system, an image compression system for subjecting a series of image data sent from the image pickup system to image compression processing in frame or field units, and It comprises a data recording system for recording the reproduced video data on a recording medium, a data reproducing system for reproducing the video data from the recording medium, and an image expanding system for performing an image expanding process on the reproduced video data and outputting it. . The digital video recorder according to the present invention has, as its characteristic configuration, a semiconductor memory capable of writing and reading video data in units of frames or fields, and a video of one frame or one field in response to a still image write command. While writing data to semiconductor memory,
A memory control unit for reading out one frame or one field of video data from the semiconductor memory in response to a still image read command, one frame or one field of first video data D1 output from the image compression system, and the semiconductor memory. Second of one frame or one field to be read
Of the image data D2, the first data switching means SW1 to be sent to the data recording system, the second image data D2 read from the semiconductor memory, and the data reproducing system. It is provided with a second data switching means SW2 for selecting one of the third video data D3 output from the above and transmitting it to the image expansion system.

In the above digital video recorder, when recording a moving image, the first data switching means SW1 selects the video data D1 output from the image compression system and sends it to the data recording system. As a result, a series of video data, which is a moving image, is recorded on the recording medium. When a still image recording command is issued during recording of a moving image, the image data of a still image is written in the semiconductor memory in parallel with the recording operation of a series of image data of a moving image. After that, when reproducing the moving image, the second data switching means SW2 selects the video data from the data reproducing system and sends it to the image expanding system. As a result, the video data subjected to the image expansion processing is supplied to a monitor or the like, and a moving image is displayed.

On the other hand, at the time of reproducing a still image, the semiconductor memory is searched. Generally, the access time to the semiconductor memory is about several hundred nanoseconds at the longest, which is much shorter than the access time to the recording medium such as the magnetic tape, and the extremely high speed search is possible. When reproducing a still image, the second data switching means SW2 selects the video data read from the semiconductor memory and sends it to the image expansion system. As a result, a still image is displayed on the monitor.

When a desired one or a plurality of still images among the still images written in the semiconductor memory are to be recorded on the recording medium, the first data switching means SW1 is the video data read from the semiconductor memory. To send it to the data recording system. At this time, by performing a search on the semiconductor memory, it is possible to perform various edits such as continuously recording a plurality of still images at a predetermined location on the recording medium, or rearranging the order and recording.

In the above digital video recorder, image data to be recorded as a moving image on a recording medium is subjected to image compression processing, and then one frame or one field of the image data is recorded as a still image in a semiconductor image. Since it is written in the memory, there is no need to provide an image compression system dedicated to still images. In addition, since the video data for video reproduction reproduced from the recording medium and the video data for still image reproduction read from the semiconductor memory are output to the monitor etc. through the common image expansion system, the still image is reproduced. It is not necessary to provide a dedicated image expansion system.

The digital video recorder of the present invention further has a specific configuration in which the first video data D1 of one frame or one field output from the image compression system and one frame or one field output from the data reproduction system. Of the third video data D3, the third data switching means SW3 which selects one of the video data and sends it to the semiconductor memory is provided.

In the digital video recorder, the video data can be written in the semiconductor memory (17) by selecting the video data of the still picture reproduced from the recording medium by the third data switching means SW3. . Therefore, the still image once recorded on the recording medium can be transferred to the semiconductor memory, and the still image in the semiconductor memory can be transferred to the recording medium again by switching the video data by the first data switching means SW1. I can.
As a result, it is possible to make various edits on the recording medium.

Further, in a specific configuration, the semiconductor memory has a capacity capable of recording video data for a plurality of frames or a plurality of fields. In addition, the memory control means, for a plurality of frames or fields to be written or read, an upper address generation circuit for generating an upper address for specifying a write area or a read area in frame or field units, and 1 It comprises a lower address generation circuit for generating a lower address for specifying a writing position or a reading position of a data unit for a series of video data forming a frame or one field.

In the concrete structure, each time a still image recording command or a still image reproducing command is issued, a higher address is generated and the memory area to be written or read in the semiconductor memory is in units of frames or fields. Specified. Further, when one memory area is specified by one upper address, a series of lower addresses for sequentially writing video data in the memory area or sequentially reading video data from the memory area are generated, A writing position or a reading position of each video data is specified together with the upper address. In this way, the circuit configuration of the memory control means is simplified by defining the writing or reading address of the video data as the upper and lower hierarchical address structures.

[0015]

In the digital video recorder according to the present invention, since the video data of a still image is recorded in the semiconductor memory which can be accessed at high speed, the desired still image can be reproduced quickly and easily. Further, since the semiconductor memory can be used for editing a still image on the recording medium, desired editing can be easily performed without using a special editing machine.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment in which the present invention is applied to a DV format digital VTR will be specifically described below with reference to the drawings. FIG. 1 shows the overall configuration of a digital VTR of the present invention. A signal processing system for recording and reproducing moving images, that is, a CCD image processing circuit (3), an image compression processing circuit (4), an error correction code. Additional circuit (6), modulation processing circuit
The shutter button (5) to be operated when recording a still image to the demodulation processing circuit (13), the error correction circuit (14), and the image decompression processing circuit (15), and the image to be a still image A semiconductor memory (17) for storing data, a memory control signal generation circuit (18) for controlling writing and reading of video data to and from the semiconductor memory (17), and data for the semiconductor memory (17) It is equipped with a memory read / write clock generation circuit (40) which supplies a clock for writing and reading.

Further, three changeover switches (50), (16) and (51) are provided for changing over the image data. The first changeover switch SW1 (50) switches between the video data D1 output from the image compression processing circuit (4) and the video data D2 read from the semiconductor memory (17), and the error correction code addition circuit (6). To supply to. The second changeover switch SW2 (16) switches between the video data D3 output from the error correction circuit (14) and the video data D2 read from the semiconductor memory (17), and the image expansion processing circuit (1
It is for supplying to 5). Third changeover switch S
W3 (51) switches between the video data D1 output from the image compression processing circuit (4) and the video data D3 output from the error correction circuit (14), and supplies it to the semiconductor memory (17). It is a thing.

In the signal recording mode, the light from the subject is condensed on the CCD image pickup device (2) through the optical system (1),
Converted to electrical signals. The electric signal is supplied to the CCD image processing circuit (3), and the luminance signal Y and the color difference signals Pb, P
r is converted to digital video data. The digital video data obtained from the CCD image processing circuit (3) is input to the image compression processing circuit (4) and the amount of information is compressed by DCT (discrete cosine transform). It is supplied to the error correction code addition circuit (6) via the changeover switch (50) and the error correction code is added.
Furthermore, after the video data obtained from the error correction code addition circuit (6) has undergone the necessary modulation processing in the modulation processing circuit (7),
Magnetic tape through recording amplifier (8) and recording head (9)
Recorded in (10).

In the signal reproduction mode, the magnetic tape (10)
The video data recorded in (1) is reproduced by the reproducing head (11), subjected to waveform equalization processing by the equalizer (12), and then demodulated by the demodulation processing circuit (13). The video data obtained from the demodulation processing circuit (13) is subjected to error detection and error correction based on the error correction code in the error correction circuit (14). Video data D3 output from the error correction circuit (14)
The image expansion processing circuit (15) via the changeover switch (16).
Supplied to The image expansion processing circuit (15) performs image expansion processing to obtain the original luminance signal Y and the color difference signals Pb and Pr.
Is converted into digital video data, and these data are output to an external monitor. As a result, a moving image is displayed on the external monitor.

When recording a still image while recording a moving image,
Press the shutter button (5). As a result, the shutter pulse is supplied to the memory control signal generation circuit (18) and the image compression processing circuit (4). The image compression processing circuit (4) creates a frame pulse W according to the input of the shutter pulse and supplies it to the memory control signal generation circuit (18). by this,
The memory control signal generation circuit (18) supplies control signals (memory enable signal and address signal) for writing data to the semiconductor memory (17). As a result, one frame of compressed video data output from the image compression processing circuit (4) is supplied to the semiconductor memory (17) via the third changeover switch (51) and written to the designated address.

Thereafter, when reproducing a still image, one frame of video data is read from the semiconductor memory (17),
The video data D2 is supplied to the image expansion processing circuit (15) through the changeover switch (16). As a result, the luminance signal Y and the color difference signals Pb and Pr for one frame are output to the external monitor and a still image is displayed.

By the way, in the DV format,
Video data for one frame, including VAUX data having information related to video, is 77 bytes x 138 sync blocks x 10 tracks = 1
Since it has a data amount of 06260 bytes, in order to record one still image, an area of 106260 bytes may be secured in the semiconductor memory (17). Therefore, in order to record 10 still images, at least 1.07 MB semiconductor memory (17)
You just need to prepare. Here, when the data write unit is 8 bits and the semiconductor memory (17) capable of addressing every 8 bits is adopted, the address is 106260.
By increasing the unit, the address A of the head data of the N (N ≧ 10) th still image can be expressed by A = (N−1) × 106260, which allows the semiconductor memory (17)
It is possible to control writing and reading of video data to and from.

However, in the above method, it is necessary to individually generate an address for each piece of video data that constitutes 10 still images, which complicates the address generation circuit. Therefore, in this embodiment,
The address method shown in FIG. 5 is adopted. That is, the memory area assigned to one still image is 2 ¹⁷ (= 131072) bytes, and the lower address is configured in units of 17 bits. The lower address is 0 each time the top data of a still image is input.
Is reset to 1 and set to 1 by the clock synchronized with the data
Each is counted up. Further, in order to specify one still image, a 4-bit upper address is constructed, and the upper address represents the number of 16 still images.

As a result, all the still image data have lower addresses 0x00000 to 0x19F13 as shown in FIG.
The memory area of the lower address 0x19F14 to 0xFFFFF written in the data area represented by (hexadecimal display) is a dummy data area and is not used for recording still image data. Therefore, when n is a hexadecimal number (0 to F), the nth still image is stored in the area of the upper address 0xn and the lower address 0x00000 to 0x19F13.

In order to realize the above address method, the memory control signal generating circuit (18) shown in FIG. 1 is replaced by the upper address generating circuit (41) shown in FIG. 2 and the lower address generating circuit (4) shown in FIG.
2) and the memory enable signal generating circuit (43) shown in FIG. The operation of the upper address generation circuit (41) and the lower address generation circuit (42) in the signal recording mode is shown in FIG.

In the upper address generation circuit (41) shown in FIG. 2, when the switch (27) is operated to set the signal recording mode, the switch (27) reads / writes "L" to the selector (25). Supply a select signal. On the other hand, when the signal playback mode is set, the switch (27) turns the selector (25)
The read / write select signal of "H" is supplied to. As a result, the selector (25) is
The 4-bit data of the "0" port to which the upper address counter (19) is connected is selected, and in the signal reproduction mode, the 4-bit data of the "1" port to which the dip switch (26) is connected is selected.

In the signal recording mode, first, the reset button
When (20) is operated, the reset pulse generated thereby is supplied to the D type flip-flop (21) and the upper address counter (19). In response to this, the output of the upper address counter (19), that is, the upper address is 0x0
Is set to At the same time, the output of the D type flip-flop (21) becomes "L", the output of the 4-input NAND gate (23) becomes "H", and the shutter wait state is set.

In this state, when the first shutter is released, the shutter pulse generated thereby is input to the 3-input AND gate (22) via the NOT gate (24).
Here, the output of the D type flip-flop (21) is "L".
Therefore, no shutter pulse is input to the upper address counter (19). Next, at the rising edge of the first shutter pulse, the D-type flip-flop
The output of (21) becomes "H", and the second shutter waiting state is entered.

When the shutter is released for the second time, a shutter pulse is input to the upper address counter (19) and the upper address value is counted up to 0x1. Or later,
By the same operation up to the 16th time, the upper address is 0x
It will be counted up to F.

When the upper address becomes 0xF, 4 inputs N
The output of the AND gate (23) becomes "L", and the acceptance of the 17th and subsequent shutter pulses is rejected. This is because the memory capacity is 16 still images in the present embodiment.
This is because the 17th and subsequent data imports are prohibited.
Therefore, when a larger capacity memory is used, the circuit configuration should be adapted to the capacity. 4 inputs NA at this time
The output (“L”) of the ND gate (23) is input to a memory enable signal generating circuit, which will be described later, as a write enable permission signal.

In the signal recording mode, the lower address generating circuit (42) shown in FIG. 3 has the image compression processing circuit (4).
As an output signal from, a frame pulse W that is "L" during the period in which compressed data is output as shown in FIG. 6 is input in synchronization with the memory write clock. Selector
(30) is the read / write select signal
The frame pulse W of the "0" port is selected. The selected frame pulse W passes through the NOT gate (28) and the D-type flip-flop (31) and the lower address counter (2
Input to the reset terminal of 9). When the frame pulse W is "H", the lower address counter (29) is 0x00.
It has been reset to 000. When the compressed data is output from the image compression processing circuit (4), the frame pulse W becomes "L" and the lower address counter (29) is counted up by the memory write clock.

The memory enable signal generating circuit (43) generates a memory enable signal for permitting data writing to the semiconductor memory (17) in the signal recording mode, and its circuit configuration is shown in FIG. The circuit operation is shown in FIG. The shutter pulse supplied from the shutter button (5) is converted by the monostable multivibrator (36) into a shutter pulse_A which becomes "L" only for one frame pulse period, and then, in the D type flip-flop (32), The shutter pulse_B latched by the frame pulse W and obtained by this is input to the 3-input OR circuit (33).

Since the selector (34) is selected as the "0" port by the read / write select signal, the signal from the 3-input OR circuit (33) is output as the memory write enable signal. This memory write enable signal becomes "L" only during the "L" period of the frame pulse W after the shutter button is operated, and during that period, data writing to the semiconductor memory (17) is permitted. However, for the 17th and subsequent shutter pulses, the signal obtained by latching the write enable permission signal output from the 4-input NAND gate (23) by the D type flip-flop (35) becomes "H". The memory write enable signal input to the 3-input OR circuit (33) becomes "H", and data writing to the semiconductor memory (17) is prohibited. Also, except when writing to the memory, the "H" state is selected by the selector (34) in order to prevent memory writing due to malfunction.

As described above, the memory control signal generation circuit (18)
Data for the semiconductor memory (17) by the address signal and the memory write enable signal generated by the video signal, the video data from the image compression processing circuit (4), and the memory write clock from the memory read / write clock generation circuit (40). Writing is performed. Here, since the data writing in the semiconductor memory (17) does not have any influence on the operation during normal moving image recording, it can be obtained at that time by operating the shutter button (5) even during moving image recording. Video data for one frame can be written in the semiconductor memory (17) as a still image.

In the signal reproduction mode, when reproducing a still image, the changeover switch (16) shown in FIG. 1 is switched to the semiconductor memory (17) side, and the still image data written in the semiconductor memory (17) is stored in the semiconductor memory (17). It is supplied to the image expansion processing circuit (15) to restore a still image. Selection of a still image to be restored is performed by operating the DIP switch (26) shown in FIG. 2 and inputting a still image number corresponding to the desired still image. The still image number is output as a higher address to the semiconductor memory (17) via the selector (25). At this time, the read / write select signal is set to "H" by the switch (27).

In the memory enable signal generating circuit (43) shown in FIG. 4, the read enable generating circuit (38) is
The memory read clock is counted, and as shown in FIG. 8, a signal of "L" is output during the 106260 clock period, and a signal of "H" is output during the 24812 clock period. The output signal is shown in FIG.
It is supplied to the semiconductor memory (17) as a memory read enable signal via the selector (37) shown in FIG. The "L" period of the memory read enable signal is a period required to read one frame of video data from the semiconductor memory (17), and in this period, a lower address is designated in synchronization with the memory read clock. Semiconductor memory
The video data of a specific still image stored in (17) can be sequentially read.

The lower address is generated by the lower address generating circuit (42) shown in FIG. Here, the memory read clock from the memory read / write clock generation circuit (40) is supplied to the lower address counter (29),
The lower address counter (29) is incremented. Further, the memory read enable signal is input to the reset terminal of the lower address counter (29) through the NOT gate (28) and the D type flip-flop (31), so that the memory read enable signal and the lower address as shown in FIG. The timing of is being adjusted.

Further, as shown in FIG. 4, a signal obtained by latching the memory read enable signal by the D type flip-flop (39) is output as a frame pulse R to the image expansion processing circuit (15). As a result, the image expansion processing circuit (15)
Is the semiconductor memory (17) during the “L” period of the frame pulse R.
It is possible to recognize that one frame of data is output from.

The image expansion processing circuit (15) receives the frame pulse R and the compressed video data for one frame from the semiconductor memory (17) and converts the data into the original luminance signal Y and color difference signals Pb, Pr. Restore and output to an external monitor. As a result, a desired still image is displayed on the external monitor.

Next, a circuit operation for performing various edits when recording a still image on the magnetic tape 10 by the digital VTR will be described. According to the digital VTR, one or more still images or moving images are recorded on the magnetic tape (10) in the same manner as the conventional digital VTR,
It is possible to reproduce one frame of a still image or a moving image recorded on the magnetic tape (10) and write the frame as a still image in the semiconductor memory (17).

In this case, the video data D3 from the error correction circuit (14) is selected by the second selector switch (16), and the error correction circuit (1) is selected by the third selector switch (51).
With the video data D3 from 4) selected, operate the shutter button (5) while watching the screen of the monitor. As a result, one frame of a still image or a moving image displayed when the shutter button (5) is operated is written in the semiconductor memory (17). In this way, the still image to be edited is transferred from the magnetic tape (10) to the semiconductor memory (17).

According to the digital VTR, after writing one or more still images in the semiconductor memory (17),
A desired still image can be read from the semiconductor memory (17) and recorded in an arbitrary area of the magnetic tape (10). Also, when the semiconductor memory (17) is full, the still image in the semiconductor memory (17) is transferred onto the magnetic tape (10),
It is also possible to secure a free space in the semiconductor memory (17).

In this case, the video data D2 from the semiconductor memory (17) is selected by the second changeover switch (16) and the semiconductor memory (1) is selected by the first changeover switch (50).
With the video data D2 from 7) selected, operate the shutter button (5) while watching the monitor screen. As a result, the still image displayed when the shutter button (5) is operated is recorded on the magnetic tape (10). here,
If a still image recording area for 30 seconds, for example, is provided at a predetermined position on the magnetic tape (10), for example, at the beginning of the tape as shown in FIG. 9, and still images are sequentially recorded in the recording area. , When playing back the magnetic tape (10) later, a still image does not interrupt the moving image. Further, when searching for a desired still image, the search area is small, so that it does not take time. In this case, even if the video data of each still image is recorded for 5 frames, 180 still images can be recorded in the still image recording area for 30 seconds. The still image recording area is not limited to the beginning or end of the tape, but may be provided at the beginning of the moving image recording area for each day. In this way, for still images to be recorded on the magnetic tape (10),
Make various edits.

According to the digital VTR, since the still image video data is recorded in the semiconductor memory (17), the still image can be searched at high speed. In addition, since a circuit configuration for recording a still image is added to the circuit configuration for recording video data for a moving image on the magnetic tape (10), it is possible to record a still image during recording of a moving image. Not only is it possible, but image compression processing circuit (4) and image expansion processing circuit (1
By sharing 5), the circuit configuration is simplified.

The description of the above embodiments is for the purpose of explaining the present invention, and should not be construed as limiting the invention described in the claims or reducing the scope thereof.
In addition, the configuration of each part of the present invention is not limited to the above-described embodiment, and it goes without saying that various modifications can be made within the technical scope described in the claims. For example, the present invention can be applied to not only a DV format digital VTR but also a digital video recorder that records and reproduces video data on various recording media, and similar effects can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a digital VTR according to the present invention.

FIG. 2 is a block diagram showing a configuration of an upper address generation circuit.

FIG. 3 is a block diagram showing a configuration of a lower address generation circuit.

FIG. 4 is a block diagram showing a configuration of a memory enable signal generation circuit.

FIG. 5 is a diagram showing respective recording areas and addresses of a semiconductor memory.

FIG. 6 is a time chart showing a signal write operation of an upper address generation circuit and a lower address generation circuit.

FIG. 7 is a time chart showing the operation of the memory enable signal generation circuit.

FIG. 8 is a time chart showing a signal read operation of an upper address generation circuit and a lower address generation circuit.

FIG. 9 is a diagram showing recording areas of moving images and still images formed on a magnetic tape by the digital VTR of the present invention.

FIG. 10 is a diagram showing recording areas of moving images and still images formed on a magnetic tape by a conventional digital VTR.

[Explanation of symbols]

 (1) Optical system (2) CCD (4) Image compression processing circuit (5) Shutter button (17) Semiconductor memory (18) Memory control signal generation circuit (10) Magnetic tape

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Hirotsugu Murashima 2-5-5 Keihan Hondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (72) Inventor Yoshiyuki Yoshida 2-chome, Keihan Hondori, Moriguchi-shi, Osaka No. 5-5 Sanyo Electric Co., Ltd.

Claims (4)

[Claims] 1. An image pickup system, an image compression system for subjecting a series of image data sent from the image pickup system to image compression processing in frame or field units, and a data recording system for recording the compressed image data on a recording medium. In a digital video recorder having a data reproduction system for reproducing video data from a recording medium and an image expansion system for performing image expansion processing on the reproduced video data and outputting the video data, the video data is written in frame or field units. And a readable semiconductor memory, and one frame or one field of video data is written to the semiconductor memory in response to a still image write command, while one frame or one field of video is written from the semiconductor memory in response to a still image read command. Memory control means for reading data and one frame or one file output from the image compression system. One of the first video data D1 of the field and the second video data D2 of one frame or one field read from the semiconductor memory is selected and sent to the data recording system. Data switching means SW1
And the second video data D2 read from the semiconductor memory
And the third video data D3 output from the data reproduction system
And a second data switching means SW2 for selecting one of the image data to be sent to the image expansion system. 2. One of the first video data D1 of one frame or one field output from the image compression system and the third video data D3 of one frame or one field output from the data reproduction system, 2. The digital video recorder according to claim 1, further comprising third data switching means SW3 for selecting one of the video data and sending it to the semiconductor memory. 3. The digital video recorder according to claim 1, wherein the semiconductor memory has a capacity capable of recording video data for a plurality of frames or a plurality of fields. 4. A high-order address generation circuit, wherein the memory control means generates a high-order address for specifying a write area or a read area in frame or field units for a plurality of frames or fields to be written or read. 4. The digital device according to claim 3, further comprising: a lower address generation circuit for generating a lower address for specifying a writing position or a reading position of a data unit for video data forming one frame or one field. Video recorder.