JP3249391B2 - Digital video recorder - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to recording digital video data sent from an imaging system such as a CCD on a recording medium such as a magnetic tape or reproducing video data from the recording medium and outputting the data to a monitor or the like. The present invention relates to a digital video recorder.

[0002]

2. Description of the Related Art HD (High Definition) digital VCR
In a digital VTR conforming to the DV format standardized by the council, digital video data for one frame of a moving image is recorded over ten tracks in the case of the NTSC system. In a digital VTR, by pressing a shutter button, one frame of video data obtained at that time can be recorded on a magnetic tape as a still image (magazine "Video α", November 1995).
Monthly No. 42-48).

[0003] In recording a still image, in order to record one frame of video data on a magnetic tape, 10 frames are recorded.
It is sufficient to provide a recording area for a track, 1/30 second,
In consideration of ease of retrieval, prevention of deterioration of image quality due to damage to the tape, and the like, the same video data is repeatedly recorded a plurality of times in units of 10 tracks over a predetermined time T (for example, 7 seconds). FIG. 10 shows a state in which a moving image and a still image are mixedly recorded on a magnetic tape, and a plurality of moving image recording areas having an arbitrary length and the predetermined time T over the predetermined time T according to the shooting order. A plurality of still image recording areas are formed. A digital VTR using such a magnetic tape
In this case, the moving image and the still image are reproduced in the recording order.

[0004]

However, in a conventional digital VTR, when a desired still image is to be reproduced, a fast forward or rewind operation is performed.
Since an area in which a desired still image is recorded has to be searched, the operation is complicated and takes time. For example, in the case of a one-hour tape in the DV format, searching from the beginning to the end of the tape requires 36 seconds even if fast-forwarding at 100 times speed is performed. Also, when collecting and re-recording still images recorded on a magnetic tape in one place on a magnetic tape, or re-recording in a rearranged order, an editing machine becomes indispensable, and editing work is troublesome. There was a problem that took time.

An object of the present invention is to provide a digital video recorder capable of reproducing a desired still image quickly and easily. Another object of the present invention is to provide a digital video recorder which can easily perform desired editing when recording a still image on a recording medium without using a special editing machine.

[0006]

According to the present invention, there is provided a digital video recorder comprising: an image pickup system; an image compression system for performing image compression processing on a series of video data sent from the image pickup system in frame or field units; A data recording system that records the reproduced video data on a recording medium, a data reproduction system that reproduces the video data from the recording medium, and an image decompression system that performs image decompression processing on the reproduced video data and outputs the resulting data. . The digital video recorder according to the present invention has a characteristic configuration in which a semiconductor memory capable of writing and reading video data in frame or field units and an image of one frame or one field in response to a still image writing command. While writing data to semiconductor memory,
Memory control means for reading one frame or one field of video data from the semiconductor memory in response to a still image read command; one frame or one field of first video data D1 output from the image compression system; The second of one frame or one field to be read
Out of the video data D2, the first data switching means SW1 to be transmitted to the data recording system, the second video data D2 read from the semiconductor memory, and the data reproduction system. And a second data switching means SW2 for selecting any one of the third video data D3 output from the first video data and transmitting the selected video data to the image decompression system.

In the digital video recorder, when recording a moving image, the first data switching means SW1 selects the video data D1 output from the image compression system and sends it to the data recording system. As a result, a series of video data to be a moving image is recorded on the recording medium. Further, when a still image recording command is issued during recording of a moving image, video data to be a still image is written to the semiconductor memory in parallel with the recording operation of a series of video data to be a moving image. Thereafter, at the time of moving image reproduction, the second data switching means SW2 selects video data from the data reproduction system and sends it to the image decompression system. Thus, the video data subjected to the image expansion processing is supplied to a monitor or the like, and a moving image is displayed.

On the other hand, at the time of reproducing a still image, a search for a semiconductor memory is performed. In general, the access time to a semiconductor memory is about several hundred nanoseconds at the longest, and is much shorter than the access time to a recording medium such as a magnetic tape, so that a very high-speed search is possible. At the time of still image reproduction, the second data switching means SW2 selects video data read from the semiconductor memory and sends it to the image decompression system. As a result, a still image is displayed on the monitor.

When one or more desired still images among the still images written in the semiconductor memory are to be recorded on the recording medium, the first data switching means SW1 is provided with the video data read from the semiconductor memory. And sends it to the data recording system. At this time, various edits can be performed by searching the semiconductor memory, such as recording a plurality of still images continuously at a predetermined location on the recording medium or recording the still images in a different order.

In the above-mentioned digital video recorder, after video data to be recorded as a moving image on a recording medium is subjected to image compression processing, one frame or one field of video data therein is converted into a still image by a semiconductor. Since the data is written to the memory, there is no need to provide an image compression system dedicated to still images. Also, video data for reproducing a moving image reproduced from a recording medium and video data for reproducing a still image read from a semiconductor memory are output to a monitor or the like through a common image decompression system. There is no need to provide a dedicated image expansion system.

The digital video recorder according to the present invention further includes, in a specific configuration, one frame or one field of first video data D1 output from an image compression system and one frame or one field output from a data reproduction system. And a third data switching means SW3 for selecting any one of the third video data D3 and sending the selected video data to the semiconductor memory.

In the digital video recorder, the video data of the still picture reproduced from the recording medium is selected by the third data switching means SW3, so that the video data can be written in the semiconductor memory (17). . Therefore, the still image once recorded on the recording medium can be transferred to the semiconductor memory, and the still image in the semiconductor memory can be transferred to the recording medium again by switching the video data by the first data switching means SW1. I can do it.
As a result, various edits can be made on the recording medium.

Further, in a specific configuration, the semiconductor memory has a capacity capable of recording video data for a plurality of frames or a plurality of fields. The memory control means includes an upper address generation circuit for generating an upper address for specifying a write area or a read area in units of frames or fields for a plurality of frames or fields to be written or read; A lower address generating circuit for generating a lower address for specifying a write position or a read position in a data unit for a series of video data constituting a frame or one field is provided.

In this specific configuration, each time a still image recording command or a still image reproducing command is issued, an upper address is generated, and the memory area to be written or read in the semiconductor memory is frame or field unit. Specified. Further, when one memory area is specified by one upper address, a series of lower addresses for sequentially writing video data in the memory area or sequentially reading video data from the memory area is generated. A write position or a read position of each video data is specified together with the upper address. In this way, by defining the write or read address of the video data as the upper and lower hierarchical address structures, the circuit configuration of the memory control means is simplified.

[0015]

In the digital video recorder according to the present invention, since the video data of a still image is recorded in a semiconductor memory which can be accessed at a high speed, a desired still image can be reproduced quickly and easily. Further, since the semiconductor memory can be used for editing a still image on a recording medium, desired editing can be easily performed without using a special editing machine.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to a digital VTR of a DV format will be specifically described below with reference to the drawings. FIG. 1 shows the overall configuration of a digital VTR according to the present invention, and a signal processing system for recording and reproducing moving images, that is, a CCD image processing circuit (3), an image compression processing circuit (4), and an error correction code. Additional circuit (6), modulation processing circuit
(7) For the demodulation processing circuit (13), the error correction circuit (14), and the image expansion processing circuit (15), a shutter button (5) to be operated when recording a still image, and a video to be a still image A semiconductor memory (17) for storing data, a memory control signal generating circuit (18) for controlling writing and reading of video data to and from the semiconductor memory (17), and data to the semiconductor memory (17). A memory read / write clock generation circuit (40) for supplying a write and read clock is provided.

Further, three changeover switches (50), (16) and (51) are provided for changing over the image data. The first changeover switch SW1 (50) switches between the video data D1 output from the image compression processing circuit (4) and the video data D2 read from the semiconductor memory (17) to provide an error correction code adding circuit (6). It is for supplying to. The second changeover switch SW2 (16) switches between the video data D3 output from the error correction circuit (14) and the video data D2 read from the semiconductor memory (17), and switches the image expansion processing circuit (1).
It is for supplying to 5). Third changeover switch S
W3 (51) switches between video data D1 output from the image compression processing circuit (4) and video data D3 output from the error correction circuit (14), and supplies the video data D3 to the semiconductor memory (17). Things.

In the signal recording mode, light from the subject is condensed on the CCD image pickup device (2) via the optical system (1).
Converted to electrical signals. The electric signal is supplied to a CCD image processing circuit (3), and the luminance signal Y and the color difference signals Pb, P
r is converted into digital video data. Digital video data obtained from the CCD image processing circuit (3) is input to an image compression processing circuit (4), and after the amount of information is compressed by DCT (discrete cosine transform), the compressed video data D1 is converted to the first video data. The signal is supplied to an error correction code adding circuit (6) via a changeover switch (50), and an error correction code is added.
Further, the video data obtained from the error correction code adding circuit (6) undergoes necessary modulation processing in the modulation processing circuit (7),
After passing through the recording amplifier (8) and recording head (9), the magnetic tape
Recorded in (10).

In the signal reproducing mode, the magnetic tape (10)
Are reproduced by a reproducing head (11), subjected to a waveform equalization process by an equalizer (12), and then demodulated by a demodulation processing circuit (13). Video data obtained from the demodulation processing circuit (13) is subjected to error detection and error correction based on an error correction code in an error correction circuit (14). Video data D3 output from the error correction circuit (14)
Is the image expansion processing circuit (15) through the changeover switch (16).
Supplied to In the image expansion processing circuit (15), image expansion processing is performed, and the original luminance signal Y and color difference signals Pb, Pr are obtained.
, And these data are output to an external monitor. As a result, a moving image is displayed on the external monitor.

When recording a still image while recording a moving image,
Press the shutter button (5). Thereby, the shutter pulse is supplied to the memory control signal generation circuit (18) and the image compression processing circuit (4). The image compression processing circuit (4) creates a frame pulse W according to the input of the shutter pulse and supplies it to the memory control signal generation circuit (18). by this,
The memory control signal generation circuit (18) supplies a control signal (memory enable signal and address signal) for writing data to the semiconductor memory (17). As a result, the compressed video data for one frame output from the image compression processing circuit (4) is supplied to the semiconductor memory (17) via the third changeover switch (51), and is written to the designated address.

Thereafter, when reproducing a still image, video data for one frame is read from the semiconductor memory (17),
The video data D2 is supplied to an image expansion processing circuit (15) via a changeover switch (16). As a result, the luminance signal Y and the color difference signals Pb and Pr for one frame are output to the external monitor, and a still image is displayed.

By the way, in the DV format,
One frame of video data includes 77 bytes × 138 sync blocks × 10 tracks = 1, including VAUX data having video-related information.
Since it has a data amount of 06260 bytes, an area of 106260 bytes may be secured in the semiconductor memory (17) to record one still image. Therefore, in order to record 10 still images, at least 1.07 Mbytes of semiconductor memory (17)
You just need to prepare. Here, when the unit of data writing is 8 bits and a semiconductor memory (17) capable of addressing every 8 bits is adopted, the address is set to 106260
By incrementing by the unit, the address A of the head data of the Nth (N ≧ 10) th still image can be represented by A = (N−1) × 106260, whereby the semiconductor memory (17)
And writing and reading of video data to and from the image data can be controlled.

However, in the above method, it is necessary to individually generate an address for every video data constituting 10 still images, so that the address generation circuit becomes complicated. Therefore, in this embodiment,
The address method shown in FIG. 5 is adopted. That is, the memory area allocated to one still image is 2 ¹⁷ (= 131072) bytes, and the lower address is configured in 17-bit units. The lower address is set to 0 each time the head data of a still image is input.
Is reset to 1 by the clock synchronized with the data.
Counts up by one. In order to specify one still image, a 4-bit upper address is formed, and the upper address indicates the number of 16 still images.

As a result, all the still picture data are stored in lower addresses 0x0000 to 0x19F13 as shown in FIG.
The data is written in a data area represented by (hexadecimal notation), and the memory area of lower addresses 0x19F14 to 0xFFFFF is used as a dummy data area and is not used for recording still image data. Therefore, when n is a hexadecimal number (0 to F), the nth still image is stored in an area where the upper address is 0xn and the lower address is 0x00000 to 0x19F13.

In order to realize the above addressing method, the memory control signal generating circuit (18) of FIG. 1 is replaced by an upper address generating circuit (41) shown in FIG. 2 and a lower address generating circuit (4) shown in FIG.
2) and a memory enable signal generation circuit (43) shown in FIG. FIG. 6 shows the operation of the upper address generation circuit (41) and the lower address generation circuit (42) in the signal recording mode.

In the upper address generating circuit (41) shown in FIG. 2, when the switch (27) is operated to set the signal recording mode, the switch (27) reads / writes "L" to the selector (25). Supply select signal. On the other hand, when the signal reproduction mode is set, the switch (27) is set to the selector (25).
Is supplied with a read / write select signal of "H". This allows the selector (25) to operate in the signal recording mode.
The upper address counter (19) selects the 4-bit data of the "0" port connected thereto, and in the signal reproduction mode, selects the 4-bit data of the "1" port connected to the dip switch (26).

In the signal recording mode, first, a reset button
When (20) is operated, the reset pulse generated by this is supplied to the D-type flip-flop (21) and the upper address counter (19). Accordingly, the output of the upper address counter (19), that is, the upper address is 0x0
Is set to At the same time, the output of the D-type flip-flop (21) becomes "L", the output of the 4-input NAND gate (23) becomes "H", and the camera enters a shutter waiting state.

In this state, when the first shutter is released, the shutter pulse generated by this is input to the three-input AND gate (22) via the NOT gate (24).
Here, the output of the D-type flip-flop (21) is "L".
Therefore, no shutter pulse is input to the upper address counter (19). Next, at the rising timing of the first shutter pulse, a D-type flip-flop is
The output of (21) becomes "H", and a second shutter wait state is set.

When the second shutter is released, a shutter pulse is input to the upper address counter (19), and the upper address value is counted up to 0x1. Or later,
By the same operation until the 16th time, the upper address becomes 0x
It will be counted up to F.

When the upper address becomes 0xF, 4 inputs N
The output of the AND gate (23) becomes "L", and rejection of the 17th and subsequent shutter pulses is rejected. This is because, in this embodiment, the memory capacity is 16 still images.
This is to prohibit the 17th and subsequent data fetches.
Therefore, when a larger capacity memory is used, a circuit configuration corresponding to the capacity is used. At this time, the 4-input NA
The output ("L") of the ND gate (23) is input as a write enable permission signal to a memory enable signal generation circuit described later.

In the signal recording mode, the lower-order address generation circuit (42) shown in FIG.
As shown in FIG. 6, a frame pulse W which becomes "L" while compressed data is being output is input in synchronization with the memory write clock as shown in FIG. Selector
(30) is obtained by the aforementioned read / write select signal.
The frame pulse W of the “0” port is selected. The selected frame pulse W is sent to the lower address counter (2) through a NOT gate (28) and a D-type flip-flop (31).
Input to the reset terminal of 9). When the frame pulse W is "H", the lower address counter (29) is set to 0x00.
000 has been reset. When the compressed data is output from the image compression processing circuit (4), the frame pulse W becomes "L" and the lower address counter (29) is counted up by the memory write clock.

The memory enable signal generation circuit (43) generates a memory enable signal for permitting data writing to the semiconductor memory (17) in the signal recording mode. The circuit configuration is shown in FIG. And its circuit operation is shown in FIG. The shutter pulse supplied from the shutter button (5) is converted by the monostable multivibrator (36) into a shutter pulse _A that becomes “L” for only one frame pulse period, and then the D-type flip-flop (32) The shutter pulse_B latched by the frame pulse W and obtained thereby is input to a three-input OR circuit (33).

Since the selector (34) has been selected as the "0" port by the read / write select signal, the signal from the three-input OR circuit (33) is output as a memory write enable signal. This memory write enable signal becomes "L" only during the "L" period of the frame pulse W after the shutter button is operated, and during that period, data writing to the semiconductor memory (17) is permitted. However, for the 17th and subsequent shutter pulses, the signal obtained by latching the write enable enable signal output from the 4-input NAND gate (23) by the D-type flip-flop (35) becomes "H". The memory write enable signal input to the 3-input OR circuit (33) becomes "H", and data writing to the semiconductor memory (17) is prohibited. At times other than the time of memory writing, the selector (34) selects the "H" state to prevent memory writing due to malfunction.

As described above, the memory control signal generating circuit (18)
Data to the semiconductor memory (17) by the address signal and the memory write enable signal generated by the above, the video data from the image compression processing circuit (4), and the memory write clock from the memory read / write clock generation circuit (40). Writing is performed. Here, since data writing to the semiconductor memory (17) does not affect the operation at the time of normal moving image recording at all, even during moving image recording, the data can be obtained at that time by operating the shutter button (5). One frame of video data can be written to the semiconductor memory (17) as a still image.

In the signal reproduction mode, when reproducing a still image, the changeover switch (16) shown in FIG. 1 is switched to the semiconductor memory (17) side, and the still image data written in the semiconductor memory (17) is changed. The image data is supplied to the image expansion processing circuit (15), and the still image is restored. Selection of a still image to be restored is performed by operating a dip switch (26) shown in FIG. 2 and inputting a still image number corresponding to a desired still image. The still image number is output as an upper address to the semiconductor memory (17) via the selector (25). At this time, the read / write select signal is set to "H" by the switch (27).

In the memory enable signal generation circuit (43) shown in FIG. 4, the read enable generation circuit (38)
The memory read clock is counted, and as shown in FIG. 8, a signal of "L" is output during the 106260 clock period and a signal of "H" is output during the 24812 clock period. The output signal is shown in FIG.
Is supplied to the semiconductor memory (17) as a memory read enable signal via the selector (37) shown in FIG. The "L" period of the memory read enable signal is a period required to read one frame of video data from the semiconductor memory (17), and during this period, a lower address is specified in synchronization with the memory read clock. By doing, semiconductor memory
The video data of a specific still image stored in (17) can be sequentially read.

The lower address is generated by a lower address generator (42) shown in FIG. Here, the memory read clock from the memory read / write clock generation circuit (40) is supplied to the lower address counter (29),
The lower address counter (29) counts up. Also, the memory read enable signal is input to the reset terminal of the lower address counter (29) via the NOT gate (28) and the D-type flip-flop (31). Is performed.

As shown in FIG. 4, a signal obtained by latching a memory read enable signal by a D-type flip-flop (39) is output as a frame pulse R to an image expansion processing circuit (15). Thereby, the image expansion processing circuit (15)
Is the semiconductor memory (17) during the "L" period of the frame pulse R.
Can be recognized that data for one frame has been output.

The image expansion processing circuit (15) receives the frame pulse R and the compressed video data for one frame from the semiconductor memory (17), and converts the data into the original luminance signal Y and color difference signals Pb and Pr. Restore and output to an external monitor. As a result, a desired still image is displayed on the external monitor.

Next, a circuit operation for performing various editing operations when recording a still image on the magnetic tape (10) by the digital VTR will be described. According to the digital VTR, one or more still images or moving images are recorded on a magnetic tape (10) in the same manner as a conventional digital VTR,
One frame of a still image or a moving image recorded on the magnetic tape (10) can be reproduced, and the frame can be written as a still image in the semiconductor memory (17).

In this case, the video data D3 from the error correction circuit (14) is selected by the second changeover switch (16), and the error correction circuit (1) is selected by the third changeover switch (51).
With the video data D3 from 4) selected, the shutter button (5) is operated while looking at the screen of the monitor. As a result, one frame of a still image or a moving image that was projected when the shutter button (5) was operated is written into the semiconductor memory (17). In this way, the still image to be edited is transferred from the magnetic tape (10) to the semiconductor memory (17).

According to the digital VTR, after one or more still images are written in the semiconductor memory (17),
A desired still image can be read from the semiconductor memory (17) and the still image can be recorded in an arbitrary area of the magnetic tape (10). When the semiconductor memory (17) is full, the still image in the semiconductor memory (17) is transferred onto the magnetic tape (10),
It is also possible to secure a free space in the semiconductor memory (17).

In this case, the video data D2 from the semiconductor memory (17) is selected by the second changeover switch (16), and the semiconductor memory (1) is changed by the first changeover switch (50).
With the video data D2 from 7) selected, the shutter button (5) is operated while looking at the monitor screen. As a result, the still image projected when the shutter button (5) is operated is recorded on the magnetic tape (10). here,
A still image recording area for, for example, 30 seconds is provided at a predetermined location on the magnetic tape (10), for example, at the beginning of the tape as shown in FIG. 9, and the still images are sequentially recorded in the recording area. When the magnetic tape (10) is reproduced later, a still image does not interrupt between moving images. In addition, when searching for a desired still image, the search area is narrow, so that it does not take much time. In this case, even if the video data of each still image is recorded for 5 frames, 180 still images can be recorded in the still image recording area for 30 seconds. Note that the still image recording area is not limited to the beginning and end of the tape, but can be provided at the beginning of the moving image recording area for each day. In this way, for still images to be recorded on the magnetic tape (10),
Various edits are made.

According to the digital VTR, since the video data of the still image is recorded in the semiconductor memory (17), the still image can be searched at a high speed. In addition, since a circuit configuration for recording a still image is added to the circuit configuration for recording video data to be a moving image on the magnetic tape (10), recording of a still image can be performed even during recording of a moving image. Not only is possible, but also an image compression processing circuit (4) and an image decompression processing circuit (1
By sharing 5), the circuit configuration is simplified.

The description of the above embodiments is for the purpose of explaining the present invention, and should not be construed as limiting the invention described in the claims or reducing the scope thereof.
In addition, the configuration of each part of the present invention is not limited to the above-described embodiment, and it goes without saying that various modifications can be made within the technical scope described in the claims. For example, the present invention is not limited to the digital VTR of the DV format, but can be applied to a digital video recorder that records and reproduces video data on various recording media, and the same effects can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an entire configuration of a digital VTR according to the present invention.

FIG. 2 is a block diagram illustrating a configuration of an upper address generation circuit.

FIG. 3 is a block diagram showing a configuration of a lower address generation circuit.

FIG. 4 is a block diagram illustrating a configuration of a memory enable signal generation circuit.

FIG. 5 is a diagram showing recording areas and addresses of a semiconductor memory.

FIG. 6 is a time chart illustrating a signal write operation of an upper address generation circuit and a lower address generation circuit.

FIG. 7 is a time chart illustrating an operation of the memory enable signal generation circuit.

FIG. 8 is a time chart showing a signal read operation of an upper address generation circuit and a lower address generation circuit.

FIG. 9 is a diagram showing recording areas of moving images and still images formed on a magnetic tape by the digital VTR of the present invention.

FIG. 10 is a diagram illustrating recording areas of moving images and still images formed on a magnetic tape by a conventional digital VTR.

[Explanation of symbols]

 (1) Optical system (2) CCD (4) Image compression processing circuit (5) Shutter button (17) Semiconductor memory (18) Memory control signal generation circuit (10) Magnetic tape

──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Hiroshi Murashima 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (72) Yoshiyuki Yoshida 2-chome, Keihanhondori, Moriguchi-shi, Osaka No. 5 Sanyo Electric Co., Ltd. (56) References JP-A-5-37896 (JP, A) JP-A-6-113250 (JP, A) JP-A 8-130711 (JP, A) (58) Survey Field (Int.Cl. ⁷ , DB name) H04N 5/76-5/956 G11B 20/10-20/12

Claims (4)

(57) [Claims] 1. An imaging system, an image compression system for performing image compression processing on a series of video data sent from the imaging system in frame or field units, and a data recording system for recording compressed video data on a recording medium And a data reproduction system for reproducing video data from a recording medium, and an image decompression system for performing image decompression processing on reproduced video data and outputting the reproduced video data. And a readable semiconductor memory, and writes one frame or one field of video data to the semiconductor memory in response to a still image write command, and one frame or one field of video from the semiconductor memory in response to a still image read command. Memory control means for reading data, and one frame or one file output from the image compression system. Of the first video data D1 of the first field and the second video data D2 of one frame or one field read from the semiconductor memory, and the first video data to be transmitted to the data recording system is selected. Data switching means SW1
And second video data D2 read from the semiconductor memory
And third video data D3 output from the data reproduction system.
And a second data switching means SW2 for selecting any one of the video data and transmitting it to the image decompression system. 2. One frame or one field of the first video data D1 output from the image compression system and one frame or one field of the third video data D3 output from the data reproduction system. The digital video recorder according to claim 1, further comprising third data switching means (SW3) for selecting one of the video data and transmitting the video data to the semiconductor memory. 3. The digital video recorder according to claim 1, wherein the semiconductor memory has a capacity capable of recording video data for a plurality of frames or a plurality of fields. 4. An upper address generation circuit for generating an upper address for specifying a write area or a read area in units of frames or fields for a plurality of frames or fields to be written or read. 4. The digital device according to claim 3, further comprising: a lower address generation circuit for generating a lower address for specifying a write position or a read position in a data unit for video data constituting one frame or one field. Video recorder.