JP3272244B2 - Digital video recorder - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to recording digital video data sent from an imaging system such as a CCD on a recording medium such as a magnetic tape or reproducing video data from the recording medium and outputting the data to a monitor or the like. The present invention relates to a digital video recorder.

[0002]

2. Description of the Related Art HD (High Definition) digital VCR
In a digital VTR conforming to the DV format standardized by the council, digital video data for one frame of a moving image is recorded over ten tracks in the case of the NTSC system. In a digital VTR, by pressing a shutter button, one frame of video data obtained at that time can be recorded on a magnetic tape as a still image (magazine "Video α", November 1995).
Monthly No. 42-48).

[0003] In recording a still image, in order to record one frame of video data on a magnetic tape, 10 frames are recorded.
It is sufficient to provide a recording area for a track, 1/30 second,
In consideration of ease of retrieval, prevention of deterioration of image quality due to damage to the tape, and the like, the same video data is repeatedly recorded a plurality of times in units of 10 tracks over a predetermined time T (for example, 7 seconds). FIG. 9 shows a state in which moving images and still images are mixedly recorded on a magnetic tape, and a plurality of moving image recording areas having an arbitrary length according to a shooting order;
A plurality of still image recording areas over the predetermined time T are formed. When such a magnetic tape is reproduced by a digital VTR, moving images and still images are reproduced in the order of recording.

[0004]

However, in a conventional digital VTR, when a desired still image is to be reproduced, a fast forward or rewind operation is performed.
Since an area in which a desired still image is recorded has to be searched, the operation is complicated and takes time. For example, in the case of a one-hour tape in the DV format, searching from the beginning to the end of the tape requires 36 seconds even if fast-forwarding at 100 times speed is performed.

[0005] When reproducing still picture image data recorded on a magnetic tape and displaying it on a monitor or supplying it to an external device such as an information processing machine or an editing machine via a cable or the like, the magnetic tape In the process of recording and playing back video data, large errors may occur in the data due to scratches on the magnetic tape, etc. May not be possible.

SUMMARY OF THE INVENTION It is an object of the present invention to quickly and easily reproduce a desired still image, and to perform an effective error correction at the time of reproducing a still image or processing by an external device. To provide a digital video recorder.

[0007]

A digital video recorder according to the present invention comprises: an imaging device; an image compression processing circuit for performing image compression processing on a series of video data sent from the imaging device in units of frames or fields; An error correction code adding circuit for adding an error correction code to the compressed video data, a data recording circuit for recording the video data with the error correction code added on a recording medium, and a data reproducing circuit for reproducing the video data from the recording medium And an error correction circuit for performing error correction on reproduced video data, and an image decompression processing circuit for performing image decompression processing on the error-corrected video data and outputting the resulting data. Further, the digital video recorder according to the present invention has a characteristic configuration in which a semiconductor memory capable of writing and reading video data to which an error correction code is added can be written in units of frames or fields and a still image writing command. Memory control means for writing one frame or one field of video data obtained from the error correction code adding circuit to the semiconductor memory, and for reading one frame or one field of video data from the semiconductor memory in response to a still image read command; Data switching means for supplying video data read from the semiconductor memory to the error correction circuit.

In the digital video recorder of the present invention, when a still image recording command is issued during recording of a moving image, the video data of a still image is written to the semiconductor memory in parallel with the recording operation of a series of video data of a moving image. It is. And
When the desired still image is to be reproduced after the recording of the moving image and the still image is completed, a search for the semiconductor memory is performed. In general, the access time to a semiconductor memory is about several hundred nanoseconds at the longest, and is much shorter than the access time to a recording medium such as a magnetic tape, so that a very high-speed search is possible.

In the digital video recorder according to the present invention, after image compression processing and addition of an error correction code are performed on video data to be recorded on a recording medium as a moving image, one frame or one field in the data is processed. Is written in the semiconductor memory as a still image. Therefore, it is not necessary to provide an image compression processing circuit and an error correction code adding circuit dedicated to a still image. Also, video data for reproducing a moving image reproduced from a recording medium and video data for reproducing a still image read from a semiconductor memory are output to a monitor or the like via a common error correction circuit and an image expansion processing circuit. You. Therefore, there is no need to provide an error correction circuit and an image expansion processing circuit dedicated to a still image.

In a specific configuration, the semiconductor memory has a capacity capable of recording video data for a plurality of frames or a plurality of fields including an error correction code. The memory control means includes an upper address generation circuit for generating an upper address for specifying a write area or a read area in units of frames or fields for a plurality of frames or fields to be written or read; A lower address generating circuit for generating a lower address for specifying a write position or a read position in a data unit for a series of video data constituting a frame or one field is provided.

In this specific configuration, each time a still image recording command or a still image reproducing command is issued, an upper address is generated, and the memory area to be written or read in the semiconductor memory is frame or field unit. Specified. Further, when one memory area is specified by one upper address, a series of lower addresses for sequentially writing video data in the memory area or sequentially reading video data from the memory area is generated. A write position or a read position of each video data is specified together with the upper address. In this way, by defining the write or read address of the video data as the upper and lower hierarchical address structures, the circuit configuration of the memory control means is simplified.

[0012]

In the digital video recorder according to the present invention, since the video data of a still image is recorded in a semiconductor memory which can be accessed at a high speed, a desired still image can be reproduced quickly and easily. In addition, video data to be a still image is written to a semiconductor memory as data including an error correction code, and then read out from the semiconductor memory when a still image is reproduced or supplied to an external device. The error can hardly occur, so that an effective error correction can be performed during reproduction of a still image or processing by an external device.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to a digital VTR of a DV format will be specifically described below with reference to the drawings. FIG. 1 shows the overall configuration of a digital VTR according to the present invention. In a general signal processing system for recording and reproducing moving images, a shutter button (5) to be operated when recording a still image is provided. A semiconductor memory (17) for storing video data to be a still image, a memory control signal generation circuit (18) for controlling writing and reading of video data to and from the semiconductor memory (17), and a semiconductor memory ( A memory read / write clock generating circuit (40) for supplying a clock for writing and reading data to 17) is provided. In the signal recording mode, light from the subject is condensed on the CCD image pickup device (2) via the optical system (1) and is converted into an electric signal. The electric signal is a CCD image processing circuit
Supplied to (3), the luminance signal Y and the color difference signals Pb, Pr
Is converted to digital video data.

The digital video data obtained from the CCD image processing circuit (3) is input to an image compression processing circuit (4), and after the amount of information is compressed by DCT (discrete cosine transform), an error correction code adding circuit is provided. In (6), an error correction code is added. Further, the video data obtained from the error correction code adding circuit (6) undergoes necessary modulation processing in a modulation processing circuit (7), and then passes through a recording amplifier (8) and a recording head (9) to a magnetic tape ( Recorded in 10).

In the signal reproducing mode, the magnetic tape (10)
Are reproduced by a reproducing head (11), subjected to a waveform equalization process by an equalizer (12), and then demodulated by a demodulation processing circuit (13). The video data obtained from the demodulation processing circuit (13) is supplied to a switch (16)
Then, the data is supplied to an error correction circuit (14), subjected to error detection and error correction based on the error correction code, and then supplied to an image decompression processing circuit (15). In the image expansion processing circuit (15), the image expansion processing is performed, and the original luminance signal Y and color difference signal P
The data is converted into digital video data consisting of b and Pr, and these data are output to an external monitor. As a result, a moving image is displayed on the external monitor.

When recording a still image during recording of a moving image,
Press the shutter button (5). As a result, the shutter pulse is supplied to the memory control signal generation circuit (18) and the image compression processing circuit (4). The image compression processing circuit (4) cuts out one frame of the compressed video data in response to the input of the shutter pulse and supplies it to the error correction code adding circuit (6).
In response, the error correction code adding circuit (6) creates a frame pulse W and supplies it to the memory control signal generating circuit (18). Thereby, the memory control signal generation circuit (18) supplies control signals (memory enable signal and address signal) for writing data to the semiconductor memory (17). As a result, one frame of video data output from the error correction code adding circuit (6) is supplied to the semiconductor memory (17) and written to the designated address.

Thereafter, when reproducing a still image, video data for one frame is read from the semiconductor memory (17),
The video data is supplied to an error correction circuit (14) via a changeover switch (16). Then, the video data subjected to error detection and error correction by the error correction circuit (14) is supplied to the image decompression processing circuit (15). As a result, the luminance signal Y and the color difference signals Pb and Pr for one frame are output to the external monitor, and a still image is displayed.

By the way, in the DV format,
One frame of video data, including VAUX data having video-related information and an error correction code, is 85 bytes × 149 sync blocks × 10 tracks = 1
Since it has a data amount of 26,650 bytes, it is sufficient to secure an area of 126,650 bytes in the semiconductor memory (17) in order to record one still image. Therefore, in order to record 10 still images, at least 1.27 Mbytes of semiconductor memory (17)
You just need to prepare. Here, when the data writing unit is 8 bits and a semiconductor memory (17) capable of addressing every 8 bits is adopted, the address is 126650.
By increasing in increments, the address A of the head data of the Nth (N ≧ 10) th still image can be represented by A = (N−1) × 126650, whereby the semiconductor memory (17)
And writing and reading of video data to and from the image data can be controlled.

However, in the above-mentioned method, it is necessary to individually generate addresses for all video data constituting 10 still images, so that the address generation circuit becomes complicated. Therefore, in this embodiment,
The address method shown in FIG. 5 is adopted. That is, the memory area allocated to one still image is 2 ¹⁷ (= 131072) bytes, and the lower address is configured in 17-bit units. The lower address is set to 0 each time the head data of a still image is input.
Is reset to 1 by the clock synchronized with the data.
Counts up by one. In order to specify one still image, a 4-bit upper address is formed, and the upper address indicates the number of 16 still images.

As a result, all the still picture data are stored in the lower addresses 0x0000 to 0x1EEB9 as shown in FIG.
The data is written in the data area represented by (hexadecimal notation), and the memory area of lower addresses 0x1EEBA to 0xFFFFF is used as a dummy data area and is not used for recording still image data. Therefore, when n is a hexadecimal number (0 to F), the n-th still image is stored in an area where the upper address is 0xn and the lower address is 0x00000 to 0x1EEB9.

In order to realize the above addressing method, the memory control signal generating circuit (18) of FIG. 1 is replaced by an upper address generating circuit (41) shown in FIG. 2 and a lower address generating circuit (4) shown in FIG.
2) and a memory enable signal generation circuit (43) shown in FIG. FIG. 6 shows the operation of the upper address generation circuit (41) and the lower address generation circuit (42) in the signal recording mode.

In the upper address generating circuit (41) shown in FIG. 2, when a signal recording mode is set by operating a mode switching switch (27), the switch (27) becomes a selector.
An "L" read / write select signal is supplied to (25). On the other hand, when the signal playback mode is set, the switch (2
7) supplies an "H" read / write select signal to the selector (25). Thus, in the signal recording mode, the selector (25) selects the 4-bit data of the “0” port to which the upper address counter (19) is connected, and in the signal reproduction mode, the dip switch (26) is connected. Select 4-bit data of "1" port.

In the signal recording mode, first, a reset button
When (20) is operated, the reset pulse generated by this is supplied to the D-type flip-flop (21) and the upper address counter (19). Accordingly, the output of the upper address counter (19), that is, the upper address is 0x0
Is set to At the same time, the output of the D-type flip-flop (21) becomes "L", the output of the 4-input NAND gate (23) becomes "H", and the camera enters a shutter waiting state.

In this state, when the first shutter is released, a shutter pulse generated by this is input to a three-input AND gate (22) via a NOT gate (24).
Here, the output of the D-type flip-flop (21) is "L".
Therefore, no shutter pulse is input to the upper address counter (19). Next, at the rising timing of the first shutter pulse, a D-type flip-flop is
The output of (21) becomes "H", and a second shutter wait state is set.

When the second shutter is released, a shutter pulse is input to the upper address counter (19), and the upper address value is counted up to 0x1. Or later,
By the same operation until the 16th time, the upper address becomes 0x
It will be counted up to F.

When the upper address becomes 0xF, 4 inputs N
The output of the AND gate (23) becomes "L", and rejection of the 17th and subsequent shutter pulses is rejected. This is because, in this embodiment, the memory capacity is 16 still images.
This is to prohibit the 17th and subsequent data fetches.
Therefore, when a larger capacity memory is used, a circuit configuration corresponding to the capacity is used. At this time, the 4-input NA
The output ("L") of the ND gate (23) is input as a write enable permission signal to a memory enable signal generation circuit described later.

In the signal recording mode, the lower address generation circuit (42) shown in FIG.
As an output signal from (6), a frame pulse W which becomes "L" while compressed video data is being output as shown in FIG. 6 is input in synchronization with the memory write clock. The selector (30) selects the frame pulse W of the "0" port by the read / write select signal described above.
The selected frame pulse W is input to the reset terminal of the lower address counter (29) via the NOT gate (28) and the D-type flip-flop (31). When the frame pulse W is "H", the lower address counter (29) is set to 0
It has been reset to x00000. When the compressed data is output from the error correction code adding circuit (6), the frame pulse W becomes "L" and the lower address counter (29) is counted up by the memory write clock.

The memory enable signal generation circuit (43) generates a memory enable signal for permitting data writing to the semiconductor memory (17) in the signal recording mode. The circuit configuration is shown in FIG. And its circuit operation is shown in FIG. The shutter pulse supplied from the shutter button (5) is converted by the monostable multivibrator (36) into a shutter pulse _A that becomes “L” for only one frame pulse period, and then the D-type flip-flop (32) The shutter pulse_B latched by the frame pulse W and obtained thereby is input to a three-input OR circuit (33).

Since the selector (34) is selected as the "0" port by the read / write select signal, a signal from the three-input OR circuit (33) is output as a memory write enable signal. This memory write enable signal becomes "L" only during the "L" period of the frame pulse W after the shutter button is operated, and during that period, data writing to the semiconductor memory (17) is permitted. However, for the 17th and subsequent shutter pulses, the signal obtained by latching the write enable enable signal output from the 4-input NAND gate (23) by the D-type flip-flop (35) becomes "H". The memory write enable signal input to the 3-input OR circuit (33) becomes "H", and data writing to the semiconductor memory (17) is prohibited. At times other than during memory writing, the selector (34) selects the "H" state in order to prevent memory writing due to malfunction.

As described above, the memory control signal generating circuit (18)
The address signal and the memory write enable signal generated by the above, the compressed video data from the error correction code adding circuit (6), and the memory read / write clock generation circuit (40)
Memory write clock from the semiconductor memory
Data writing to (17) is performed. Here, since data writing to the semiconductor memory (17) does not affect the operation at the time of normal moving image recording at all, even during moving image recording, the data can be obtained at that time by operating the shutter button (5). One frame of video data can be written to the semiconductor memory (17) as a still image.

In the signal reproduction mode, when reproducing a still image, the changeover switch (16) shown in FIG. 1 is switched to the semiconductor memory (17) side so that the still image data written in the semiconductor memory (17) is changed. Supplied to the error correction circuit (14),
After error detection and error correction are performed, the image expansion processing circuit
The data is supplied to (15), and the still image is restored. The selection of the still image to be restored is made by the dip switch (26) shown in FIG.
And inputting a still image number corresponding to a desired still image. Select the still image number using the selector (2
The data is output as an upper address to the semiconductor memory (17) through 5). At this time, the read / write select signal is
It is set to “H” by (27).

In the memory enable signal generation circuit (43) shown in FIG. 4, the read enable generation circuit (38)
The memory read clock is counted, and as shown in FIG. 8, a signal of "L" is outputted for a period of 126650 clocks, and a signal of "H" is outputted for a period of 4422 clocks. The output signal is supplied to the semiconductor memory (17) as a memory read enable signal via the selector (37) shown in FIG. The "L" period of the memory read enable signal is a period required to read one frame of video data from the semiconductor memory (17), and during this period, a lower address is specified in synchronization with the memory read clock. By doing, semiconductor memory
The video data of a specific still image stored in (17) can be sequentially read.

The lower address is generated by a lower address generator (42) shown in FIG. Here, the memory read clock from the memory read / write clock generation circuit (40) is supplied to the lower address counter (29),
The lower address counter (29) counts up. Also, the memory read enable signal is input to the reset terminal of the lower address counter (29) via the NOT gate (28) and the D-type flip-flop (31). Is performed.

As shown in FIG. 4, a signal obtained by latching a memory read enable signal by a D-type flip-flop (39) is output as a frame pulse R to an error correction circuit (14). Thus, the error correction circuit (14) can recognize that one frame of data is output from the semiconductor memory (17) during the "L" period of the frame pulse R.

The error correction circuit (14) calculates the frame pulse R
And receives one frame of compressed video data from the semiconductor memory (17), performs error detection and error correction on the data, and then converts the error-corrected video data into an image decompression processing circuit.
Supply to (15). The image decompression processing circuit (15) subjects the compressed video data for one frame to image decompression, and the video data obtained by this is further supplied to the image decompression processing circuit (15), where the original luminance signal Y and color difference After being restored to the signals Pb and Pr, they are output to an external monitor. As a result, a desired still image is displayed on the external monitor.

According to the digital VTR, since the video data of the still image is recorded in the semiconductor memory (17), the still image can be searched at a high speed. Since the still image is played back, a high-quality still image can be displayed regardless of whether or not the magnetic tape (10) is damaged. Also, when video data read from the semiconductor memory (17) is supplied to an external device such as an editing machine via a cable, almost no errors occur in the data during the writing and reading processes to and from the semiconductor memory (17). In the external device, based on the error correction code included in the video data, for a data error that may occur in the transmission process,
Effective error correction can be performed.

Further, video data to be a moving image is transferred to a magnetic tape.
The circuit configuration for recording still images has been added to the circuit configuration for recording in (10), so not only can still images be recorded during moving image recording, but also image compression processing can be performed. The circuit configuration is simplified by sharing the circuit (4), the error correction code adding circuit (6), the error correction circuit (14), and the image decompression processing circuit (15). Furthermore, since only moving images can be recorded on the magnetic tape (10),
There is no interruption of the still image in the process of reproducing (10).

The description of the above embodiments is for the purpose of illustrating the present invention, and should not be construed as limiting the invention described in the claims or reducing the scope thereof.
In addition, the configuration of each part of the present invention is not limited to the above-described embodiment, and it goes without saying that various modifications can be made within the technical scope described in the claims. For example, the present invention is not limited to the digital VTR of the DV format, but can be applied to a digital video recorder that records and reproduces video data on various recording media, and the same effects can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an entire configuration of a digital VTR according to the present invention.

FIG. 2 is a block diagram illustrating a configuration of an upper address generation circuit.

FIG. 3 is a block diagram showing a configuration of a lower address generation circuit.

FIG. 4 is a block diagram illustrating a configuration of a memory enable signal generation circuit.

FIG. 5 is a diagram showing recording areas and addresses of a semiconductor memory.

FIG. 6 is a time chart illustrating a signal write operation of an upper address generation circuit and a lower address generation circuit.

FIG. 7 is a time chart illustrating an operation of the memory enable signal generation circuit.

FIG. 8 is a time chart showing a signal read operation of an upper address generation circuit and a lower address generation circuit.

FIG. 9 is a diagram illustrating recording areas of moving images and still images formed on a magnetic tape by a conventional digital VTR.

[Explanation of symbols]

 (1) Optical system (2) CCD (4) Image compression processing circuit (5) Shutter button (17) Semiconductor memory (18) Memory control signal generation circuit (10) Magnetic tape

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Takashi Onaka 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (72) Inventor Masahiko Tomikawa 2-5-2 Keihanhondori, Moriguchi-shi, Osaka No. 5 Sanyo Electric Co., Ltd. (56) References JP-A-8-130711 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 5/76-5/956 G11B 20 / 10-20/12

Claims (1)

(57) [Claims] An image pickup apparatus, an image compression processing circuit that performs image compression processing on a series of video data sent from the image pickup apparatus in units of frames or fields, and an error that adds an error correction code to the compressed video data. A correction code adding circuit, a data recording circuit for recording video data to which an error correction code is added on a recording medium, a data reproducing circuit for reproducing video data from the recording medium, and an error for performing error correction on the reproduced video data. In a digital video recorder including a correction circuit and an image decompression processing circuit that performs image decompression processing on video data on which error correction has been performed, and outputs a plurality of frames to which an error correction code is added in frame or field units. a semiconductor memory capable of writing and reading of image data of a plurality field of, in response to the still image write command, erroneous Memory control means for writing one frame or one field of video data obtained from the correction code adding circuit into the semiconductor memory, and for reading one frame or one field of video data from the semiconductor memory in response to a still image read command; Data switching means for supplying the video data read from the memory to the error correction circuit, wherein the memory control means sets the data to be written or read.
Multiple frames or fields
Write area or read area in units of frames or fields
Upper address to generate upper address to specify area
And one frame or one field.
Write position or data unit
Or the lower address for specifying the read position
A digital video recorder , comprising: