JPH09326909A - Image processing method and its unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To conduct error spread binarization processing in a short time without requiring a local memory by using a fast page mode so as to store and read error data generated in the error spread processing process to a register. SOLUTION: A contrast of consecutive 8-picture element C-J from input image data is read by registers X0-X7 by using the fast page mode. Furthermore, the contrast of B(C)-B(J) produced by the processing in a preceding line of the picture elements C J is read by registers E0-E7 by using the fast page mode similarly. Then the picture elements C are processed by using the value of the B(C) in the register E0, the contrast of the picture element C of a register X0, error data ER(A), (B) of an internal register of an error spread processing gate array caused by the processing result of the preceding picture elements A, B and the result is written in a register Y. Similarly, other picture elements D-J are processed and the error spread binarization processing is conducted in a short time without using a local memory.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing method and apparatus for processing multivalued data read by a scanner device and image data synthesized by a computer by, for example, an error diffusion method.

[0002]

2. Description of the Related Art Image data obtained by reading an image with a conventional image processing apparatus, for example, a scanner, is subjected to binarization processing by an error diffusion method by hardware such as an image processing gate array, and then the color or color processing is performed. An apparatus that outputs to an external image output apparatus such as a monochrome binary printer generally has a configuration as shown in FIG.
That is, the CPU 201 and the main memory 20 are connected to the bus 201.
3, image processing gate array 204, I / O port 20
6, the DMAC207 is directly connected, the scanner
An image input / output device 208 such as a printer is connected via an I / O port 206.

When the content of the image processing needs to refer to the pixel value around the pixel of interest, such as the binarization processing by the error diffusion method, the image processing gate is usually provided as shown in FIG. Attach local memory 205 to the array,
Operate as follows.

(1) Scanner 208 to I / O port 2
Image data in the main memory 203 via DM 06
Read by A transfer.

(2) In response to an instruction from the CPU 202, the image data is sent pixel by pixel to an image processing unit (here, an error diffusion processing unit) of the image processing gate array 204, where the input image is binarized. After that, the binarization result is written again in the main memory 203 for each pixel. However, the error data generated by the binarization processing of each pixel (data used in the binarization processing of the next line) is once written in the local memory 205 connected to the error diffusion processing unit,
When the pixel on the line next to the pixel of interest is binarized, it is read again from there and used for the processing.

(3) The binary image obtained as a result of the binarization process is output from the main memory 203 to the printer 208 by DMA transfer via the I / O port 206.

The local memory 205 here corresponds to an error buffer when the content of the image processing is binarization processing by the error diffusion method, and when it is edge enhancement processing of the image. It corresponds to the line memory of the input image. The data stored in these error buffers and line memories may be stored in the main memory 203,
As a result, the number and time of data movement between the main memory 203 and the image processing gate array 204 increase,
The ratio of the time to occupy the bus 201 becomes high,
The operation of the entire device becomes slow.

Therefore, in many cases, a FIFO type local memory (SRAM) 205 having a capacity capable of storing one or two lines of an image is installed in the image processing gate array 204 to temporarily store information of peripheral pixels of the image of interest. By storing the data in the bus 201, high-speed processing can be performed without occupying the bus 201 too much.

[0009]

However, in such an image processing apparatus, when the image processing gate array is provided with a local memory, the local memory is replaced by the main memory as shown in FIG. In comparison with, the hardware required for local memory access, such as an address counter, needs to be specially added to the image processing gate array, which causes a drawback that the design load and the gate array size increase. there were.

The present invention has been made to solve the above problems, and an object of the present invention is to provide an image processing method and apparatus which can perform image processing at high speed without requiring a local memory.

[0011]

In order to achieve the above object, the image processing apparatus of the present invention has the following configuration.

That is, the memory means includes image processing means for processing image data, memory means for storing image data processed by the image processing means, and control means for controlling access to the memory means. It is characterized in that the first page mode of the DMA controller is used for accessing.

Another image processing apparatus according to the present invention has the following configuration.

That is, the image processing means includes means for processing image data, memory means for storing image data processed by the image processing means, and control means for controlling access to the memory means. It is characterized in that it is connected to a system bus and uses a part of the memory means as a buffer for image processing.

Further, the image processing method of the present invention has the following steps.

That is, there are provided an image processing step of processing image data, a storage step of storing image data processed in the image processing step, and a control step of controlling access to the storage step. The first page mode of the DMA controller is used for access in the process.

Another image processing method according to the present invention has the following steps.

That is, there are provided an image processing step of processing the image data, a storage step of storing the image data processed in the image processing step in a memory, and a control step of controlling access to the memory, The memory is connected to the system bus, and a part of the memory is used as a buffer for image processing.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[First Embodiment] FIG. 1 is a block diagram showing the arrangement of an image processing apparatus according to the first embodiment.
In the figure, reference numeral 101 denotes a CPU, which controls the entire apparatus. 102 is a main memory, and in the embodiment, D
It is composed of RAM and is accessed via the bus 107. An error diffusion processing unit 103 binarizes the multivalued image data by the error diffusion method. A DMA controller 104 has a first page mode, which will be described later, and is connected to the main memory 102 and the error diffusion processing unit 1 via the bus 107.
Data (image data, error data) is exchanged with the server 03. An I / O port 105 inputs / outputs image data to / from a scanner or a printer (both depending on the configuration) 108. Reference numeral 106 denotes another interface, which transfers image data to another device connected to this device. Further, the CPU 101 directly controls the error diffusion processing unit 103, and outputs the output image data and 2
Manage the value error.

FIG. 4 is a diagram showing the configuration of the error diffusion processing unit 103 in the embodiment. As illustrated, the error diffusion processing unit 103 includes eight registers X0 to X7 for storing an input image, eight registers E0 to E7 for storing error data, and one register for storing an output binary image. Y and an error diffusion processing gate array similar to the conventional device. Each register is 8 bits,
Both are directly connected to the bus. The error diffusion matrix is configured as shown in FIG. 5, and the binarization error of the pixel of interest “*” is diffused to the peripheral pixels by the coefficient distribution shown in the figure. Here, it is assumed that the image data has 8 bits (256 gradations) for each pixel.

Prior to the subsequent description, the first page mode of the DMA controller will be described with reference to FIG.

Normally, the memory receives the row address and the column address sent from the DRAM controller via the address bus at the timing of (a) shown in FIG. 6 and outputs the data in the memory. However, in the case of accessing continuous addresses in the memory, the row address is not rewritten and only the column address is continuously rewritten, so that the data is output from the memory at the timing of (b) shown in FIG. DRA with a mode that allows
There is an M controller. Such a mode is called a first page mode. Since image data is typically placed on consecutive addresses in memory, the data output rate can be nearly doubled when accessing such data.

In the conventional error diffusion processing, the image data is read pixel by pixel from the main memory into the error diffusion processing section, and the error data generated there is saved in the local memory, while the binarization processing result is converted into one pixel. (1 bit) was output to the main memory. On the other hand, in the embodiment, the following data is read and written using the first page mode every time 8 pixels are processed.

(1) The error data generated by the binarization processing of 8 pixels (data used for the binarization processing of the pixels on the next line, which is conventionally stored in the local memory) is stored in the register E0. Output from E7 to the main memory 102.

(2) Result of binarization processing of 8 pixels (8
Bit = 1 byte) byte-packed into main memory 10
Output to 2.

(3) The next image data is read from the main memory 102 into the registers X0 to X7 in units of 8 pixels.

As a result, the time required for transferring the error data necessary for the binarization processing of 8 pixels (generated during the processing in the previous line) from the main memory 102 as 1-byte data via the bus is set. If 1 unit time is used, 16 (= (1 + 1) × 8) unit time is required to process 8 pixels in the conventional example, but 13 (= 8/2) in the embodiment.
(+ 1 + 8/2 + 8/2) unit time, and since the local memory is not needed, the gate array scale can be small.

Next, details of the error diffusion processing in the embodiment will be described. Here, a case where the error diffusion binarization process is performed using the error diffusion matrix as shown in FIG. However, in FIG. 5, a + b + c + d + e
= 1. Further, the value of the binarization error generated by binarizing a certain pixel ω will be expressed as ER (ω). When the pixel arrangement of the input image is as shown in (a) of FIG. 7, if the pixel of interest is H, the binarization error ER (H) caused by the binarization process of the pixel is , L,
It is diffused into M and N. On the contrary, a part of the binarization error value generated in the pixels B, C, D, F, and G, specifically, ER (B)
× e + ER (C) × d + ER (D) × c + ER (F) ×
b + ER (G) × a is added to the pixel value of pixel H.

In the conventional error diffusion processing, among these values added to the pixel value of the pixel H, the value generated during the processing in the preceding line of the pixel H, that is, ER (B) × e + ER
(C) × d + ER (D) × c is configured to be stored in the FIFO format error buffer after the binarization processing of the pixel D. This value will be expressed as B (H) for the pixel H. Then, when the pixel H of the next line becomes the pixel of interest, its value is read from the error buffer,
The pixel H is binarized after being added to the gray value of the pixel H together with ER (F) × e + ER (G) × d. At this time, at the same time, B (L) (= ER (F) × e + ER (G) × d
+ ER (H) × c) will be stored in the error buffer for later processing of pixel L.

In the embodiment, the error diffusion processing unit performs the same processing as that described above without using the error buffer.
This is performed in pixel units according to the following algorithm. However,
The pixel arrangement of the input image is assumed to be as shown in (b) of FIG.

(1) From the input image data read into the main memory 102, the grayscale values of 8 pixels continuous in the main scanning direction are registered in the register X using the first page mode.
Read from 0 to X7. Here, it is assumed that the pixels C to J shown in FIG. 7B have been read.

(2) The values of B (C) to B (J) generated by the processing on the lines preceding the pixels C to J are read from the main memory 102 into the registers E0 to E7 by using the same fast page mode. .

(3) The value of B (C) in the register E0, the gray value of the pixel C in the register X0, and the ER (A) and ER (B) generated as a result of the processing in the previous pixels A and B. The error diffusion binarization process of the pixel C is performed using (remains in the internal register of the error diffusion process gate array), and the binarization result is written in the 0 bit of the register Y.

(4) At the same time, the ER resulting from this processing
(C) and B using the above ER (A) and ER (B)
(P) (= ER (A) × c + ER (B) × ER (C) ×
a) is obtained and written in the register E0.

(5) The next pixel D is processed. The binarization result is written to the first bit of register Y, and at the same time B
The value of (Q) is calculated and written in the register E1.

(6) Similarly, the pixels E to J are processed. When the binarization processing of the pixel J is completed, the register Y
The binarized result of eight pixels C to J is stored in the register E
The values of B (P) to B (W) are stored in 0 to E7.

(7) The binarization result of the pixels C to J is output from the register Y to the main memory 102.

(8) The values of B (P) to B (W) are output from the registers E0 to E7 to the main memory 102 using the first page mode.

(9) The target pixel group is moved to the next (after pixel K) and the process returns to (1).

By performing such processing, the error diffusion binarization processing of the input image can be performed with the same or shorter processing time as the conventional one and with simpler hardware (because there is no local memory) than the conventional one. It can be performed.

In the above-described embodiment, the error diffusion processing is described as an example, but the present invention is not limited to this, and image processing such as the edge enhancement which needs to refer to the lines before and after the pixel of interest. It is also effective in processing.
That is, the line containing the pixel of interest and the lines before and after it are
A local memory is required by adopting a configuration in which the pixels are read pixel by pixel from the main memory into the image processing unit using the first page mode, and the processing results are similarly written to the main memory using the first page mode in units of 8 pixels. Processing can be performed at high speed.

As described above, according to the first embodiment, in the image processing such as the error diffusion binarization processing in which it is necessary to refer to the pixel values on the lines above and below the target pixel, the DRAM controller is used. By using the first page mode, it is possible to delete the local memory and reduce the gate array scale.

[Second Embodiment] Next, a second embodiment according to the present invention will be described in detail with reference to the drawings.

In the second embodiment, a case where the present invention is applied to a reading unit of a facsimile machine or the like will be described as an example.

A reading unit of a facsimile machine scans an original with a CCD sensor or a line sensor such as a contact image sensor, A / D-converts the output, and converts it into digital multi-valued data of about 6 to 8 bits. . Edge enhancement processing and error diffusion processing are performed on this, and binary image data that represents pseudo halftone is output.

Such an image reading unit requires a line buffer capable of storing multi-valued data of 2 lines for edge enhancement processing and 1-2 lines for storing error data of error diffusion processing.

FIG. 8 is a block diagram showing the structure of such an image reading unit. The operation of the image reading unit will be described below with reference to FIG.

First, the analog image data read by the sensor 301 is converted into digital image data by the A / D converter 302, and the image processing unit 303 performs edge enhancement processing and error diffusion processing. At this time, the RAM 312 is used as a line buffer for image processing.

Next, 2 output from the image processing unit 303 is output.
Value data is serial / parallel converter (S / P) 304
Is converted into parallel data having the same width as the bus 311 and output to the latch 305. When the latch 305 latches the data, the data is output under the control of the DMA controller 306, and the data is the RAM 3 composed of DRAM.
08 is transferred to the line buffer.

Numeral 309 in the figure is a timing controller, which controls signals a, b, and
Outputs c, d, and e. A CPU 307 controls the entire image reading unit.

Next, the edge emphasis processing and the error diffusion processing will be described with reference to FIGS. 9 and 10. First, the edge emphasis processing is performed by replacing E ′ obtained by the following calculation with respect to the target pixel E shown in FIG.

E '= E + 4 * E- (A + C + G + I) Here, in the case of a reading system in which the image scanning is performed from left to right for main scanning and from top to bottom for sub-scanning, the last of the pixels A to I is scanned. The pixel I is input to the image processing unit 303. Therefore, the read data is stored in the line buffer in the RAM 312, the pixels A to H are read from the line buffer, the edge enhancement processing is performed, and the pixel E ′ is output.

Actually, the pixel C → B →
Three shift registers for shifting A, F → E → D, I → H → G are provided inside the image processing unit 303, and the pixel I is set to A /
Generally, the number of accesses to the line buffer is reduced by inputting the pixels C and F from the D converter 302 from the line buffer and shifting the shift register in synchronization with the pixel clock.

In this processing, access to the line buffer per pixel is writing of pixel I and reading of pixels C and F.

The line buffer is a queue buffer for two lines in units of one line.

Next, the error diffusion process will be described with reference to FIG. The error diffusion process is a process that is often used to binarize multi-valued image data to express pseudo halftone. The target pixel E ′ (output of edge enhancement) shown in FIG. 10 is 0 to 255 for 8-bit multi-valued data, for example.
Has a concentration value of. This is binarized, that is, 0 (white) or 2
The value is converted to 55 (black), and the difference from the original value (that is, the density error) is distributed to the surrounding pixels before binarization at a constant ratio and added. Here, for example, 1/3 for each pixel J · N, K ·
Distribute 1/12 to L / M / O. As a result, the density information can be expressed in a macroscopically white / black area ratio.

In the above-described processing, since the processing is sequentially performed in the main scanning direction, it can be configured by an adder and a register in the same line, but in order to store the error distributed to the next line, a line buffer (error buffer) is used. ) Is used. In this process, the error buffer per pixel is accessed once for reading and once for writing.

That is, when both the edge enhancement process and the error diffusion process are performed, the memory is accessed 5 times, that is, 3 times for reading and 2 times for writing for each pixel.

FIG. 11 is a diagram showing the access timing to the above-mentioned memory. That is, the memory is accessed five times in one pixel cycle. Address A,
B is reading from the edge enhancement line buffer, address C is writing to the edge enhancement line buffer, address D is reading from the error buffer, and address E is writing to the error buffer.

In the reading unit having such a configuration, the RAM 30
The capacity of 8 is several kilobytes, an SRAM chip is used, and the A / D converter 302, the image processing unit 303, the serial / parallel converter 304, the latch 305, the timing control unit 309, and the RAM 312 are integrated into one chip. The above functions were realized in.

However, in the above-mentioned configuration, although the DRAM having a low bit unit price is used as the main bus, since the SRAM having a high bit unit price or the RAM in the ASIC is used, the device becomes expensive. It was

The purpose of the second embodiment is to provide an inexpensive image processing apparatus.

FIG. 12 is a block diagram showing the arrangement of the image reading section according to the second embodiment. In the figure, 40
1 is an image sensor, and signal a is an image sensor 40.
1 drive signal. An A / D converter 402 converts an analog output from the image sensor 401 into digital multi-valued data. The signal b is a signal for instructing the A / D converter 402 on the conversion timing. 403
Is a latch and latches the output from the A / D converter 402. The signal f is a signal for instructing the latch 403 to latch. An image processing unit 404 performs edge enhancement processing and error diffusion processing. The signal c is a drive signal for the image processing unit 404. 405 is serial /
It is a parallel converter (S / P) and converts the serial output of the image processing unit 404 into parallel data. The signal d is a drive signal for the serial / parallel converter 405. 40
A latch 6 latches the output of the serial / parallel converter 405 in accordance with the latch timing signal e, and DM
Output under the control of the A controller 407.

Reference numeral 410 denotes a sensor timing control section, which is a signal a which is optimal for driving the sensor from the clock 411.
A signal b and a signal f synchronized with it are output. Also,
The bus right request signal g is made active to the CPU 408, and when the bus access end signal i is received, the bus right request signal g is made inactive. An image processing timing control unit 412 generates a signal c, a signal d, and a signal e from the clock 413 when receiving the bus right request acknowledge signal h, and outputs a bus access end signal i for one pixel. The signal j is sent to the RAM 40 while the image processing unit 404 is acquiring the bus right.
9 are address signals, data signals, and bus control signals. 408 is C for controlling the entire system
It is a PU and has a general bus right transfer function. When the bus right request signal g becomes active, the bus right request acknowledge signal h is output after the end of the bus cycle being executed, the bus access is stopped, and the bus right request is issued. When the signal g becomes inactive, bus access is restarted.

Next, the operation of the second embodiment will be described with reference to FIG. First, the sensor timing controller 410 uses the signals a and b to detect the sensor 40.
1. Drive the A / D converter 402, and use the signal f to A / D
Latch 4 of digital multi-level data output of converter 402
Latch to 03. Here, the sensor timing control unit 410 activates the signal g, and requests the bus right to the CPU 408. As a result, in the CPU 408,
When the bus cycle being executed ends, the bus right request acknowledge signal h is activated.

Next, when the image processing timing control section 412 receives the signal h, it outputs the drive signal c to the image processing section 404, and the image processing section 404 starts processing the data held in the latch 403. As a result, addresses A to E as shown in FIG. 13 are output as the signal j, and the line buffers in the RAM 409 are sequentially accessed. At this time, the response time of the signal h with respect to the signal g is not constant because it depends on the bus cycle being executed at the output time of the signal h, but since the input data of the image processing unit 404 is latched by the latch 403, there is no problem. Processing is performed.

That is, in the above configuration, since the RAM connected to the main bus is accessed in synchronization with the acknowledge signal from the CPU in response to the bus right request, a line buffer should be provided in the RAM connected to the main bus. it can.

After that, when the access to the line buffer is finished, the image processing timing control section 412 outputs the bus access end signal i, and the sensor timing control section 410 which received the signal makes the signal g inactive. When the signal g becomes inactive, the CPU 408 inactivates the bus right request acknowledge signal h.

At this time, in a normal CPU, there is a delay from when the bus right request signal g becomes inactive to when the bus right request acknowledge signal h becomes inactive. This period is an invalid bus period in which neither the reading unit nor the CPU uses the bus, which causes a decrease in the processing speed of the entire system. Therefore, in the second embodiment, the RAM access is performed five times (for one pixel) by acquiring the bus right once to reduce the invalid bus period.

Next, the output of the image processing unit 404 is sent to the serial / parallel converter 405, collected into bits for the bus width, latched in the latch 406, and then transferred to the RAM 409 under the control of the DMA controller 407. It
For example, the output transfer from the latch 406 has a bus width of 16
If it is a bit, it is once in 16 pixels.

[Modification] FIG. 14 is a block diagram showing a modification of the second embodiment. The same parts as those in FIG. 12 are designated by the same reference numerals, and the description thereof will be omitted. As shown
In this modification, the latch 403 shown in FIG.
This is a buffer 501. Further, the signal k is a FIFO buffer control signal. If a FIFO buffer having a storage capacity of n pixels is used, the image processing unit 404 can continuously perform the processing of n pixels, can further reduce the invalid bus period, and cause a CPU cost factor. Can be reduced.

When a DRAM is used as the RAM 409, a high-speed page mode (fast
page mode) and EDO mode (extended data out mod
By using e), the bus occupancy period of the image processing unit 404 can be shortened, and the factor of CPU cost increase can be reduced.

As described above, it is not necessary to provide a high bit unit price SRAM or RAM in the ASIC in the image processing unit.
An inexpensive memory such as DRAM connected to the system bus can be used as a buffer memory for image processing,
An inexpensive image processing unit can be provided.

Even when the present invention is applied to a system composed of a plurality of devices (eg, host computer, interface device, reader, printer, etc.), a device composed of one device (eg, copier, facsimile). Device).

Further, an object of the present invention is to supply a storage medium having a program code of software for realizing the functions of the above-described embodiments to a system or apparatus, and to supply the computer (CPU or MP) of the system or apparatus.
It goes without saying that U) is also achieved by reading and executing the program code stored in the storage medium.

In this case, the program code itself read from the storage medium realizes the function of the above-described embodiment, and the storage medium storing the program code constitutes the present invention.

As a storage medium for supplying the program code, for example, a floppy disk, a hard disk, an optical disk, a magneto-optical disk, a CD-ROM, a CD
-R, a magnetic tape, a nonvolatile memory card, a ROM, or the like can be used.

Moreover, not only the functions of the above-described embodiments are realized by executing the program code read by the computer, but also the OS (operating system) running on the computer based on the instructions of the program code. It is needless to say that this also includes a case where the above) performs a part or all of the actual processing and the processing realizes the functions of the above-described embodiments.

Further, after the program code read from the storage medium is written in the memory provided in the function expansion board inserted in the computer or the function expansion unit connected to the computer, based on the instruction of the program code, It goes without saying that a case where the CPU provided in the function expansion board or the function expansion unit performs a part or all of the actual processing and the processing realizes the functions of the above-described embodiments is also included.

[0081]

As described above, according to the present invention,
Image processing can be performed at high speed without the need for a local memory.

[0082]

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a configuration of an image processing apparatus according to a first embodiment.

FIG. 2 is a block diagram showing a configuration of an image processing apparatus in a conventional example.

3 is a block diagram in which a main memory replaces the local memory shown in FIG.

FIG. 4 is an error diffusion processing unit 103 according to the first embodiment.
It is a figure which shows the structure of.

FIG. 5 is a diagram showing a configuration of an error diffusion matrix in the first embodiment.

FIG. 6 is a diagram showing an access to a normal memory and an access in a first page mode of a DRAM controller.

FIG. 7 is a diagram showing an arrangement of pixels of an input image according to the first embodiment.

FIG. 8 is a block diagram showing a configuration of a general image reading unit.

FIG. 9 is a diagram for explaining edge enhancement processing.

FIG. 10 is a diagram for explaining error diffusion processing.

FIG. 11 is a diagram showing an access timing to a memory.

FIG. 12 is a block diagram showing a configuration of an image reading unit according to a second embodiment.

FIG. 13 is a diagram for explaining the operation in the second embodiment.

FIG. 14 is a block diagram showing a modified example of the second embodiment.

[Explanation of symbols]

 101 CPU 102 Main Memory 103 Error Diffusion Processing Unit 104 DMA Controller 105 I / O Port 106 Other Interface 107 Bus 108 Scanner / Printer 401 Sensor 402 A / D Converter 403 Latch 404 Image Processing Unit 405 Serial / Parallel Converter 406 Latch 407 DMA Controller 408 CPU 409 RAM 410 Sensor timing control unit 411 clock 412 Image processing timing control unit 413 clock

Claims (11)

[Claims] 1. A memory means, comprising: image processing means for processing image data; memory means for storing image data processed by the image processing means; and control means for controlling access to the memory means. An image processing apparatus characterized in that a first page mode of a DMA controller is used to access the memory. 2. Intermediate data generated in the process of image processing is stored in the memory means from the image processing means by using the first page mode, and similarly read out from the memory means by using the first page mode. The image processing device according to claim 1, wherein the image processing device is transferred to a means and used for image processing. 3. When the data is transferred from the image processing means to the memory means, the binarized results of N pixels are combined into 1 word (where 1 word = N bits) and then transferred. The image processing apparatus according to claim 2. 4. The image processing apparatus according to claim 1, wherein the image processing means is an error diffusion process for performing a binarization process on image data by an error diffusion method. 5. The image processing apparatus according to claim 1, wherein the image processing means is edge enhancement processing for performing edge enhancement on image data. 6. An image processing means for processing image data, a memory means for storing image data processed by said image processing means, and a control means for controlling access to said memory means, each means comprising: An image processing apparatus connected to a system bus, wherein a part of the memory means is used as a buffer for image processing. 7. The image processing apparatus according to claim 6, wherein the image processing unit detects that the bus use right has been acquired from the control unit, and accesses the memory unit via a system bus. . 8. The image processing apparatus according to claim 7, wherein the memory means is accessed a plurality of times with one bus acquisition right. 9. The apparatus according to claim 8, further comprising image reading means connected to the image processing means, and data holding means provided between an output of the image reading means and an input of the image processing means.
The image processing apparatus according to any one of the preceding claims. 10. An image processing step of processing image data, a storage step of storing image data processed in the image processing step, and a control step of controlling access to the storage step, An image processing method, characterized in that a first page mode of a DMA controller is used for access in a process. 11. An image processing step of processing image data, a storage step of storing the image data processed in the image processing step in a memory, and a control step of controlling access to the memory, An image processing method, wherein the memory is connected to a system bus and a part of the memory is used as a buffer for image processing.