JPH09326427A - Semiconductor substrate and manufacturing method of semiconductor integrated circuit device using the substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an N-type semiconductor substrate and a manufacturing method of a semiconductor integrated circuit device using the substrate capable of assessment of heavy metal contamination by the SPV method (surface light electromotive force). SOLUTION: A semiconductor substrate 1 is used as a N-type semiconductor substrate and contains lower concentration of boron used for an assessment of iron contamination than the concentration of the above-mentioned N-type impurity and is capable of assessment of iron contamination by the SPV method. A method of manufacturing the semiconductor integrated circuit device has a process of formation of a plurality of semiconductor elements in the semiconductor region of the above-mentioned semiconductor substrate 1 capable of assessment of iron contamination by an SPV method.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor substrate and a method of manufacturing a semiconductor integrated circuit device using the same, and more particularly, an N-type semiconductor substrate capable of performing heavy metal contamination evaluation by the SPV method and a semiconductor using the same. The present invention relates to a technique effectively applied to a manufacturing method of an integrated circuit device.

[0002]

The present inventor has studied a method of manufacturing a semiconductor integrated circuit device. The following is the technique examined by the present inventor, and the outline thereof is as follows.

In a method of manufacturing a semiconductor integrated circuit device,
M using a P-type semiconductor substrate containing boron (B)
OSFET (Metal Oxide Semiconductor Field Effect)
Semiconductor devices such as transistors are formed by wafer processing.

In this case, a silicon oxide film, which is a manufacturing process of a semiconductor integrated circuit device, is formed by CVD (chemical vapor deposition).
of the semiconductor element in the semiconductor integrated circuit device due to the iron contamination due to the contamination of heavy metals in the wafer processing such as the formation by the ition) method. It is a cause of deterioration of the physical characteristics.

Therefore, evaluation of heavy metal contamination is carried out by using various physical property inspection methods. At that time, X-ray fluorescence spectroscopy or DLTS (Deep Level Transient Spectroscopy)
However, there is a problem in that it is necessary to form a pn junction on the semiconductor substrate, and the semiconductor substrate may be damaged or destroyed. Therefore, it has been noted that heavy metal contamination evaluation is performed by a surface photovoltaic (hereinafter referred to as SPV) method that does not require formation of a pn junction on a semiconductor substrate and that does not damage or destroy the semiconductor substrate. .

The SPV method is a method of recording a photoelectromotive force generated when an optical probe is scanned on a semiconductor substrate or the like as a two-dimensional image. When a P-type semiconductor substrate is used, Fe is used.
It is possible to evaluate iron contamination in a P-type semiconductor substrate by using the shallow donor level formed by the −B pair. In the field of semiconductor manufacturing equipment, the use of stainless steel is widespread, and it is considered to be most meaningful to evaluate iron, which is the main component of stainless steel, as an evaluation of heavy metal contamination.

[0007] Documents relating to the manufacturing process of a semiconductor integrated circuit device provided with a MOSFET include, for example, 1
On December 15, 990, there is one described in "Illustrated Super LSI Engineering" p117 to p135 by W. Mali, published by Keigaku Shuppan Co., Ltd.

[0008]

However, in the above-described method for manufacturing the semiconductor integrated circuit device, the P-type semiconductor substrate containing boron is used, and the iron contamination evaluation can be performed by the SPV method. However, the present inventor has found a problem that the iron contamination evaluation cannot be performed by the SPV method in the method for manufacturing the semiconductor integrated circuit device using the N-type semiconductor substrate containing phosphorus (P). .

That is, in the method of manufacturing the semiconductor integrated circuit device using the N-type semiconductor substrate containing phosphorus (P), since Fe is not contained in the N-type semiconductor substrate, the Fe-B pair is contained in the N-type semiconductor substrate. Since a shallow shallow donor level is not formed, it is not possible to evaluate iron contamination in the N-type semiconductor substrate by the SPV method.

Therefore, since it is not possible to evaluate the iron contamination in the N-type semiconductor substrate by the SPV method, the quality control by the iron contamination evaluation (hereinafter referred to as QC).
It is not possible to take early countermeasures against defects by evaluating
There is a problem that the manufacturing yield of semiconductor integrated circuit devices cannot be improved.

The object of the present invention is to evaluate heavy metal pollution by SPV.
An object of the present invention is to provide an N-type semiconductor substrate and a method for manufacturing a semiconductor integrated circuit device using the same, which can be performed by a method.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0013]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the semiconductor substrate of the present invention is an N-type semiconductor substrate containing N-type impurities such as phosphorus, and boron for evaluating iron contamination is contained in a lower concentration than the N-type impurities. Therefore, iron contamination can be evaluated by the SPV method.

Further, the method for manufacturing a semiconductor integrated circuit device of the present invention includes the step of forming a plurality of semiconductor elements in the semiconductor region of the semiconductor substrate described above, and the semiconductor substrate can be evaluated for iron contamination by the SPV method. It is possible.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and redundant description will be omitted.

(First Embodiment) FIG. 1 is a sectional view showing a semiconductor substrate according to an embodiment of the present invention. FIG.
3 is a graph showing an impurity concentration distribution in the semiconductor substrate in FIG. 1. FIG. The semiconductor substrate of this embodiment will be described with reference to FIGS. 1 and 2.

The semiconductor substrate 1 of the present embodiment is in the form of a wafer having a thickness of several hundreds of μm in order to have sufficient mechanical strength, and is made of a silicon single crystal as a material.

Further, the semiconductor substrate 1 of this embodiment is N
Phosphorus (P) is contained as a type impurity, and the phosphorus concentration 2 is 1 × 10 ¹⁶ pieces / cm ³ . Furthermore, the semiconductor substrate 1 of the present embodiment contains boron (B) for performing iron contamination evaluation, and the boron concentration 3 is 1 × 10 ^14.
The number of pieces / cm ³ .

The method for manufacturing the semiconductor substrate 1 according to the present embodiment uses a single crystal manufacturing apparatus and a cutting apparatus using the Czochralski method or the floating zone method to evaluate the contamination of phosphorus and iron as N-type impurities. For performing iron implantation by implanting boron into the N-type semiconductor substrate using an ion implantation method, or an aspect of forming an N-type semiconductor substrate using a silicon single crystal containing boron for performing A mode of forming an N-type semiconductor substrate containing boron can be adopted.

The semiconductor substrate 1 of the present embodiment is N
Although phosphorus is used as the type impurity, it is possible to adopt a mode in which N type impurities such as arsenic (As) are used.

Further, the semiconductor substrate 1 of the present embodiment is N
The phosphorus concentration 2 as a type impurity is 1 × 10 ¹⁶ pieces / cm ³ , the boron concentration 3 is 1 × 10 ¹⁴ pieces / cm ³ , and the boron concentration 3 is two orders of magnitude lower than the phosphorus concentration 2. According to the experimental results of the present inventor, it has been found that the concentration of boron may be one to two orders of magnitude lower than the concentration of N-type impurities in the semiconductor substrate 1.

According to the semiconductor substrate 1 of this embodiment, N
In addition to containing the type impurities, boron for performing the iron contamination evaluation is contained at a lower concentration than the N-type impurities, and the iron contamination evaluation can be performed by the SPV method.

That is, in the wafer processing step of manufacturing the semiconductor substrate 1 itself or a semiconductor integrated circuit device using the semiconductor substrate 1, a wafer processing such as forming a heavy metal such as iron in the atmosphere or a silicon oxide film by the CVD method. In some cases, heavy metal may be contaminated therein, and iron may particularly infiltrate into the semiconductor substrate 1. The iron contamination may cause deterioration in electrical characteristics of semiconductor elements in the semiconductor integrated circuit device. However, since the semiconductor substrate 1 of the present embodiment contains boron that can be used for iron contamination evaluation, the shallow donor level created by the Fe—B pair contained in the semiconductor substrate 1 is used to evaluate iron contamination. It can be performed.

As a result, according to the semiconductor substrate 1 of the present embodiment, since the iron contamination evaluation can be performed by the SPV method, it is not necessary to form a pn junction for the iron contamination evaluation and the semiconductor substrate 1 is destroyed. The adverse effects such as can be prevented.
In addition, QC based on the iron contamination evaluation and early failure countermeasures based on the iron contamination evaluation can be taken, and the manufacturing yield of products such as semiconductor integrated circuit devices can be improved.

(Embodiment 2) FIG. 3 shows an SOI (Siliconon) having a semiconductor substrate according to another embodiment of the present invention.
It is sectional drawing which shows an (Insulator) base | substrate. Using FIG.
An SOI substrate having the semiconductor substrate of this embodiment will be described.

The SOI substrate 4 of the present embodiment has a semiconductor substrate 7 for forming an element of about 1 μm formed on the base semiconductor substrate 5 with the insulating film 6 interposed therebetween, which is sufficient. In order to have mechanical strength, the base semiconductor substrate 5 is used to form a wafer having a thickness of several hundred μm, and the base semiconductor substrate 5 and the element forming semiconductor substrate 7 are made of silicon. It is made from crystals.

Further, the semiconductor substrate 5 and the semiconductor substrate 7 of the present embodiment contain phosphorus as an N-type impurity, and the phosphorus concentration 2 is 1 × 10 ¹⁶ pieces / cm ³ . Furthermore, the semiconductor substrate 5 and the semiconductor substrate 7 of the present embodiment
Contains boron for the evaluation of iron pollution, and the boron concentration is 1 × 10 ¹⁴ / cm ³ .

Although phosphorus is used as the N-type impurity in the semiconductor substrate 5 and the semiconductor substrate 7 of the present embodiment, an N-type impurity such as arsenic may be used.

Further, the semiconductor substrate 5 and the semiconductor substrate 7 of the present embodiment have a phosphorus concentration of 1 × 1 as an N-type impurity.
0 ¹⁶ pieces / cm ³ and the boron concentration is 1 × 10 ¹⁴ pieces / c
m ³ and the boron concentration is two orders of magnitude lower than the phosphorus concentration, but according to the experimental results of the present inventor, the boron concentration is 1 concentration lower than the N-type impurity concentration of the semiconductor substrate 5 and the semiconductor substrate 7. It has been found that a concentration of ~ 2 orders of magnitude lower is sufficient.

SOI having the semiconductor substrate of this embodiment
According to the base 4, the semiconductor substrate 5 and the semiconductor substrate 7 are N
Type impurities are contained, and boron for performing iron contamination evaluation is contained in these semiconductor substrates 5 and 7 in a concentration lower than that of the N type impurities. Therefore, iron contamination evaluation can be performed by the SPV method. it can.

Further, according to the SOI substrate 4 having the semiconductor substrate of the present embodiment, since the base semiconductor substrate 5 contains boron for iron contamination evaluation,
Since the quantification of iron contamination in the semiconductor substrate 5 for the base of the SOI substrate 4 can be evaluated at the actual product level, the QC can be improved.

As a result, according to the SOI substrate 4 having the semiconductor substrate of the present embodiment, the iron contamination evaluation can be performed by the SPV method, so that the semiconductor substrate 5 for base and the semiconductor substrate 7 for element formation can be used. P for evaluating iron pollution
It is not necessary to form an n-junction and it is possible to prevent adverse effects such as destruction of the semiconductor substrates 5 and 7. In addition, QC based on the iron contamination evaluation and early failure countermeasures based on the iron contamination evaluation can be taken, and the manufacturing yield of products such as semiconductor integrated circuit devices can be improved.

In the SOI substrate 4 having the semiconductor substrate of this embodiment, both the base semiconductor substrate 5 and the element forming semiconductor substrate 7 contain boron for iron contamination evaluation. There is a semiconductor substrate 5 for the base
Alternatively, it is possible to adopt a mode in which only one of the semiconductor substrates 7 for element formation contains boron for iron contamination evaluation.

(Third Embodiment) FIGS. 4 to 9 are schematic cross-sectional views showing a manufacturing process of a semiconductor integrated circuit device using a semiconductor substrate according to another embodiment of the present invention. The method for manufacturing the semiconductor integrated circuit device according to the present embodiment will be described with reference to FIG.

First, the semiconductor substrate 1 of the first embodiment described above is prepared, iron contamination is evaluated by the SPV method, and the semiconductor substrate 1 having less iron contamination than the evaluation standard is selected. Then, a field insulating film 8 made of a silicon oxide film is formed in the element isolation region, which is a selective region on the surface of the selected semiconductor substrate 1, by using a thermal oxidation process. Although not shown, a channel stopper film for preventing inversion is formed under the field insulating film 8 (FIG. 4).

Next, in the manufacturing process described above, SPV is used.
The iron contamination of the semiconductor substrate 1 is evaluated by the method, and if the iron contamination is larger than the evaluation standard, the manufacturing process is reviewed to reduce the iron contamination, and the production yield is prevented from decreasing due to the iron contamination. are doing. Further, in various manufacturing processes described later, the iron contamination evaluation of the semiconductor substrate 1 is performed by the SPV method as needed, and when the iron contamination is larger than the evaluation standard, the manufacturing process is reviewed to reduce the iron contamination. After that, the post-process is performed to prevent the production yield from being lowered due to iron contamination.

Next, a gate insulating film 9 made of silicon oxide is formed in the active region surrounded by the field insulating film 8, and a gate electrode 10 made of polycrystalline silicon is formed on the gate insulating film 9 by using a CVD apparatus. To form. The gate electrode 10 is formed by sequentially depositing an insulating film 11 made of a polycrystalline silicon film and a silicon oxide film on the semiconductor substrate 1 and sequentially etching these. After that, the sidewall insulating film 12 made of a silicon oxide film is formed on the sidewall of the gate electrode 10. Next, P-type impurities such as boron are ion-implanted into the semiconductor substrate 1 to form P-type semiconductor regions 13 serving as a source and a drain (FIG. 5).

After that, an insulating film 14 made of a silicon oxide film or the like is formed on the semiconductor substrate 1, a contact hole is formed in the selective region, and a contact electrode 15 is formed in that region (FIG. 6). .

Next, after the insulating film 16 made of a silicon oxide film or the like is formed on the semiconductor substrate 1, through holes are formed in the selective regions (FIG. 7).

In the manufacturing process of the semiconductor integrated circuit device described above, the p-channel MOSFET is formed on the semiconductor substrate 1, but the p-channel MOSFET is formed on the semiconductor substrate 1.
It is possible to adopt a mode in which various semiconductor elements such as n-channel MOSFETs, bipolar transistors, and capacitive elements other than the above are formed.

Next, after the barrier metal film 17 made of titanium is formed on the semiconductor substrate 1 by the sputtering method, the metal film 18 made of aluminum is formed on the surface of the barrier metal film 17 by the sputtering method. Form. After that, a barrier metal film 19 made of titanium is formed on the metal film 18 by using a sputtering method. In this case, the barrier metal film 17 and the barrier metal film 19
May be in the form of a refractory metal film using an alloy such as titanium, tungsten, molybdenum or TiW. Further, the metal film 18 may be in the form of a metal film using copper or gold (FIG. 8).

After that, an unnecessary portion of the barrier metal film 17 / metal film 18 / barrier metal film 19 as a wiring layer is removed by using a photolithography technique and a selective etching technique to form a wiring pattern (FIG. 9). Next, after a multilayer wiring layer is formed as necessary, a passivation film (not shown) is formed, thereby completing the manufacturing process of the semiconductor integrated circuit device.

According to the method of manufacturing the semiconductor integrated circuit device of the present embodiment, since the semiconductor substrate 1 of the first embodiment described above is used, SP can be used in various manufacturing steps.
Since the iron pollution evaluation can be performed by the V method as needed, when the iron pollution is larger than the evaluation standard, the manufacturing process is reviewed to reduce the iron pollution, and the manufacturing yield is increased by the iron pollution. It is possible to prevent the deterioration.

According to the method of manufacturing the semiconductor integrated circuit device of the present embodiment, since the semiconductor substrate 1 of the first embodiment described above is used, the iron contamination evaluation can be performed by the SPV method. It is not necessary to form a pn junction for evaluating iron contamination on the semiconductor substrate 1, and it is possible to prevent adverse effects such as breakage of the semiconductor substrate 1. Further, QC based on the iron contamination evaluation and early failure countermeasures based on the iron contamination evaluation can be taken, and the manufacturing yield of the semiconductor integrated circuit device can be improved.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the scope of the invention. Needless to say, it can be changed.

For example, the method of manufacturing the semiconductor integrated circuit device according to the third embodiment described above is similar to the semiconductor substrate 1 according to the first embodiment.
The SOI substrate 4 according to the second embodiment
It can be applied to a method of manufacturing a semiconductor device such as a semiconductor integrated circuit device using the.

[0048]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1). According to the semiconductor substrate of the present invention, N
Type impurities are contained, and boron for iron contamination evaluation is contained in a lower concentration than the N type impurities, and iron contamination evaluation can be performed by the SPV method.

(2). SO having semiconductor substrate of the present invention
According to the I substrate, the semiconductor substrate for base and the semiconductor substrate for element formation contain N-type impurities, and boron for iron contamination evaluation is contained at a lower concentration than the N-type impurities. Therefore, iron contamination can be evaluated by the SPV method.

An SOI having the semiconductor substrate of the present invention
According to the substrate, since the semiconductor substrate for base contains boron for iron contamination evaluation, the quantification of iron contamination in the semiconductor substrate for base of the SOI substrate can be evaluated at the actual product level. QC can be improved.

As a result, according to the SOI substrate having the semiconductor substrate of the present embodiment, the iron contamination evaluation can be performed by the SPV method. Therefore, the iron contamination evaluation is performed on the base semiconductor substrate and the element forming semiconductor substrate. It is not necessary to form a pn junction for the purpose of protecting the semiconductor substrate from being adversely affected. In addition, QC based on the iron contamination evaluation and early failure countermeasures based on the iron contamination evaluation can be taken, and the manufacturing yield of products such as semiconductor integrated circuit devices can be improved.

(3). According to the method for manufacturing a semiconductor integrated circuit device using the semiconductor substrate of the present invention, the iron contamination evaluation can be performed by the SPV method in various manufacturing steps as needed, so that the iron contamination is larger than the evaluation standard. First, it is possible to prevent the production yield from decreasing due to iron pollution by reviewing the manufacturing process and reducing iron pollution.

(4). According to the method for manufacturing a semiconductor integrated circuit device using a semiconductor substrate of the present invention, it is possible to evaluate iron contamination by the SPV method in various manufacturing steps. Therefore, it is possible to form a pn junction for evaluating iron contamination on a semiconductor substrate. In addition to being unnecessary, it is possible to prevent adverse effects such as breakage of the semiconductor substrate. Further, QC based on the iron contamination evaluation and early failure countermeasures based on the iron contamination evaluation can be taken, and the manufacturing yield of the semiconductor integrated circuit device can be improved.

[Brief description of drawings]

FIG. 1 is a sectional view showing a semiconductor substrate according to an embodiment of the present invention.

FIG. 2 is a graph showing an impurity concentration distribution in the semiconductor substrate in FIG.

FIG. 3 is a sectional view showing an SOI base having a semiconductor substrate according to another embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device using a semiconductor substrate according to another embodiment of the present invention.

FIG. 5 is a schematic cross sectional view showing a manufacturing process of a semiconductor integrated circuit device using a semiconductor substrate according to another embodiment of the invention.

FIG. 6 is a schematic cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device using a semiconductor substrate according to another embodiment of the present invention.

FIG. 7 is a schematic cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device using a semiconductor substrate according to another embodiment of the present invention.

FIG. 8 is a schematic cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device using a semiconductor substrate according to another embodiment of the present invention.

FIG. 9 is a schematic cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device using a semiconductor substrate according to another embodiment of the present invention.

[Explanation of symbols]

 1 semiconductor substrate 2 phosphorus concentration 3 boron concentration 4 SOI substrate 5 semiconductor substrate 6 insulating film 7 semiconductor substrate 8 field insulating film 9 gate insulating film 10 gate electrode 11 insulating film 12 sidewall insulating film 13 semiconductor region 14 insulating film 15 contact electrode 16 Insulating film 17 Barrier metal film 18 Metal film 19 Barrier metal film

Claims (7)

[Claims] 1. A semiconductor substrate containing N-type impurities, wherein boron for evaluating heavy metal contamination is contained in a concentration lower than that of the N-type impurities. 2. The semiconductor substrate according to claim 1, wherein the semiconductor substrate is a semiconductor substrate for forming a plurality of semiconductor elements forming a semiconductor integrated circuit device. 3. The semiconductor substrate according to claim 1, wherein the semiconductor substrate is a semiconductor substrate for forming a semiconductor element on an SOI substrate. 4. The semiconductor substrate according to claim 1, wherein the semiconductor substrate is a base semiconductor substrate in an SOI substrate. 5. The semiconductor substrate according to claim 1, wherein the concentration of boron is less than the concentration of the N-type impurity by 1 to 2 digits. 6. A method for manufacturing a semiconductor integrated circuit device, comprising the step of forming a plurality of semiconductor elements in a semiconductor region of the semiconductor substrate according to claim 1. 7. The method of manufacturing a semiconductor integrated circuit device according to claim 6, comprising a step of evaluating heavy metal contamination of the semiconductor substrate by an SPV method.