JPH09326197A - Nonvolatile semiconductor storage device and bit line charging method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the time required for reading and writing data by providing a temporary storage circuit which accumulates data for writing to and reading from memory and a voltage supplying circuit which supplies voltages corresponding to multi-values to bit lines for each bit line. SOLUTION: Each bit line is provided with a temporary storage circuit which accumulates data to be written to and read out from memory cells and a voltage supplying the potentials corresponding to multivalues to bit lines. In one unit block, a sense amplifier which is connected with a cell array including multi-value storable nonvolatile memory cells through bit lines is connected with a temporary storage circuit. This circuit is connected with an I/O line and the voltage supplying means, which is connected with bit lines. By this, multi-value data can be read out at one time from multi-value storable nonvolatile memory cells connected to one word line and thereby readout time can be saved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device, and more particularly to a non-volatile semiconductor memory device capable of simultaneously reading multi-valued non-volatile memory elements connected to the same word line. .

[0002]

2. Description of the Related Art Non-volatile semiconductor memory devices have the advantage that the data stored in the memory are not lost even when the power is turned off. Therefore, the demand for portable telephones, pagers and the like has greatly increased. A flash memory, which is a non-volatile semiconductor memory device that can be electrically collectively erased, can configure a memory cell with one transistor, unlike a two-transistor byte type non-volatile semiconductor memory device. It is possible to reduce the size of the disk, and it is expected to be used as a substitute for a large-capacity magnetic disk.

In these non-volatile semiconductor memory devices, memory cells composed of MOS transistors having a floating gate are arranged in a matrix to form a memory cell, and a tunnel phenomenon or impact ionization phenomenon is used to make the floating gate a floating gate. Electrons are injected, the threshold value of the MOS transistor is changed, and information is stored by the change.
Further, the electrons injected into the floating gate are confined in the floating gate due to the energy barrier. Therefore, the information once stored in the floating gate is not lost, and it functions as a nonvolatile memory device.

Further, in the nonvolatile semiconductor device, data is stored by setting the threshold level of a MOS transistor forming a memory cell to a binary value of a high state (a state where data is accumulated) and a low state (an erased state). There are two types, one is for storing data and the other is for storing data with the threshold level being multi-valued (three or more).

Here, a nonvolatile semiconductor memory device capable of multi-valued storage will be described taking a NAND flash memory as an example. FIG. 34 shows a main block diagram of the nonvolatile semiconductor memory device. The nonvolatile semiconductor memory device 993 is composed of a row decoder 994, a column decoder 995, an I / O buffer, a sense amplifier block 997, a column gate transistor group 998, and a memory cell array 999.

A memory cell array 999 in which NAND type memory cells are arranged in a matrix has thousands of word lines and thousands of bit lines. One end of the word line is connected to the row decoder 994, and the row decoder 994 selects the word line based on an external address signal. Further, one end of the bit line has a column gate transistor group 99.
8 and the column gate transistor group 998 is
A column decoder 99 based on an external address signal
The signal decoded by 5 is received, and the selected bit line is connected to the sense amplifier block 997. The signal sense-amplified by the sense amplifier block 997 is I / O.
The data is transmitted to the buffer 996, and the I / O buffer 996 interfaces with the outside of the nonvolatile semiconductor memory device 993.

Next, FIG. 36 shows a memory cell array 999,
Column gate transistor group 998, column decoder,
A detailed diagram of the row decoder portion is shown. Where BL1
BL4 bit line, WL1 to WL5 word lines, 99
Reference numeral 2 denotes a NAND type memory cell.

FIG. 37 shows a detailed view of the NAND type memory cell 992. One NAND memory cell 992
Are memory cells MC11 to MC18 connected in series eight
Each of the memory cells MC11 to MC18 has a floating gate for accumulating electrons. In addition, the memory cells MC11 to MC11 connected in series
One end of MC18 is connected to the bit line BL1 via the first selection transistor SGD1, and the other ends of the memory cells MC11 to MC18 connected in series are connected to the common source line via the second selection transistor SGS1. Has been done. All NAND memory cells 992 are configured as described above.

FIG. 38 is a sectional view of the NAND type memory cell 992 on the integrated circuit. A P-WELL is formed on an N-type semiconductor substrate (N-SUBSTRATE), and memory cells MC11 to MC1 are formed on this P-WELL.
8. Select transistors SGS1 and SGD1 are formed. The diffusion layer N + used as the source / drain of these transistors is shared with the adjacent transistor, and the other diffusion layer of the selection transistor SGD1 is connected to the bit line.

Next, the write operation of this nonvolatile semiconductor memory device will be described with reference to FIG. Here, it is assumed that data is written only in the memory cell MC11 shown in FIG.

First, the bit line BL1 is set to 0 V in a state where charges are not accumulated in all the memory cells.
Then, the bit line BL2 is applied to 10V. Next, the non-selected word lines WL1C to WL1I are applied to 12V, the selected word line WL1B is applied to the write voltage (for example, 20V), the word line WL1A of the selection transistor is applied to 12V, and the WL1L is applied to 0V. Therefore, the memory cells MC11 to MC1
8. The selection transistor SGD1 is turned on and the selection transistor SGS1 is turned off.

Since the select transistor SGS1 is in the OFF state, in the memory cell MC11, the memory cell MC
Since the potential of the source terminal S of 11 becomes a floating state and a write voltage (for example, 20 V) is applied between the control gate CG and the drain terminal D, electrons are applied to the floating gate FG via the gate insulating film 990. Is injected (see FIG. 39 (1)). That is, data is stored in the memory cell MC11, and this state is called an accumulated state.

The accumulated state will be further described with reference to FIG. 39 (2). FIG. 39 (2) shows a threshold number distribution diagram, showing a case of four-value writing. As described above, by applying a high voltage (write voltage) between the control gate CG and the drain terminal D of the memory cell, electrons are injected into the floating gate FG, and the threshold value of this memory cell rises. . That is, the threshold value transits from the erased state "0" to any of the accumulated states "1", "2", and "3". Further, which one of the storage states “1”, “2”, and “3” transitions to depends on the magnitude of the voltage applied between the control gate and the drain terminal. here,
It is assumed that the state of "2" data has been reached.

Further, the threshold values of all the memory cells used in the flash memory do not rise to the same extent, but vary depending on the individual memory cells. Therefore, the threshold value of the memory cells in the storage state has a certain number distribution L1 to L4. For example, the threshold range L1 for "0" data is -2.5V to -0.5V, the threshold range L2 for "1" data is 0.5V to 1.5V, "2". "The threshold value range L3 for data is 2.5 V to 3.5 V,
The threshold value range L3 for "3" data is 4.5V to
Assume 5.5V.

Further, in MC12 to MC18, since the control gate CG is applied to 12V, a voltage of 12V is applied between the control gate CG and the drain terminal D, but it is low to cause the tunnel phenomenon. Since it is a voltage, electrons are not injected into the floating gate FG. That is, no data is stored and the erased state remains "0".

Further, in the memory cell MC21, 10V (20V) is provided between the control gate CG and the drain terminal D.
-10V) is applied to the memory cells MC22 to MC28.
Between the control gate CG and the drain terminal D of 2V (12
V-10V) is applied. Therefore, the memory cell M
No electrons are injected into the floating gates FG of C21 to MC28. That is, it remains in the erased state.

The voltage (10 V) applied to the bit line BL2 is particularly called a write inhibit voltage. As described above, the storage state is set only in the predetermined memory cell MC11, and the write operation is completed.

Next, the read operation will be described.
Now, assume that the memory cell MC11 is in the state of "2" data. The word line WL1B is set to 4V and the memory cell MC11
Select Further, the word lines WL1A and WL1J and the non-selected word lines WL1C to WL1I are applied to 12V, and the memory cells MC12 to MC18, MC22 to MC28, the selection transistors SGD1, SDG2, SGS1 and SGS2 are applied.
Turn on.

Further, the bit lines BL1 and BL2 are discharged to 0V and then brought into a floating state. Further, the common source line potential VS is set to 12V. Word select line WL1B
Potential (4V) is a threshold voltage (2.5V to 3.5V)
Since it is higher, the memory cell in the storage state of "2" data is turned on. Therefore, the bit line BL1 is charged to a potential obtained by subtracting the threshold voltage of the memory cell MC11 from the common source line potential VS.

In this case, in the memory cell MC11, the threshold voltage of the memory cell MC11 is 2.5V to 3.5V.
Since it is V ("2" state, see FIG. 39 (2)), the bit line is charged to a potential in the range of 2.5V to 3.5V. The change in the potential of the bit line is sensed by the sense amplifier, and sense amplification is performed.

Further, considering the influence of other cells, even if one of those cells is in the "3" state, the threshold value of the memory cell MC11 is -2.5V to -0.5V.
In the case of "0" state (see FIG. 39 (2)), the bit line is at a potential in the range of 6.5 V or more and the threshold value is 0.5 V to
At 1.5 V (“1” state, see FIG. 39 (2)), the bit lines are charged to potentials in the range of 4.5 V to 5.5 V, respectively. In addition, the threshold value is 4.5V to 5.5V
In the case of "3" state (see FIG. 39 (2)), since the memory cell MC11 is not turned on, the bit line remains at 0V.

As described above, in the non-volatile semiconductor memory device of four-value storage, the potential of the selected word line is set to a predetermined potential and the change in the potential of the bit line is sensed, whereby four storage states "0" are obtained. , "1", "2", "3" are discriminated.

Next, this discrimination will be described. The main part of the circuit of the nonvolatile semiconductor memory device of four-value storage is shown in FIG.
It was shown at 0. Each of the plurality of memory cells 1 to N is connected to a bit line, and a plurality of flip-flops FF11 are provided via the control circuits 1 to 3 and the column gates 1 to N.
To FF13. The terminals VL11 to VL13 of these flip-flops FF11 to FF13 are also included.
Each is connected to an I / O buffer. Further, the control circuits 1 to 3 are circuits for controlling what kind of signal is transmitted to the FF11 to FF13 in the subsequent stage according to the signal transmitted from the bit lines 1 to N.

Next, a method of discriminating four-valued data will be briefly described. As described above, the potential of the bit line is determined according to the threshold value of the selected memory cell. The potential of this bit line is latched in the flip-flops FF11 to FF13, and four values are discriminated by the potentials of the terminals VL11 to VL13. For example, when VL11 = H, VL12 = H, VL13 = H, "0" data VL11 = L, VL12 = H, VL13 = H, "1" data VL11 = L, VL12 = L, VL13 = H When "2" data VL11 = L, VL12 = L, VL13 = L, four values of "0" to "3" are discriminated like "3" data.

It should be noted here that the N memory cells 1 to N have three flip-flops FF11.
~ It means that FF13 is shared. That is, while reading four values from one memory cell (for example, memory cell 1), the other memory cells 2 to N are separated from the bit line. Therefore, it is impossible to read from all the bit lines 1 to N. Also, bit lines 1 to N
If a sense amplifier including a plurality of flip-flops is provided in each of the above, the chip area will increase.
Further, if an attempt is made to make the chip area the same as in the case of binary, it is only possible to provide the sense amplifier composed of three flip-flops by three bit lines in common.

[0026]

As described above, in a nonvolatile semiconductor memory device for multi-value storage, since many memory cells share a flip-flop used as a sense amplifier, memory cells of all values are stored. Could not be read at once. Therefore, in order to read the data from all the memory cells, it is necessary to read the data from each memory cell, and it takes time to read the data.

An object of the present invention is to solve the above problems.
An object of the present invention is to provide a non-volatile semiconductor device capable of reading out data once from all memory cells while suppressing an increase in chip area as much as possible.

[0028]

According to the present invention, a temporary storage circuit for accumulating data to be written in a memory cell and data to be read from the memory cell, and a voltage supply means for supplying a potential corresponding to multiple values to the bit line are provided. It is provided for each.

Therefore, since reading and writing can be performed simultaneously on the memory cells connected to the same word line, the time required for reading and writing data can be shortened. Further, since the nonvolatile semiconductor memory device according to the present invention has the voltage supply means, it is possible to supply the potential according to the data written in the nonvolatile memory cell to the bit line.

[0030]

Embodiments of the present invention will be described in detail with reference to the drawings. A detailed view of the memory cell array 999, the column gate transistor group 998, the column decoder and the row decoder portion has already been shown in FIG. Where BL1
BL4 bit line, WL1 to WL5 word lines, 99
Reference numeral 2 denotes a NAND type memory cell.

FIG. 33 shows a detailed view of the NAND type memory cell 992. One NAND memory cell 992
Are memory cells MC11 to MC18 connected in series eight
Each of the memory cells MC11 to MC18 has a floating gate for accumulating electrons. In addition, the memory cells MC11 to MC11 connected in series
One end of MC18 is connected to the bit line BL1 via the first selection transistor SGD1, and the other ends of the memory cells MC11 to MC18 connected in series are connected to the common source line via the second selection transistor SGS1. Has been done. All NAND memory cells 992 are configured as described above.

First, the write operation of the nonvolatile semiconductor memory device will be described with reference to FIG. Here, it is assumed that data is written only in the memory cell MC11 shown in FIG.

First, in a state where charges are not accumulated in all the memory cells, the bit line BL1 is set to 0V.
Then, the bit line BL2 is applied to 10V. Next, the non-selected word lines WL1C to WL1I are applied to 12V, the selected word line WL1B is applied to the write voltage (for example, 20V), the word line WL1A of the selection transistor is applied to 12V, and the WL1L is applied to 0V. Therefore, the memory cells MC11 to MC1
8. The selection transistor SGD1 is turned on and the selection transistor SGS1 is turned off.

Since the selection transistor SGS1 is in the OFF state, in the memory cell MC11, the memory cell MC
Since the potential of the source terminal S of 11 becomes a floating state and a write voltage (for example, 20 V) is applied between the control gate CG and the drain terminal D, electrons are applied to the floating gate FG via the gate insulating film 990. Is injected (see FIG. 35 (1)). That is, data is stored in the memory cell MC11, and this state is called an accumulated state.

The accumulated state will be further described with reference to FIG. FIG. 35 (2) shows a threshold number distribution diagram, showing a case of four-value writing. As described above, by applying a high voltage (write voltage) between the control gate CG and the drain terminal D of the memory cell, electrons are injected into the floating gate FG, and the threshold value of this memory cell rises. . That is, the threshold value transits from the erased state “0” to any one of the accumulated states “1”, “2”, and “3”. Also, "1", "2",
Which storage state "3" is transited to depends on the magnitude of the voltage applied between the control gate and the drain terminal.

FIG. 1 shows a block diagram of a first embodiment according to the present invention. As shown in FIG. 1, in the nonvolatile semiconductor memory device, a unit block including a cell array, a word line, a bit line, a sense circuit, a voltage supply means, and a temporary memory circuit is connected to each I / O line. .

Further, in one unit block, a cell array including nonvolatile memory cells capable of multi-valued storage is connected to a sense circuit via a bit line, and this sense circuit is connected to a temporary storage circuit. The temporary storage circuit is I
The / O line is connected to the voltage supply means, and this voltage supply means is connected to the bit line.

The sense circuit is for sensing and amplifying the signal read from the nonvolatile memory via the bit line, and the temporary storage circuit is for writing the data read from the nonvolatile memory and the memory. Data for temporary storage. The I / O line is an input / output line for exchanging data between the temporary storage circuit and the external circuit. Further, the voltage supply means is for charging the bit line to four kinds of potentials for four-value writing in accordance with the data stored in the temporary storage circuit. The memory cell array is already shown at 993 in FIG.

Next, FIG. 2 shows the sense circuit of FIG.
The detailed circuit diagram of a temporary memory circuit and a voltage supply means part is shown. The sense circuit is configured below a latch circuit including transistors TS1 to TS4 and two inverters. In addition, the temporary storage circuit includes transistors T11 to T1.
4 and capacitors C1 to C4, a storage cell in which a transistor T1N (N = 1, 2, 3, 4) and an information storage capacitor CN (N = 1, 2, 3, 4) are connected in series. Four are connected in parallel.

The voltage supply means is a transistor T3.
1 to T34 and T41 to T44, and four voltage supply circuits in which transistors T3N and T4N (N = 1, 2, 3, 4) are connected in series are connected in parallel. In addition, the storage node N1 in the temporary storage circuit
To N4 are connected to the gate terminals of the transistors T31 to T34, respectively.

Next, the read operation of the nonvolatile semiconductor memory device shown in FIG. 2 will be described with reference to FIG. now,
It is assumed that data is stored in the nonvolatile memory in the memory cell. First, the potential of the bit line is precharged to a high potential (hereinafter, referred to as H), and then brought into a floating state.

Next, the Rest signal is set to a low potential (hereinafter, L
Then, when TS2 in the sense circuit is turned on,
The nodes SN1 and SN2 are H and L, respectively. Also,
Almost at the same time when the Rest signal is set to L, the gate potential M1 of the transistor T11 in the temporary storage circuit (hereinafter, simply M
1) to H and the transistor T1 to ON, the storage node N1 of the information storage capacitor C1 is reset to L. After that, M1 is returned to L. The above operation corresponds to time (1) in FIG.

Next, one non-volatile memory in the memory cell is selected by a word drive circuit (not shown). That is, the word line connected to the nonvolatile memory is selected. The gate potential of the selected nonvolatile memory (hereinafter,
Let Vs01 (for example, 0V) be a select gate),
All the other gate potentials of the non-selected non-volatile memory (hereinafter referred to as non-selected gates) are raised from L to H. This operation corresponds to time (2) in FIG.

Next, the Sense signal is set to L, and M1 is set to L.
From H to H to turn on the transistor TS1. If the potential Vs01 of the select gate is lower than the threshold value of the non-volatile memory having the select gate, the non-volatile memory is turned ON, and the bit line precharged to H is discharged to L.

RE of the transistor TS3 in the sense circuit
Since the ST signal is always in Vcc, that is, in the H state during the read operation, the transistor TS3 is always in the ON state during the read operation. Also, the bit line is discharged,
When it goes to L, the transistor TS4 in the sense circuit turns on, so the node SN2 goes to H.

When M1 is raised from L to H, the transistor T11 is turned on. Therefore, the node SN2
H charges the information storage capacitor C1 and the storage node N1 becomes H. After that, M1 is lowered from H to L again. At this time, since the other transistors T12 to T14 are in the OFF state, the read data is stored only in the transistor T11. The above operation corresponds to time (3) in FIG.

The same operation as described above is repeated three more times, and the read data is temporarily stored in the information storage capacitors C2 to C3. However, capacitors C1, C2, C3, C4
The potentials of the select gates when the read data are stored in the Vs01, Vs12, Vs23, and Vs24, respectively.
It should be noted that the potential is raised to (Vs01 <Vs12 <Vs23 <Vs24). The above operation corresponds to time (4) to (5) in FIG.

Next, the data stored in the information storage capacitors C1 to C4 is placed on the input / output line I / O, and the binary data corresponding to the potential H or L is output to the outside of the nonvolatile semiconductor memory circuit. To transfer.

Next, the read operation will be described in more detail. FIG. 4A shows a distribution diagram of the number of threshold values in the case of four values. Further, (2) indicates a NAND type memory cell. These four values are defined as "0", "1", "2", and "3" in ascending order of threshold value, and their widths are defined as Ln to Hn (n = 0, 1, 2, 3), respectively.
The selection gate potential Vs01 described later is in the range of H0 to L1, Vs12 is in the range of H1 to L2, and Vs23 is H.
Within the range of 2 to L3, Vs34 is assumed to be larger than H3.

Further, in (2) of FIG. 4, the selection transistors SGS and SGD are turned on, the non-selected non-volatile memory cells MC12 to MC18 are turned on, and one terminal of the selection transistor SGS is grounded. Further, a case where the selected nonvolatile memory cell MC11 is in the state of "1" will be described as an example.

First, the selected nonvolatile memory cell MC
The gate potential of 11 is set to Vs01 (see FIG. 3 for the waveform). At this time, the potential Vs01 is smaller than the threshold value (L1 to H1) of the selected nonvolatile memory MC11, so that the nonvolatile memory MC11 remains in the OFF state. Therefore, the bit line precharged to H does not discharge and remains H. In this case, as described above, L is stored while the information storage capacitor C1 remains L. This operation corresponds to the time (3) in FIG.

Next, the gate potential of the selected nonvolatile memory cell MC11 is set to Vs12 (see FIG. 3 for waveform). At this time, the potential Vs12 is equal to the selected nonvolatile memory M
Since it is larger than the threshold value (L1 to H1) of C11, the nonvolatile memory MC11 is turned on. Therefore, the bit line precharged to H is discharged, and the potential changes from H to L. In this case, H is stored in the information storage capacitor C2. This operation corresponds to the time (4) in FIG.

Next, when the gate potential of the selected non-volatile memory cell MC11 is set to Vs23 (see FIG. 3 for the waveform), H is applied to the information storage capacitor C3 as described above.
Is stored. This operation corresponds to the time (5) in FIG.

Next, when the gate potential of the selected nonvolatile memory cell MC11 is set to Vs23 (see FIG. 3 for the waveform), the information storage capacitor C3 is set to H in the same manner as described above.
Is stored. This operation corresponds to the time (6) in FIG. As described above, the read operation of this embodiment is completed.

FIG. 5 shows a summary of what information is stored in the information storage capacitor according to the data stored in the selected non-volatile memory during the read operation.

As shown in FIG. 5, when "0" data is stored in the selected non-volatile memory, the potentials of the storage nodes N1, N2, N3 and N4 are all H and "1" data is stored. Is stored, the potentials of the storage nodes N1, N2, N3 and N4 are L and L, respectively.
When H, H, and H are stored and "2" data is stored, the potentials of the storage nodes N1, N2, N3, and N4 are L, L, H, and H, respectively, and "3" data is stored. Storage nodes N1, N2, N
The potentials of 3 and N4 are L, L, L, and H, respectively.

As described above, the data is stored in the four information storage capacitors included in the temporary storage circuit, and the four-value data is discriminated based on the data. Further, although the case of four values is assumed above, an N value of three or more may be used. However, in that case, the number of information storage capacitors is N.

In this embodiment, the potential of the select gate is set to Vs.
It was increased from 01 to Vs34, but from Vs34 to Vs0
It may be reduced to 1. Further, as can be seen from FIG. 5, the number of information capacitors is 3 if only four values are discriminated.
It may be individual. That is, when the N value is determined, the number of information storage capacitors may be the number corresponding to the N value, and the number of information storage capacitors is not necessarily the same as the N value.

Further, the capacitor for storing information may be a MOS capacitor instead of the usual one in which a dielectric material is sandwiched between electrodes. A schematic diagram of the MOS capacitor is shown in FIG. Further, (2) of FIG. 6 shows an equivalent circuit of the capacitor.

As shown in FIG. 6, the gate electrode is connected to storage node N1, one diffusion layer is connected to terminal VPL1, and the other diffusion layer is connected to one diffusion layer (N
1 and VPL1 (see FIG. 2), this MOS capacitor has a threshold value.

As shown in (2) of FIG. 6, the upper electrode D1 of the capacitor is the gate electrode and the lower electrode D2 of the capacitor is M.
The interelectrode insulating film D is formed in the channel region A of the OS capacitor.
3 corresponds to the gate insulating film, respectively.

In the present embodiment, since the sense circuit and the temporary storage circuit are provided for each bit line, unlike the prior art, a multi-value memorable nonvolatile memory cell connected to one word line is used for one multi-value storage. Value data can be read. Therefore, the read time can be shortened.

Conventionally, the latch circuit is used in the circuit for multilevel storage, but since the temporary storage circuit of the present invention is formed by the MOS transistor and the capacitor, the occupied area does not increase significantly.

In addition, a planar type M is used as an information storage capacitor.
When an OS capacitor is used, unlike a stack-type capacitor in which capacitors are stacked on a semiconductor substrate or a trench-type capacitor in which a groove is formed in a semiconductor substrate, a planar MOS capacitor can be formed simultaneously with other MOS transistors. Without a significant increase in process activity.

When the trench type capacitor or the stack type capacitor is used, the capacitor can be formed three-dimensionally, so that the occupied area hardly increases. next,
The second embodiment will be described in detail with reference to the drawings.

FIG. 7 shows operation waveforms of the second embodiment. The present embodiment is characterized in that the select gate of the selected nonvolatile memory is raised stepwise. This embodiment has exactly the same circuit configuration as that of the first embodiment, and the circuit configuration has already been shown in FIG.

Next, the read operation of the second embodiment will be described. First, precharge the bit line to H,
Then put it in a floating state. Also, VPL1 to VPL
Set PL4 to L.

Next, the transistor TS in the sense circuit
When the Rest signal in 2 is changed from H to L, the transistor TS2 is turned on, and the nodes SN1 and SN2 are turned on.
Becomes H and L respectively.

Almost at the same time when the Rest signal is set to L, all of the M1 to M4 signals input to the gate terminals of the transistors T11 to T14 in the temporary storage circuit change from L to H, so that the transistors T11 to T14 are turned on.

At this time, since VPL1 to VPL4 are L,
The information storage capacitors C1 to C4 are discharged and reset. The state so far corresponds to the time (1) in FIG. 7.
Next, a row decoder (not shown) selects a predetermined word line from one nonvolatile memory in the memory cell.

The select gate of the selected nonvolatile memory is raised from L to H in a substantially linear manner. Meanwhile, Sense
By setting the signal to L, the transistor TS1 is turned on, M1 to M4 are sequentially raised from L to H, and the transistors T11 to T14 are sequentially turned on. This operation corresponds to the state from time (2) to (5) in FIG.

RE of the transistor TS3 in the sense circuit
Since the ST signal is always in the Vcc, that is, H state during the read operation, the transistor TS3 is always in the ON state during the read operation.

In addition, the nonvolatile memory cell changes the potential of the bit line precharged to H according to what data is stored in the selected nonvolatile memory cell. Transistors T11 to T1 of the temporary storage circuit
4 are sequentially turned on, and the potentials corresponding to the changes in the potential of the bit line are sequentially stored in the information storage capacitors C1 to C4.

Next, the CLS signal is raised from L to H, and the transistors T11 to T included in the temporary memory circuit are used.
By sequentially turning on 14, the data is loaded on the input / output line I / O line, and the data is transferred to a circuit outside the nonvolatile semiconductor memory device. This operation corresponds to the time (6) in FIG. As described above, the reading operation of this embodiment is completed.

Next, a circuit for raising the potential of the selected word line will be described. FIG. 8 shows a selected word line drive circuit at the time of reading. As shown in FIG. 8, the transistor T
It is composed of r55 to Tr58.

The transistors Tr55 to Tr57 are connected between the output Vscg and the high power supply voltages Vc1 to Vc3, respectively, and the transistor Tr58 is connected between the output Vscg and the low power supply voltage Vss. Also, the transistor Tr
Drive signal D1 is applied to each of the gate terminals of 55 to Tr57.
~ D3 is applied, and the Rest-Vscg signal is applied to the gate terminal of the transistor Tr58. Also, the output V
scg is connected to the word line via the row decoder.

Output waveforms of the word drive circuit shown in FIG. 8 are shown in FIG. 9 When the Rest-Vscg is changed from H to L and the drive signals D1 to D3 are sequentially changed from H to L, the potential of the output Vscg is Vs01, Vs12, Vs23, Vs.
34 and rise in steps. As described above, the waveform of the select gate shown in FIG. 7 can be formed.

FIG. 10 shows a word drive circuit. FIG.
As shown in, the high power supply voltage Vcc and the low power supply voltage Vss
The resistors R110 to R140 are connected in series between and. The gate terminals of the transistors Tr711 to Tr713 are connected to the nodes N11 to N13, respectively.
The drain terminals of the transistors Tr711 to Tr713 are connected to the power supply voltage Vcc, and the source terminals of the transistors Tr711 to Tr713 are transistor transistors Tr714 to Tr716.
Is connected to the output terminal Vscg via. The current path of the transistor Tr717 is connected to the power supply voltage Vcc and the output terminal Vscg.

FIG. 10B shows the operation waveform of the word line drive circuit of FIG. 10A. When the drive signals D1 to D4 are sequentially changed from H to L, the output signal Vscg rises substantially linearly.

FIG. 11 shows another word drive circuit, and its waveform is shown in FIG. As shown in FIG. 11, the transistors Tr91, Tr93, and Tr95 each have a resistance R.
91, R93, and R95 connected in series are connected in parallel between the high power supply voltage Vcc and the terminal N100,
Transistors Tr92, Tr94, Tr96 connected in series with resistors R92, R94, R96, respectively, are connected in parallel between the low power supply voltage Vss and the terminal N100.

The terminal N100 has an operational amplifier circuit OP3.
Is connected to the negative terminal of the operational amplifier circuit OP4, and the negative terminal of the operational amplifier circuit OP4 and the operational amplifier circuit OP3 are connected.
+ Terminal is connected.

The output terminals of the operational amplifiers OP3 and OP4 are connected to the gate terminals of Tr99 and Tr100, respectively, and the gate terminal of Tr99 and the high power supply voltage Vcc are connected.
A transistor Tr97 is connected between them, and a Tr98 is connected between the gate terminal of Tr100 and the low power supply voltage Vss.

The gate terminal of the transistor Tr97 is the NAND gate 103 whose inputs are bD1 to bD3.
In addition, the gate terminal of Tr100 is connected to the NOR gate 104 whose inputs are D1 to D3. Where bD1
bD3 means a complementary signal of D1 to D3, respectively.

Resistors R97 and R98 are connected between the node 101 and the low power supply voltage Vss, and the node 102 is connected to the-terminal of the operational amplifier circuit OP3 and the + terminal of the operational amplifier circuit OP4. Further, Tr101 is connected between the low power supply voltage Vcc and the node 101.

The detailed circuit diagram of the operational amplifier OP3 or OP4 is shown in (2) of FIG. The waveform of the output Vscg of these circuits is shown in FIG. As shown in FIG. 12, the output Vscg can be increased stepwise.

The data stored in the information storage capacitor has already been shown in FIG. In this embodiment as well, as in the first embodiment, data is stored in the four information storage capacitors included in the temporary storage circuit, and four data are stored based on the data.
Determine the value data.

In the above, the case of 4 values is assumed, but 3
The above N values may be used. However, in that case, the number of information storage capacitors is N. In addition, the capacitor for information storage is not a normal one with a dielectric material sandwiched between electrodes,
It may be a MOS capacitor. The schematic diagram and equivalent circuit of the MOS capacitor have already been shown in FIG.

In the present embodiment, since the sense circuit and the temporary storage circuit are provided for each bit line, unlike the prior art, the multi-value storable non-volatile memory cell connected to one word line is stored once. It is possible to read multi-valued data. Therefore, the read time can be shortened.

Conventionally, the latch circuit is used for the circuit for multilevel storage, but since the temporary storage circuit of the present invention is formed by the MOS transistor and the capacitor, the occupied area does not increase significantly.

When a MOS capacitor is used as the information storage capacitor, unlike a stack type capacitor in which capacitors are stacked on a semiconductor substrate or a trench type capacitor formed by digging a groove in a semiconductor substrate, a MOS capacitor is another MOS capacitor. Since it can be formed at the same time as the transistor, an increase in process steps can be suppressed.

Further, in the first embodiment, the bit line is precharged once to be in a floating state, the sense amplifier is reset, and then the potential of Vs01 is applied to the select gate to change the potential of the bit line by the sense amplifier. Sense amplification. Next, the bit line is precharged again, the sense circuit is reset, and then the floating state is set, the potential of Vs12 is applied to the selection gate, and the change in the potential of the bit line is sense-amplified by the sense amplifier. As described above, the potentials of the bit lines are set to Vs01, Vs12, Vs23, Vs34.
Each time it is changed, the bit line must be precharged and the sense amplifier must be reset.

However, in the present embodiment, the potential of the select gate is increased almost linearly. This select gate, operation and time for driving the word line and time for resetting the word line etc. are only once, and it is possible to shorten the time for precharging the bit line and resetting the sense amplifier. I can.

Therefore, unlike the first embodiment in which the read operation must be repeated N times in order to read N-value data, this embodiment requires only one read operation to read N-value data. , The total reading time can be reduced.

Next, the third embodiment will be described in detail with reference to the drawings. FIG. 13 shows operation waveforms of the third embodiment. The present embodiment is characterized in that the select gate of the selected nonvolatile memory is raised substantially linearly. This embodiment has exactly the same circuit configuration as the first embodiment,
The circuit configuration has already been shown in FIG.

Next, the read operation of the third embodiment will be described. First, precharge the bit line to H,
Then put it in a floating state. Also, VPL1 to VPL
Set PL4 to L.

Next, the transistor TS in the sense circuit
When the Rest signal in 2 is changed from H to L, the transistor TS2 is turned on, and the nodes SN1 and SN2 are turned on.
Becomes H and L respectively.

Almost at the same time when the Rest signal is set to L, all of the M1 to M4 signals input to the gate terminals of the transistors T11 to T14 in the temporary storage circuit change from L to H, so that the transistors T11 to T14 are turned on.

At this time, since VPL1 to VPL4 are L,
The information storage capacitors C1 to C4 are discharged and reset. The state so far corresponds to the time (1) in FIG. Next, a row decoder (not shown) selects a predetermined word line from one nonvolatile memory in the memory cell.

The select gate of the selected nonvolatile memory is raised from L to H in a substantially linear manner. Meanwhile, Sense
By setting the signal to L, the transistor TS1 is turned on, M1 to M4 are sequentially raised from L to H, and the transistors T11 to T14 are sequentially turned on. This operation corresponds to the state from time (2) to (5) in FIG.

RE of the transistor TS3 in the sense circuit
Since the ST signal is always in the Vcc, that is, H state during the read operation, the transistor TS3 is always in the ON state during the read operation.

The nonvolatile memory cell changes the potential of the bit line precharged to H according to what data is stored in the selected nonvolatile memory cell. Transistors T11 to T1 of the temporary storage circuit
4 are sequentially turned on, and the potentials corresponding to the changes in the potential of the bit line are sequentially stored in the information storage capacitors C1 to C4.

Then, the CLS signal is raised from L to H, and the transistors T11 to T included in the temporary storage circuit are changed.
By sequentially turning on 14, the data is loaded on the input / output line I / O line, and the data is transferred to a circuit outside the nonvolatile semiconductor memory device. This operation corresponds to time (6) in FIG. As described above, the reading operation of this embodiment is completed.

Next, a circuit for raising the selected word line will be described. FIG. 14 shows a selected word line drive circuit at the time of reading. In addition, the timing chart is shown in FIG.
It was shown to.

As shown in FIG. 14, the transistor Tr5
1 to Tr53, and capacitors C51 and R51. The transistors Tr51 and Tr52 form an inverter, and the inverter has an input D and an output R
One end of 51 is connected. The transistor Tr53 and the capacitor C51 are connected in parallel between the other end of the resistor R51 and the low power supply voltage Vss, and the gate terminal of the transistor Tr53 is connected to the gate terminal of the transistor Tr52. The output Vscg is connected to the word line via the row decoder.

As shown in FIG. 15, when the potential of the input D is lowered from H to L, the potential of the output terminal Vscg rises substantially linearly, and when the potential of the input D is raised from L to H,
The potential of the output terminal Vscg becomes L.

This word drive circuit sets the potential of the input D to H level.
From L to L, the capacitor is charged first and the output V
scg does not rise immediately and the capacitor C51 is charged and the potential of the output Vscg gradually rises.
As described above, the select gate signal that rises in a substantially linear manner is output.

FIG. 16 shows a selected word line drive circuit at the time of reading. Moreover, the timing chart is shown in FIG. In the circuit of FIG. 16, the resistor R51 in FIG. 8 is replaced with a depletion type transistor Tr58. The waveform of the output Vscg shown in FIG. 17 is more linear than the waveform of the output Vscg of FIG.

Selected word line Vscg at the time of reading data
Is more linear so that the timings at which the transistors T11 to T14 (see FIG. 2) in the temporary storage circuit are activated can be set at substantially equal intervals (M1 to M in FIG. 13).
4 waveform), so the select gate and transistor T11
It becomes easy to match the timing with T14.

FIG. 18 shows another word drive circuit, and its waveform is shown in FIG. As shown in (1) of FIG. 18, the transistors Tr61 to Tr64 are connected in parallel, one end of the current path of these transistors is connected to the power supply voltages Vc1 to Vc3 and Vcc, and the other end is connected to the resistor R55 and the transistor Tr65. . Further, the transistor Tr66 and the capacitor C3 are connected in parallel between the output Vscg which is the other end of the resistor R and the low power supply voltage Vss, and the signal output from the word drive circuit is transferred to the word line through the row decoder. Transmitted.

Another word drive circuit is shown in FIG. 18 (2). As shown in FIG. 18 (2), the high power supply voltage V
Between cc and the low power supply voltage Vss, resistors R11 to R14 are connected.
Are connected in series. Also, the transistors Tr71 to T
The gate terminals of r73 are connected to the nodes N11 to N13, respectively. The drain terminals of the transistors Tr71 to Tr73 are connected to the power supply voltage Vcc,
The source terminals of the transistors Tr71 to Tr73 are connected to the output terminal Vscg via the transistor transistors Tr74 to Tr76. The current path of the transistor Tr77 is the power supply voltage Vcc and the output terminal V
connected to scg.

The operation waveforms of the circuits of (1) and (2) of FIG. 18 are shown in FIG. As shown in FIG. 19, when the drive signals D1 to D4 are sequentially changed from H to L, the output signal V
The potential of scg rises almost linearly.

Next, another word drive circuit is shown in FIG. 20, and its waveform is shown in FIG. As shown in FIG. 20, transistors Tr71, Tr73, and Tr75 connected in series with resistors R61, R63, and R65, respectively, are connected in parallel between the high power supply voltage Vcc and the terminal N90, and are connected to the transistor Tr72, Tr74 and Tr76 in which resistors R62, R64, and R66 are respectively connected in series are connected in parallel between the low power supply voltage Vcc and the terminal N90.

The terminal N90 is connected to the + terminal of the operational amplifier circuit OP1 and to the-terminal of the operational amplifier circuit OP2,
The-terminal of the operational amplifier OP1 and the + of the operational amplifier OP2
Terminal is connected.

The output terminals of the operational amplifiers OP1 and OP2 are connected to the gate terminals of Tr79 and Tr80, respectively. The transistor Tr77 is connected between the gate terminal of Tr79 and the high power supply voltage Vcc, and the gate terminal of Tr80 and the low terminal are connected. The Tr 78 is connected between the power supply voltages Vss.

The gate terminal of the transistor Tr77 is the NAND gate 101 whose inputs are bD1 to bD3.
In addition, the gate terminal of Tr80 is connected to the NOR gate 102 whose inputs are D1 to D3. Where bD1 to bD
D3 means a complementary signal of D1 to D3, respectively.

Further, the resistors R67 and R68 are connected between the node 91 and the low power supply voltage Vss, and the node 92 is connected to the-terminal of the operational amplifier circuit OP1 and the + terminal of the operational amplifier circuit OP2.

Transistor Tr81 is connected between high power supply voltage Vcc and node 91, and low power supply voltage Vcc
Tr82 is connected between the node
Is connected between the node 91 and the output Vscg, and the capacitor C5 is connected between the output Vscg and the low power supply voltage Vss.

The detailed circuit diagram of the operational amplifier OP1 or OP2 is shown in (2) of FIG. The waveform of the output Vscg of these circuits is shown in FIG. As shown in FIG. 21, the output Vscg can be increased substantially linearly.

When the potential of the output Vscg is raised by the word drive circuit shown in FIGS. 14, 16, 18, and 20, it rises only to Vcc. However, Vcc
When it is necessary to secure the above potential, Vcc is set to V by using the booster circuit (charge pump circuit) shown in FIG.
It is boosted to DD and used in FIGS. 14, 16, 18, and 20. The waveform of this booster circuit is shown in FIG.

The data stored in the information storage capacitor has already been shown in FIG. In this embodiment as well, as in the first embodiment, data is stored in the four information storage capacitors included in the temporary storage circuit, and four data are stored based on the data.
Determine the value data.

In the above, the case of 4 values is assumed, but 3
The above N values may be used. However, in that case, the number of information storage capacitors is N. In this embodiment, the potential of the select gate is raised from Vs01 to Vs34.
It may be reduced from 34 to Vs01 in a substantially linear manner.

Further, as can be seen from FIG. 5, the number of information capacitors may be three if only four values are discriminated. That is, when the N value is determined, the number of information storage capacitors may be the number corresponding to the N value, and the number of information storage capacitors is not necessarily the same as the N value.

The capacitor for storing information is a MOS.
A MOS capacitor in which the source of the transistor is connected to the source is desirable. The schematic diagram and equivalent circuit of the MOS capacitor have already been shown in FIG. At this time, it is better that a threshold voltage exists in the MOS capacitor. That is, when the data stored in the capacitor is L, Vpl1 to Vpl
This is because N1 to N4 do not become H when 4 is pushed.

In this embodiment, since the sense circuit and the temporary storage circuit are provided for each bit line, unlike the prior art, the nonvolatile memory cells connected to one word line and capable of storing multi-value data are stored once. It is possible to read multi-valued data. Therefore, the read time can be shortened.

Conventionally, the latch circuit is used for the circuit for multilevel storage, but since the temporary storage circuit of the present invention is formed by the MOS transistor and the capacitor, the occupied area does not increase significantly.

When a MOS capacitor is used as the information storage capacitor, unlike a stack type capacitor in which capacitors are stacked on a semiconductor substrate or a trench type capacitor formed by digging a groove in a semiconductor substrate, a MOS capacitor is different from other MOS capacitors. Since it can be formed at the same time as the transistor, an increase in process steps can be suppressed.

In the first embodiment, the bit line is precharged once to be in the floating state, the sense amplifier is reset, and then the potential of Vs01 is applied to the select gate to change the potential of the bit line by the sense amplifier. Sense amplification. Next, the bit line is precharged again, the sense circuit is reset, and then the floating state is set, the potential of Vs12 is applied to the selection gate, and the change in the potential of the bit line is sense-amplified by the sense amplifier. As described above, the potentials of the bit lines are set to Vs01, Vs12, Vs23, Vs34.
Each time it is changed, the bit line must be precharged and the sense amplifier must be reset.

However, in the present embodiment, the potential of the select gate is raised substantially linearly. This select gate, operation and time for driving the word line and time for resetting the word line etc. are only once, and it is possible to shorten the time for precharging the bit line and resetting the sense amplifier. I can.

Therefore, unlike the first embodiment in which the read operation must be repeated N times in order to read N-value data, this embodiment requires only one read operation to read N-value data. , The total reading time can be reduced.

A large number of power supply voltages were required to raise the selected word line in steps, but in order to raise the selected word line in a substantially linear manner, R in FIGS.
If a word drive circuit using C delay is used, the number of power supply voltages can be reduced (in FIG. 14 and FIG. 16, the power supply voltage is Vcc and Vss).

Next, the write operation of the nonvolatile semiconductor memory device shown in FIG. 2 will be described in detail with reference to the drawings. FIG.
4 is a timing chart of the write operation. First, the data in all nonvolatile memory cells are erased.
Next, the CSL signal is raised from L to H, the transistor T40 is turned on, and M1, M2, M3, and M4 are changed from L to H.
And turn on the transistors T11 to T14 sequentially.
Let N. Further, the data transmitted from the external circuit via the input / output signal line I / O is the information storage-like capacitor C1,
It is sequentially stored in C2, C3, and C4. Then, the CLS signal falls from H to L. The operation up to this point is shown in FIG.
Of time (1).

Data is stored in the information storage-like capacitors C1 to C4 according to the data to be written in the non-volatile memory, and the stored data has already been shown in FIG. Next, one of the terminals VPL1 to VPL of the information storage circuits C1 to C4
4 (see FIG. 2) are applied to Vmwl1 to Vmwl4 respectively, the Pro signal in the voltage supply means is set to H, the selection gate is set to the high voltage Vpp (for example, 20 V), and the non-selection gate is set to the H level. These operations correspond to the time (2) in FIG.

At time (2), since the signals M1 to M4 are in the L state, the transistors T11 to T14 are OFF. Therefore, the charges accumulated in the upper electrodes D1 to D4 of the information storage capacitors C1 to C4 have no escape and V
The potentials of PL1 to VPL4 are changed from L to VPL1 to VPL, respectively.
When it is raised to PL4 (hereinafter referred to as push),
The potentials of the nodes N1 to N4 also rise.

As the potentials of the nodes N1 to N4 rise, it is determined whether the transistors T31 to T34 are turned on or off. In response to this decision, the transistors T41 to
Since T44 is ON during the time (2), the potential appearing on the bit line is determined. Predetermined data (any one of "0", "1", "2", and "3") is written in the nonvolatile memory by the potential of the bit line. The write operation is completed as described above.

Next, the method of determining the potentials of VPL1 to VPL4 will be described in detail. Now, a case of writing "3" data in a predetermined nonvolatile memory cell will be described.
In this case, the potentials of the nodes N1 to N4 are L and L, respectively.
L, L, H. That is, the information storage capacitor C
L, L, L, and H are stored in 1 to C4, respectively (see FIG. 5 for stored data).

In this case, since only the potential of the node N4 is H, only the transistor T34 is turned on. Therefore, the bit line is charged to Vm4. By the potential of this bit line, "3" data is written in a predetermined nonvolatile memory cell.

Then, "2" is added to a predetermined nonvolatile memory cell.
A case of writing data will be described. In this case, node N
The potentials 1 to N4 are L, L, H, and H, respectively (see FIG. 5).

In this case, since the potentials of the nodes N3 and N4 are H, the transistors T33 and T34 are turned on. Also, at this time, even after the potential of the node N4 is pushed,
Vm4 + Vth34 (Vth34 is a transistor T34
Threshold voltage) and push voltage VPL
Determine the value of 4.

Next, "1" is set in a predetermined nonvolatile memory cell.
A case of writing data will be described. In this case, node N
The potentials 1 to N4 are L, H, H, and H, respectively (see FIG. 5).

In this case, since the potentials of the nodes N2 to N4 are H, the transistors T32 to T34 are turned on. Also, at this time, even after the potential of the node N3 is pushed,
Vm3 + Vth33 (Vth33 is a transistor T33
Threshold voltage) and push voltage VPL
Determine the value of 3.

Next, "0" is written in a predetermined nonvolatile memory cell.
A case of writing data will be described. In this case, node N
The potentials of 1 to N4 are all H (see FIG. 5). In this case, since the potentials of the nodes N1 to N4 are H, the transistors T31 to T34 are turned on. At this time, the node N
Even after the potential of 2 is pushed, Vm2 + Vth32
The potential of the push voltage VPL2 is determined so that (Vth32 is the threshold voltage of the transistor T32) is not exceeded.

As described above, the push voltages VPL1 to
Determine VPL4. For example, the push voltages VPL1 to VPL4 are determined as follows. VPL1 = Vm1-Vcc VPL2 = Vm2-Vcc VPL3 = Vm3-Vcc VPL4 = Vss When the push voltages VPL1 to VPL4 are determined as described above, the bit line Vbit is charged as follows. However, the threshold voltage Vth3 of the transistors T31 to T34
1 to Vth34 are all equal and are set to Vth. When the data to be written is "3", Vbit = Vcc-2V
th When the data to be written is “2”, Vbit = α × (Vm3
−Vss) + Vcc−2Vth When the data to be written is “1”, Vbit = α × (Vm2
−Vss) + Vcc−2Vth When the data to be written is “0”, Vbit = α × (Vm1
-Vss) + Vcc-2Vth Here, (alpha) is a coupling coefficient.

For example, the coupling coefficient is 0.8, NM
Assuming that the threshold voltage of the OS transistor is 1V, Vcc
= 3V, Vm1 = 10V, Vm2 = 4V, Vm3 =
Since 3V and Vm4 = 2V, the potentials of C1, C2, C3, and C4 become 2V, so Vpl4 = 0V remains and Vp
13 is from 0V to 1.25V, and Vpl2 is from 0V to 2.V.
When booting to 5V and Vpl1 from 0V to 10V, C
When 1, C2, C3, and C4 are H, the potentials are 10V, 4V, 3V, and 2V, respectively. 9V, 3V, 2V, and 1V are transferred to the bit lines, respectively.

If 21V is applied to the selected word line,
The potential difference applied to the word line and the channel of the selected cell is 12 V, 18 V, 19 V, and 20 V, respectively, and if the write time is about 20 μs, they remain negative at 1 V,
Writing is performed at 2V and 3V. Moreover, the writing characteristics to the memory cell are shown in FIG.
The vertical axis shows the threshold voltage Vth and the horizontal axis shows time, and the difference between the write voltage Vpp and the cell channel potential is used as a parameter.

In the non-volatile semiconductor device, what data (any one of "0", "1", "2" and "3") is written in the non-volatile memory cell in which the data is to be written is It depends on the potential of the select gate and the potential of the bit line (see FIG. 25).

As described above, the 4-level data is written by changing the potential Vbit of the bit line according to the data to be written. As described above, during the write operation of the nonvolatile semiconductor memory device according to the present invention, the temporary storage circuit for temporarily storing data, the voltage supply means for controlling the charging potential of the bit line, and the two devices are provided. Will be needed. However, as can be seen from FIG. 2, both devices have MO
Since it can be manufactured by the S process, the manufacturing process is not complicated.

Further, as shown in FIG. 26, two inverters IN1 and IN1 connected in anti-parallel in the sense circuit are connected.
2 may be replaced with clocked inverters CIN1 and CIN2.

FIG. 27 shows a timing chart at the time of reading operation of the nonvolatile semiconductor device shown in FIG. Signal Sens for controlling the clocked inverter
The operation is the same as that of the first embodiment except the operations of the e, bSense, Latch, and bLatch signals.

Further, FIG. 28 shows another timing chart at the time of reading operation of the nonvolatile semiconductor device shown in FIG. When resetting the information storage capacitor,
The signal CSL is the same as the timing chart of FIG. 27 except that the signal CSL is also raised from L to H (corresponding to time (1) in FIG. 28).

The write operation of the nonvolatile semiconductor memory circuit of FIG. 26 is the same as that of the first embodiment. Although the above embodiments have been described with respect to the NAND type memory cell, NOR type, AND type, DINOR (Divided).
29 to 31 are configuration circuit diagrams of the NOR) type memory cell.
It was shown to.

In the above embodiment, the potential of the select gate is raised from Vs01 to Vs34.
From Vs01 to Vs01. In that case, the circuit configuration is shown in FIG. As shown in FIG. 32, as compared with FIG. 2, the PMOS and NMOS of the sense circuit and the cell may be replaced with each other, and the source line Vs may be driven from Vcc after resetting to the bit line 0V.

Further, as can be seen from FIG. 5, the number of information capacitors may be three if only four values are discriminated. That is, when the N value is determined, the number of information storage capacitors may be the number corresponding to the N value, and the number of information storage capacitors is not necessarily the same as the N value.

A circuit configuration diagram in that case is shown in FIG. As shown in FIG. 33, the temporary memory circuit has only three memory cells each including a transistor and a capacitor, but this circuit can discriminate four values.

Next, the operation of the circuit shown in FIG. 33 will be described. Storage nodes N1, N2, N in the temporary storage circuit
3 is connected to the gate terminals of the corresponding transistors in the voltage supply means, as in the above circuit. However, the storage nodes N1, N2, N3 are input to the NOR gate, and the output of the NOR gate is
It is connected to the transistor in the voltage supply means.

FIG. 34 (1) shows the potentials of the storage nodes N1, N2 and N3 when storing four values. FIG.
As shown in 4 (1), when "0" data is stored in the memory cell, the potentials of N1, N2, and N3 are H, H, and
When it becomes H and "1" data is stored, N1, N2,
The potentials of N3 are L, H, and H, respectively. When storing "2" data, the potentials of N1, N2, and N3 are L, L, and H, respectively, and when storing "3" data, N is stored.
The potentials of 1, N2 and N3 are L, L and L, respectively.

Further, the potential of the bit line corresponding to the write data is as shown in FIG. 34 (2) according to the same principle as described above. As shown in FIG. 34 (2), when the write data is "3" data, the potential Vbit of the bit line is Vs.
When the write data is “2” data, the potential Vbit of the bit line is α × (Vm3−Vss) + Vcc−.
When the write data is 2Vth and the write data is "1" data,
The potential Vbit of the bit line is α × (Vm2-Vss) + V
When the write data is “0” data, the potential Vbit of the bit line is α × (Vm1-Vs).
s) + Vcc-2Vth.

As described above, the potentials of the three storage nodes N1, N2, and N3 control ON / OFF of the corresponding transistors T32 to T34 in the voltage supply means, and at the same time, the potentials of the three storage nodes N1, N2, and N3 are newly changed via the NOR gate. It is also possible to control the ON / OFF state of the transistor T31 by forming a signal at. This makes it possible to realize a non-volatile semiconductor memory device having four-value storage with three storage cells.

[0158]

Since the present invention is configured as described above, it is possible to read and write simultaneously to the memory cells connected to the same word line, so that it is possible to shorten the time required to read and write data.

Conventionally, the latch circuit is used for the circuit for multi-valued storage, but since the temporary storage circuit of the present invention is formed by the MOS transistor and the capacitor, the occupied area is not significantly increased.

Further, a planar type M is used as the information storage capacitor.
When an OS capacitor is used, unlike a stack-type capacitor in which capacitors are stacked on a semiconductor substrate or a trench-type capacitor in which a groove is formed in a semiconductor substrate, a planar MOS capacitor can be formed simultaneously with other MOS transistors. No significant increase in process steps. Further, when the trench type capacitor or the stack type capacitor is used, the capacitor can be formed three-dimensionally, so that the occupied area hardly increases.

[Brief description of drawings]

FIG. 1 is a block diagram of a nonvolatile semiconductor memory device according to the present invention.

FIG. 2 is a first detailed circuit diagram of a nonvolatile semiconductor memory device according to the present invention.

FIG. 3 is a timing chart of a data read operation according to the first embodiment.

FIG. 4 is a distribution chart of the number of threshold values in a nonvolatile memory of four-value storage.

FIG. 5 is a list view of stored data.

6A and 6B are a sectional view and an equivalent circuit diagram of a MOS capacitor.

FIG. 7 is a timing chart of a data read operation according to the second embodiment.

FIG. 8 is a first embodiment diagram of a word drive circuit for performing a read operation of the present invention.

9 is a timing chart of the word drive circuit shown in FIG.

FIG. 10 is a second embodiment diagram of a word drive circuit for performing a read operation of the present invention.

FIG. 11 is a third embodiment diagram of a word drive circuit for performing a read operation of the present invention.

12 is a timing chart of the word drive circuit shown in FIG.

FIG. 13 is a timing chart of a data read operation according to the third embodiment.

FIG. 14 is a first embodiment diagram of a word drive circuit for realizing the read operation of the third embodiment.

15 is a timing chart of the word drive circuit shown in FIG.

FIG. 16 is a second embodiment diagram of a word drive circuit for realizing the read operation of the third embodiment.

FIG. 17 is a timing chart of the word drive circuit shown in FIG. 16.

FIG. 18 is a third embodiment diagram of a word drive circuit for realizing the read operation of the third embodiment.

FIG. 19 is a timing chart of the word drive circuit shown in FIG. 18.

FIG. 20 is a fourth embodiment of the word drive circuit for realizing the read operation of the third embodiment.

FIG. 21 is a timing chart of the word drive circuit shown in FIG. 20.

FIG. 22 is a booster circuit and pulse generator circuit diagram.

23 is a timing chart of the pulse generation circuit shown in FIG. 22.

FIG. 24 is a timing chart during a write operation of the nonvolatile semiconductor memory device according to the present invention.

FIG. 25 is a diagram showing write characteristics of a nonvolatile memory cell.

FIG. 26 is a second detailed circuit diagram of the nonvolatile semiconductor memory device according to the present invention.

27 is a first embodiment of a timing chart during a read operation of the nonvolatile semiconductor memory device shown in FIG. 26. FIG.

28 is a second embodiment of a timing chart during a read operation of the nonvolatile semiconductor memory device shown in FIG.

FIG. 29 is a configuration circuit diagram of a NOR type nonvolatile semiconductor memory device.

FIG. 30 is a configuration circuit diagram of an AND-type nonvolatile semiconductor memory device.

FIG. 31 is a configuration circuit diagram of a DINOR type nonvolatile semiconductor memory device.

FIG. 32 is a circuit configuration diagram of a nonvolatile semiconductor memory device according to the present invention for reducing the potential of a select gate from a high potential to a low potential.

FIG. 33 is a detailed circuit diagram of a nonvolatile semiconductor memory device according to the present invention when there are three information storage capacitors.

34 is a diagram showing the potential of the storage node according to write data in the circuit shown in FIG.

FIG. 35 is a block diagram of a conventional nonvolatile semiconductor memory device.

FIG. 36 is a detailed circuit diagram around a memory cell array of a conventional nonvolatile semiconductor memory device.

FIG. 37 is a configuration circuit diagram of a NAND-type nonvolatile semiconductor memory device.

FIG. 38 is a cross-sectional view of a NAND memory cell on an integrated circuit.

FIG. 39 is a diagram showing a state where electrons are injected into a floating gate to write data.

FIG. 40 is a detailed diagram of a sense amplifier block of a conventional nonvolatile semiconductor memory device capable of multilevel storage.

[Explanation of symbols]

T11-T14, T31-T34, T41-T44, T
S1 to TS3 transistors IN1 and IN2 inverters C1 to C2 information storage capacitors VPL1 to VPL4 push voltage Vcc high power supply voltage Vss low power supply voltage I / O input / output line

Claims (16)

[Claims] 1. A memory cell array including a plurality of nonvolatile memory cells having a charge storage layer and capable of storing N-valued data (N> = 3), and connected to the nonvolatile memory cells. A bit line for exchanging data with the nonvolatile memory cell; a sense circuit connected to the bit line; a temporary storage circuit connected to the sense circuit for temporarily storing N-value data; And a voltage supply circuit connected to the temporary storage circuit, wherein when the data is written in the nonvolatile memory, the voltage supply circuit stores N stored in the temporary storage circuit.
The voltage applied to the bit line is changed according to the value writing data, and when reading the data from the non-volatile memory, the N-value data read from the non-volatile memory is sense-amplified by a sense circuit, A non-volatile semiconductor memory device characterized by temporarily storing sense-amplified N-value data in a temporary memory circuit. 2. A plurality of non-volatile memory cells arranged in a matrix, wherein the non-volatile memory cells are N (N> = 3).
In a non-volatile semiconductor memory device capable of storing value data, a plurality of bit lines connected to the memory cell array for exchanging data with the non-volatile memory cells, and connected to the memory cell array. A plurality of word lines connected to the gate electrodes of the non-volatile memory cells, and a sense circuit connected to each of the plurality of bit lines and for sense-amplifying the data output from the non-volatile memory cells. A temporary storage circuit for temporarily storing N-value data to be written to the memory cell array and N-value data read from the memory cell array; connected to the bit line and the temporary storage circuit; A voltage supply circuit for applying an N-value writing potential to the bit line according to the data stored in the temporary storage circuit. N connected to the same said word line
N-value data can be simultaneously written into a non-volatile memory cell capable of storing (N> = 3) values, or simultaneously from non-volatile memory cells capable of storing N (N> = 3) values connected to the same word line. A nonvolatile semiconductor memory device capable of reading N-value data. 3. The memory cell array includes a NAN in which current paths of the plurality of nonvolatile memory cells are connected in series.
3. The nonvolatile semiconductor memory device according to claim 1, wherein a D-type memory cell is formed, and one end of the NAND-type memory cell is connected to the bit line. 4. The plurality of non-volatile memory cells are AN
3. The non-volatile semiconductor memory device according to claim 1 or 2, which constitutes a D-type memory cell. 5. The plurality of non-volatile memory cells are NO
3. The non-volatile semiconductor memory device according to claim 1, wherein the non-volatile semiconductor memory device constitutes an R-type memory cell. 6. The plurality of non-volatile memory cells are DI
2. A NOR type memory cell is constructed.
2. The non-volatile semiconductor memory device as described in 2 above. 7. The temporary storage circuit has N storage cells in which a MIS transistor and an information storage capacitor are connected in series and are connected in parallel.
2. The non-volatile semiconductor memory device as described in 2 above. 8. The nonvolatile semiconductor memory device according to claim 1, wherein the information storage capacitor is a MOS capacitor having a threshold voltage. 9. The nonvolatile semiconductor memory device according to claim 1, wherein an FN tunnel current is used when writing data to the nonvolatile memory cell. Semiconductor memory device. 10. A bit line charging method for writing multi-valued data to a non-volatile semiconductor memory device having a non-volatile memory cell capable of storing multi-valued data, wherein a write signal is supplied to a MIS transistor and an information memory. A signal storage cell in which a capacitor is connected in series,
An operation of writing data in a temporary storage circuit connected in parallel by a number corresponding to multiple values and a bit line by pushing a potential of a terminal which is not connected to a MIS type transistor of both terminals of the information storage capacitor. And an operation of transferring a potential corresponding to multiple values to the bit line charging method. 11. An operation of writing an N-value writing signal to a temporary storage circuit configured by N signal storage cells in which an information storage capacitor and an MIS type transistor are connected in series are connected, and the write signal is applied to the temporary storage circuit. An operation of transferring a voltage to a voltage supply circuit for supplying a charging voltage to a bit line by pushing the potential of a terminal that is not connected to a MIS type transistor of both terminals of the information storage capacitor; Receiving a write signal and transferring an electric potential corresponding to the N value to the bit line. 12. A method of reading multi-valued data from a semiconductor memory device having a memory cell capable of storing multi-valued data, wherein when data is written in the memory cell capable of storing multi-valued data, the memory in which the data is written The operation of transmitting the data stored in the memory cell to the bit line by raising the potential of the word line connected to the cell from the low potential to the high potential, and the sense amplification of the data transmitted to the bit line. And an operation of storing the sense-amplified signal in a temporary storage circuit in association with a multi-valued signal. 13. When data is written in a nonvolatile memory cell capable of storing N (N> = 3) values, the potential of a word line connected to the nonvolatile memory cell in which the data is written is set to a low potential. To a high potential, the operation of transmitting the N-value data stored in the nonvolatile memory cell to the bit line, the sense-amplifying the N-value data transmitted to the bit line, and the sense amplification And a signal for storing the generated signal in a temporary storage circuit. 14. The data reading method according to claim 12, wherein the potential of the word line is reduced from a high potential to a low potential. 15. The data reading method according to claim 12, wherein changes in the potential of the word line from a high potential to a low potential and changes from the low potential to the high potential are substantially linear. 16. The method of reading data according to claim 12, wherein the potential of the word line is changed from a high potential to a low potential and a change from the low potential to the high potential is changed stepwise.