JPH09321624A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit provided with a sample- and-hold circuit that is able to fetch an input signal at a high speed with high accuracy and a simple configuration. SOLUTION: The semiconductor integrated circuit device provided with an A/D converter converting an analog signal fetched by a sample-and-hold means into a digital signal is provided with a preliminary charge/discharge means, which delivers an input signal fed from an external terminal to the sample-and-hold means in synchronism with the sampling operation of the sample-and-hold means and provides a prescribed voltage to an input section of the sample-and-hold means from the hold operation of the sample-and-hold means till the sampling operation is started.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique effectively used for a sampling technique in a semiconductor integrated circuit device having an A / D converter (analog / digital converter). is there.

[0002]

2. Description of the Related Art In an A / D converter mounted on a one-chip microcomputer, a successive approximation method or a serial / parallel method is widely adopted when high speed and high accuracy are required. In any type of A / D converter, a capacitor in the sample / hold circuit is charged / discharged and sampled within a limited time according to an input analog signal. The charges accumulated in the capacitor by this sampling are subsequently compared sequentially or in parallel to obtain digital values. Regarding the A / D converter, Ohmsha Co., Ltd., December 25, 1985, "Microcomputer Handbook", pages 354 to 35
There are 7 pages.

[0003]

When the time constant from the signal source to the A / D converter is larger than the sampling time, the capacitor cannot be sufficiently charged / discharged within the limited time, and conversion is performed. Accuracy is affected. Therefore, the system side takes measures such as suppressing the signal source impedance and the input capacitance to reduce the time constant, or reducing the operating frequency of the A / D converter time to secure a sufficient sampling time. There is a need. However, in the A / D converter mounted on the semiconductor integrated circuit device such as the single-chip microcomputer, it is difficult to suppress the signal source impedance and the input capacitance to be low to reduce the time constant. In other words, as the speed of microcomputer systems increases, the sampling time tends to become shorter, but the signal source impedance and input capacitance are determined by the system side, and the degree of freedom in design is low and difficult to change easily. . In particular, in the case of a sensor such as an O ₂ sensor for controlling an engine mounted on an automobile, in which the input analog signal changes rapidly, there arises a problem that it is difficult to accurately capture the input analog signal.

An object of the present invention is to provide a semiconductor integrated circuit device having a sample and hold circuit capable of capturing an input signal at high speed and with high precision by a simple structure. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0005]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, in a semiconductor integrated circuit device equipped with an analog / digital converter for converting an analog signal taken in by the sample and hold means into a digital signal, an input signal supplied from an external terminal is used for the sampling operation of the sample and hold means. Preliminary charging / discharging means for applying a predetermined voltage to the input part of the sample / hold means is added while the sample / hold means performs the hold operation and the sampling / holding operation starts until the sampling operation starts.

[0006]

1 is a block diagram of an A / D according to the present invention.
A block diagram of one embodiment of a converter is shown. The circuit circuit block shown in the figure is formed on a single semiconductor substrate (LS) together with other circuit blocks, which are omitted in FIG.
Formed in I). The figure shows an A / D converter and a sample and hold circuit provided at its input.

The sample and hold means is a switch S1.
And the capacitor C1. When the switch S1 is in the on state, the capacitor C1 is charged or discharged by the input analog signal. When the switch S1 is turned off, the analog signal immediately before that is taken into the capacitor C1 and held (held). A / D converter A
The DC converts the held analog signal into a digital signal composed of a plurality of bits such as D0 to D7.
The A / D conversion circuit ADC is not particularly limited, but is composed of the above-described known successive approximation system or serial-parallel system.

In a microcomputer mounted on an automobile, the signal source is composed of various analog sensors such as the air inflow amount. In the figure, Z is the output impedance of the signal source and A / A of the sensor and the microcomputer.
C is an input capacitance such as a distributed resistance in a signal transmission line between the D input terminal and the like, and C is a surge absorbing capacitance and a parasitic capacitance at the input terminal.

As described above, the time constant composed of the output impedance and the input capacitance of the signal source is determined by the system configuration, and when the signal change of the signal source is relatively large with respect to the time constant, the switch of the sample and hold means. It becomes difficult to charge or discharge the capacitor C1 at high speed so that the voltage of the capacitor C1 becomes equal to the signal voltage while the S1 is in the ON state.

In this embodiment, preliminary charging / discharging means is provided between the sample / hold means and the input terminal. The preliminary charging / discharging means is composed of a switch SW1 and operates to switch between the input terminal and the voltage selecting means. That is, when the switch SW1 is connected to the contact a side, the analog voltage of the signal source supplied from the input terminal is transmitted to the sample and hold means, and when the switch SW1 is connected to the contact b side, it is formed by the voltage selecting means. The precharge / discharge voltage thus generated is transmitted to the sample / hold means. The voltage selection means divides the reference voltage Vref by a resistance voltage dividing circuit, and is not particularly limited, but is an analog signal inputted from the A / D input terminal, that is, 1/1 / maximum allowable amplitude in a signal source which is a sensor. 2 to form the above-mentioned precharge / discharge voltage.

FIG. 4 shows the sample according to the present invention.
A timing diagram is shown for explaining an example of the operation of the hold circuit. When the sampling clock is at a low level, the switch S1 of the sample and hold means is turned off to enter the hold period, during which A /
The A / D conversion operation is performed by the D converter ADC. When the sampling clock changes to the high level, the switch S1 is turned on and the input analog signal is taken in. In order to speed up the input analog signal at this time, the preliminary charging / discharging means is controlled by the precharging / discharging clock.

Basically, the precharge / discharge clock is a signal having a phase opposite to that of the sampling clock, and is set to a high level during a low level period of the sampling clock, in other words, a hold period, and the switch SW1 is turned on.
To the side. As a result, the precharge / discharge voltage VP which is approximately half the maximum value of the analog input signal is applied to the input of the sample and hold means, and the sampling clock S
When the switch S1 is turned on by the high level of 1, the capacitor C1 is precharged to the precharge / discharge voltage VP at the same time.

In the preliminary charging operation, the output impedance of the voltage selecting means is reduced, and the wiring resistance from the preliminary charging / discharging means to the sample / hold means is reduced. At a short time t2 when and overlap,
It is performed at high speed so that the voltage of the capacitor C1 becomes the voltage VP. As a result, the voltage of the capacitor C1 is the previous hold voltage V1 regardless of the analog input signal.
To the above voltage VP as shown by the dotted line.

When the precharge / discharge clock is set to the low level, the switch SW1 is switched to the side a, and the input analog signal supplied from the input terminal is transmitted. At this time, since the capacitor C1 has already been set to the voltage VP, it changes in accordance with the analog input signal with reference to this voltage. However, as described above, the impedance Z on the signal source side is set. And a voltage corresponding to the analog input signal corresponding to the time constants of the input capacitance C. And
Finally, at the timing when the sampling clock changes to the low level, the voltage V2 at that time changes to the capacitor C.
Held at 1.

That is, the voltage V2 to be held in the capacitor C1 is largely changed from the previous hold voltage V1, but it is a small voltage change in view of the precharge / discharge voltage VP and is determined by the system configuration. Even if there is a relatively large time constant composed of the impedance and the input capacitance in the signal source, it is possible to perform a highly accurate sampling operation.

Although not shown in the figure, in the sample and hold circuit of this embodiment, the voltage of the capacitor C1 changes from the precharge / discharge voltage corresponding to the midpoint voltage VP to the voltage corresponding to the analog input signal. Since the change width can be reduced to half of the maximum allowable analog signal even at the maximum, it is possible to perform a highly accurate sampling operation within a short time (high speed).

FIG. 2 is a block diagram of another embodiment of the A / D converter according to the present invention. In this embodiment, continuous sampling control means is added to the sample and hold means. That is, in order to obtain a held analog signal for the A / D conversion operation, the sampling period is substantially lengthened by performing sampling twice. With this configuration, the sampling cycle can be substantially lengthened without changing the frequency of the system clock of the microcomputer or the like.

FIG. 3 is a block diagram showing still another embodiment of the A / D converter according to the present invention. In this embodiment, sampling time control means is added to the sample and hold means. That is, in order to obtain a held analog signal for the A / D conversion operation,
Only the sampling time can be lengthened. Such control of the sampling time is performed by setting the frequency itself of the sampling clock or by controlling the pulse duty. In order to improve the usability of the A / D converter, it is convenient to provide a control register and write the sampling time by software so that the sampling time can be set correspondingly.

FIG. 5 shows a block diagram of an embodiment of a single chip microcomputer to which the present invention is applied. Although not particularly limited, the single-chip microcomputer MCU of this embodiment is incorporated in an automobile, an industrial machine or the like, and functions as a control device for the same.

The microcomputer MCU shown in the figure is a so-called stored program type central processing unit CPU. The central processing unit CPU is not particularly limited, but a read-only memory R via an internal bus IBUS.
The OM, random access memory RAM, analog / digital conversion circuit A / D, watchdog timer WDT, timer circuit TIM and serial communication interface SCI are connected. Further, in each unit of the microcomputer MCU including the central processing unit CPU,
A predetermined clock signal CL from the clock generation circuit CLKG
K is supplied, and the microcomputer MCU further includes a clock controller CLKC for controlling the operation of the clock generation circuit CLKG, and a power-on reset circuit POR for resetting each part of the microcomputer MCU to the initial state when the power is turned on. Equipped with.

The watchdog timer WDT is supplied with an internal signal PR from the central processing unit CPU, and its output signal, that is, the abnormality detection signal TD, is supplied to the clock controller C.
Supplied to LKC. One input terminal of the clock generation circuit CLKG is coupled to one electrode of the crystal oscillator XTAL via the external terminal EXTAL, and the clock output signal CG of the clock controller CLKC is supplied to the other input terminal. The other electrode of the crystal oscillator XTAL is connected to the clock controller C via the external terminal XTAL.
It is bound to LKC.

The power-on reset circuit POR is supplied with the power supply voltage VCC and the ground potential VSS, which are the operating power supplies of the single-chip microcomputer MCU, via the external terminals VCC and VSS, respectively, and its output signal, that is, the power-on reset signal POR. Are supplied to the clock controller CLKC. To the clock controller CLKC, the output signal RSTP of the complete stop control register RSTP and the output signal RCMD of the mode control register RCMD are further supplied from the central processing unit CPU, and the output signal, that is, the normal reset signal RS is supplied to the central processing unit CPU. It is supplied to each part of the microcomputer MCU including.

The central processing unit CPU executes step operations according to a user program stored in the read-only memory ROM to execute predetermined arithmetic processing, and at the same time,
Controls and controls each part of the microcomputer. In this embodiment, the central processing unit CPU comprises an instruction-writable complete stop control register and a mode control register, the output signals RSTP and RCMD of which are supplied to the clock controller CLKC as described above. Further, the internal signal PR indicating the program execution status of the central processing unit CPU is constantly monitored by the watchdog timer WDT and is used for abnormality detection of the microcomputer MCU. The read-only memory ROM is, for example, a mask ROM having a predetermined storage capacity,
It stores programs and fixed data necessary for controlling the central processing unit CPU. The random access memory RAM is, for example, a static RAM having a predetermined storage capacity, and temporarily stores the calculation result of the central processing unit CPU, control data, and the like.

The analog-digital conversion circuit A / D converts an analog input signal input from various external sensors into a digital signal of a predetermined bit and transmits it to the central processing unit CPU or the like via the internal bus IBUS. In this embodiment, the reference voltage Vref used to form the precharge / discharge voltage as described above is supplied. This reference voltage Vref
Is also supplied to the A / D converter and may be used as a reference voltage for the A / D conversion operation. The sampling and holding means and the precharging / discharging clock used in the precharging / discharging means, which are included in the analog / digital converter A / D, are formed on the basis of the clock generated by the clock generating circuit CPG. It The same applies to the clock signal used for the A / converter ADC itself.

The timer circuit TIM measures time according to the clock signal supplied from the clock generation circuit CPG, and the serial communication interface S
The CI is, for example, a serial input / output device and a random access memory RAM which are connected to the outside of the microcomputer.
Support high speed data transfer to and from.

The watchdog timer WDT monitors the internal signal PR output from the central processing unit CPU, and in response to the internal signal PR not being formed for a predetermined time, in other words, the instruction by the central processing unit CPU. In response to the fact that the fetch is not performed for a long period of time, an abnormality of the central processing unit, that is, the microcomputer is detected, and its output signal, that is, the abnormality detection signal TD is selectively set to the high level. The power-on reset circuit PO
R monitors the potentials of the power supply voltage VCC and the ground potential VSS supplied via the external terminals VCC and VSS, and temporarily outputs its output signal, that is, the power-on reset signal POR, for a predetermined period when the operating power is turned on. To a high level. The abnormality detection signal TD from the watchdog timer WDT and the power-on reset signal POR from the power-on reset circuit POR are supplied to the clock controller CLKC.

As a result, in a single-chip microcomputer or the like incorporated in an automobile, an industrial machine or the like, a watchdog timer detects an abnormality or a predetermined register is written by an instruction from a central processing unit to selectively operate a clock generation circuit. A clock controller that can stop the operation is provided to release this complete stop state.
By making it possible only by the power-on reset signal when the power is turned on again, when an abnormality occurs, the operation of the microcomputer or the like can be completely stopped until the operating power is turned off and then turned on again.

The operational effects obtained from the above embodiment are as follows. (1) In a semiconductor integrated circuit device equipped with an analog / digital converter for converting an analog signal taken in by the sample and hold means into a digital signal, an input signal supplied from an external terminal is supplied to the sample and hold means. Preliminary charging / discharging means is added for transmitting in synchronization with the sampling operation and for applying a predetermined voltage to the input part of the sample / hold means from the time when the sample / hold means is in the hold operation until immediately after the start of the sampling operation. By doing so, it is possible to reduce the range of change, so that it is possible to obtain a high-speed and highly accurate sampling operation.

(2) Since the predetermined voltage is set to a voltage which is half the maximum allowable conversion voltage of the analog / digital converter, the change width can be reduced to half the maximum allowable conversion voltage, so that the maximum speed is high. It is possible to obtain the effect that the sampling operation can be performed with high accuracy.

(3) By performing the sampling operation twice in succession, it is possible to substantially lengthen the sampling cycle and to perform the highly accurate sampling operation. Is obtained.

(4) By making the sampling time controllable by the sampling time control means, there is an effect that an optimum sampling operation can be performed.

Although the invention made by the inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, the voltage selection means forms a voltage corresponding to the maximum allowable voltage of the signal source, and also via a voltage follower circuit in order to make a fixed voltage obtained by dividing the reference voltage Vref into 1/2 a low impedance. You may make it output. The reference voltage Vref may be replaced with the power supply voltage of the internal circuit or a constant voltage. Further, the voltage for preliminary charging / discharging may be given from an external terminal. INDUSTRIAL APPLICABILITY The present invention can be widely used for various semiconductor integrated circuit devices such as microcomputers having a built-in A / D converter.

[0033]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a semiconductor integrated circuit device equipped with an analog / digital converter for converting an analog signal taken in by the sample and hold means into a digital signal, an input signal supplied from an external terminal is used for the sampling operation of the sample and hold means. By transmitting in synchronism, by adding a pre-charging / discharging means for applying a predetermined voltage to the input part of the sample / hold means from the time of the hold operation of the sample / hold means to immediately after the start of the sampling operation. Since the change width can be reduced, the sampling operation can be performed at high speed and with high accuracy.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an A / D conversion unit according to the present invention.

FIG. 2 is a block diagram showing another embodiment of the A / D conversion unit according to the present invention.

FIG. 3 is a block diagram showing still another embodiment of the A / D conversion unit according to the present invention.

FIG. 4 is a timing chart for explaining an example of the operation of the sample hold circuit according to the present invention.

FIG. 5 is a block diagram showing an embodiment of a single-chip microcomputer to which the present invention is applied.

[Explanation of symbols]

Z ... Signal source impedance, C ... Input capacitance, S1 ... Sampling switch, C1 ... Sampling capacitor, S
W1 ... Changeover switch, MCU ... Single chip microcomputer, CPU ... Central processing unit, IBUS ...
Internal bus, ROM ... Read only memory, RAM ... Random access memory, A / D (ADC) ... Analog-to-digital conversion circuit, WDT ... Watchdog timer, TI
M ... Timer circuit, SCI ... Serial communication interface, POR ... Power-on reset circuit,
CLKC ... Clock controller, CLKG ... Clock generation circuit, XTAL ... Crystal oscillator.

Claims (5)

[Claims] 1. A sample / hold means, and an analog / digital converter for converting an analog signal taken in by the sample / hold means into a digital signal,
The input signal supplied from the external terminal is transmitted in synchronization with the sampling operation of the sample and hold means, and the input of the sample and hold means is performed during the hold operation of the sample and hold means until the start of the sampling operation. A semiconductor integrated circuit device, comprising: a precharge / discharge means for applying a predetermined voltage to a unit. 2. The semiconductor integrated circuit device according to claim 1, wherein the predetermined voltage is set to half the maximum allowable conversion voltage of the analog / digital converter. 3. The semiconductor integrated circuit device according to claim 1, wherein the input signal is one in which a change in the signal changes rapidly. 4. A sample / hold means, an analog / digital converter for converting an analog signal taken in by the sample / hold means into a digital signal,
The input signal supplied from the external terminal is transmitted in synchronism with the sampling operation of the sample and hold means, and the sampling operation is performed twice or more continuously, and the sampling signal after the second sampling is analog / digital converted. A semiconductor integrated circuit device, which is converted into a digital signal by a device. 5. A sample / hold means, an analog / digital converter for converting an analog signal taken in by the sample / hold means into a digital signal,
A semiconductor integrated circuit device characterized in that an input signal supplied from an external terminal is transmitted in synchronization with the sampling operation of the sample and hold means, and the sampling time is adjustable by the sampling time control means. .