JPH0537535A - Address control circuit - Google Patents

Abstract

PURPOSE:To facilitate address setting by decreasing number of address setting input terminals for a serial communication system implementing master slave communication control with a bus type topology. CONSTITUTION:A power-on reset time is set by using a resistor R1(24) and a capacitor C1(23). An analog switch 4 interrupts electrically a serial bus 2 and a slave node 5 by using a control signal 6 from a control circuit 17 at the initial stage at application of power. The control circuit 50 closes the analog switch 4 synchronously with the release of power-on reset to connect the serial bus 2 and the slave node 5. The slave node 5 stores address information inputted first after power-on reset to an address register B 12 as its own address information. Then the inputted address information and its own address are compared and when they are coincident, the operation of an internal circuit is permitted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address control circuit used in a slave node of a serial communication control system using a bus type topology and using master / slave type communication control means.

[0002]

2. Description of the Related Art Conventionally, there are roughly two types of address control circuits of this type. One of them is a terminal 3 for address input for discriminating individual nodes as shown in FIG.
There are a plurality of 9s, and the node address is set by an external circuit such as a switch. The address is recognized by comparing the address information from the address setting terminal 39 with the transmitted address information stored in the address register A11 by the comparator 13. The communication system required many terminals for address setting.

Another type of conventional example is an address control circuit as shown in FIG. In this address control circuit,
Since the comparator 13 compares the unique address information of the circuit itself stored in the built-in ROM 40 with the received address information input to the address register A11, an input terminal for address setting is not necessary. Since the address of the slave node is fixed by the built-in ROM 40, the address of the slave node cannot be changed even when the system is changed.

When an address control circuit is created by a monolithic IC, if the built-in ROM is a mask ROM, it is necessary to have as many IC types as there are slave nodes, and if the built-in ROM is a programmable ROM, individual ICs are required. It is necessary to perform a writing process on all the address control ICs.

[0005]

In the conventional address recognition control circuit of FIG. 5 described above, the address of each node is determined by the address setting terminal. Therefore, in addition to the serial communication input / output terminal, the address is controlled. A large number of terminals for setting are required, and when the serial communication circuit is integrated into an IC, the package becomes large and the cost increases.

Further, each address setting terminal 39 needs to be pulled up or pulled down by a resistor or the like, which increases the cost due to the increase in the number of parts and enlarges the board.
However, there is a drawback that it causes a decrease in reliability due to an increase in the number of mounting points.

Further, in the address recognition control circuit of FIG.
Although the input terminal for address setting is not necessary, the address of the slave node is fixed by the built-in ROM 40, so that the address of the slave node cannot be easily changed even if the system is changed. It had the drawback of being less flexible.

Further, when the address control circuit is formed by a monolithic IC, if the built-in ROM is a mask ROM, it is necessary to have as many IC types as the number of slave nodes, resulting in an increase in cost and an increase in management man-hours. In addition, if the built-in ROM is a programmable ROM, the man-hours required to write all the address control ICs are required, which also causes a cost increase and the address once set. Has the drawback that it cannot be changed easily.

An object of the present invention is to provide an address control circuit capable of reducing the number of parts and downsizing the board.

[0010]

An address control circuit of the present invention comprises a serial signal cutoff circuit, a serial / parallel conversion circuit for transmitting / receiving serial information, a first address register for storing received address information, After the power-on reset when the power is turned on, the second address register for storing the address information input first and the second address register after the power-on reset are written only once A control circuit for generating two types of control signals, a control signal and a control signal for operating the serial signal cutoff circuit; a power-on reset circuit;
After the power-on reset stored in the first address register and the time constant determination circuit for setting the on-reset time, the address information after the second time and the contents of the second address register are compared. And a comparator.

[0011]

First, the address control circuit of the present invention can set an arbitrary power-on reset time by the time-constant determining circuit.
Set the reset time by increasing it at regular intervals.

At initial power-up, all slave nodes are temporarily electrically disconnected from the serial bus by the serial signal cutoff circuit. With this setting, each slave node subsequently powers on and resets at regular time intervals. Is released, each slave node is electrically connected to the serial bus at regular time intervals.

The control master node sends its slave node to the slave nodes connected within this fixed time.
By setting the node address, all slave nodes can be set. After setting the addresses of all slave nodes, the operation is the same as that of the conventional address control circuit. By comparing the received address information with the set address information, it is determined whether the data information has been transmitted to its own node. To do.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an address control circuit for a bus type serial communication system according to an embodiment of the present invention. The control master node 1 is a control master circuit that controls serial communication and sets the address of the slave node A5. Serial bus 2 consists of control master node 1 and slave
It is a serial signal line that connects the node A5. Branch line 3
Is a branch line of the serial signal to the slave node A5 of the serial bus 2.

The analog switch 4 is located on the branch line 3 and, after the power is turned on, the control signal 6 from the slave node A5.
This is a serial signal cutoff circuit for performing serial signal cutoff and serial signal cutoff cancellation by. Slave node A
Reference numeral 5 is a slave node which operates according to the serial data from the control master node 1.

The control signal 6 is a control signal for turning on / off the analog switch 4, and the TX / RX terminal 7 is an input / output terminal of the slave node A5. The serial / parallel conversion circuit 8 has a function of converting a serial signal input from the TX / RX terminal 7 into a parallel signal and transmitting the parallel signal to the inside of the address control circuit, and a function of converting a parallel signal from the internal register into a serial signal.

The 3-state buffer 9 receives the serial signal output from the serial / parallel conversion circuit 8 as TX / RX.
It controls whether to output from the terminal 7.

The parallel bus 10 is for transmitting input information, which has been converted into a parallel signal by the serial / parallel conversion circuit 8, to each register described later, and for transmitting output information from each register to the serial / parallel conversion circuit 8. Is.

The address register A11 is for storing the received address information, and is connected to the serial / parallel conversion circuit 8 by the parallel bus A10. The address register B12 is an address register
Similar to the register A11, it is connected to the serial / parallel conversion circuit 8 via the parallel bus 10, and the control signal 15 from the control circuit 14 causes the address first input only once after power-on reset. Store information.

The comparator 13 has an address register A11.
Is a circuit that compares the contents of the address register B12 with the contents of the address register B12 and outputs a match signal 18 if they match. The control circuit 14 controls the control signal 1 to write the address register B12 only once after the power-on reset.
5, the control signal 6 of the analog switch 4, the enable control signal TXC17 to the 3-state buffer 9 at the time of transmission from the slave node, and the control signal 16 for stopping the operation of the data register. It is a control circuit that generates a control signal.

The control signal 15 is a write control signal for storing, in the address register B12, the address information first input to the address register B12 after the power-on reset. The control signal 16 is power
This is a control signal for stopping the operation of the data register during the initialization after the on-reset.

The control signal TXC17 is an enable control signal to the three-state buffer 9 at the time of transmission from the slave node, and when this signal is activated, the output signal from the serial / parallel conversion circuit 8 is TX. / RX
When the control signal TXC17 is output from the terminal and the control signal TXC17 is inactive, the output of the 3-state buffer 9 becomes high impedance and is not output. The match signal 18 is a match signal of the address comparison result output from the comparator 13. The logical product 19 is a circuit for obtaining the logical product of the control signal 16 and the coincidence signal 18, and the control signal 16 controls whether or not the coincidence signal 18 is transmitted to the data register 21. The control signal 20 is an output signal of the logical product 19 and controls whether or not the operation of the data register 21 is permitted.

The data register 21 is a register for storing data information which is input subsequently to the address information in the normal serial communication, and the parallel bus 10
It is connected to the serial / parallel conversion circuit 8 via the and is operated by the control signal 20.

The power-on reset circuit 22 is a power-on reset circuit in which the power-on reset time can be arbitrarily set by the time constant determined by the resistor R1 (24) and the capacitor C1 (23). , Has a function of initializing each internal register and notifying the control circuit 14 that power-on / reset is being performed. The capacitor C1 (23) constitutes a time constant setting circuit for setting the power-on reset time T together with the resistor R1 (24).

FIG. 2 is a connection diagram of the bus-type topology serial communication system of this embodiment. Control master node 1,
Serial bus 2, branch line 3, analog switch 4,
Slave node A5, control signal 6, capacitor C1
(23) and the resistor R1 (24) are the same as in FIG. The branch lines 25 and 31 are branch lines having the same function as the branch line 3. The analog switch 26 and the analog switch 32 are similar to the analog switch 4 in the branch line 25.
And a serial signal cutoff circuit which is located on the branch line 31 and which cuts off the serial signal and cancels the cutoff of the serial signal by the control signal 28 and the control signal 34 from each slave node after the power is turned on.

Slave node B27 is the second control slave node from slave node A5, and slave node N33 is the Nth control slave node from slave node A5.

A capacitor C2 (29) and a resistor R2 (3
0) is a time constant circuit for setting the power-on reset time of the slave node B27, where 1 is the power-on reset time of the slave node A5.
A time constant that is a power-on reset time of T + t1 is set by adding time t1 necessary and sufficient for address setting of one slave node.

The capacitor CN (35) and the resistor RN (3
6) is a time counting circuit for setting the power-on reset time of the slave node N33, where Tn is the power-on reset time of the slave node which is addressed one time before the slave node N33. A time constant, which is the power-on reset time of Tn + t1, is set by adding the time t1 necessary and sufficient for setting the address of one slave node.

Next, the operation of the address control circuit for the bus type serial communication system of the present invention will be described. First,
The time when the power is turned on to the entire system and the communication system starts operating will be described. At this time, since the slave node A5, the slave node B27, and the slave node N33 are in the power-on reset operation, the control circuit 14 of each slave node causes the analog switches 4, 26, and 32 to output serial signals. The control master node 1 outputs the control signals 6, 28 and 34 so as to perform the shutoff operation, and the control master node 1 initializes its own internal circuit.

A slave connected to the serial bus 2
Among the nodes, after the power-on reset time T of the slave node A5 having the shortest power-on reset time has elapsed, the slave node A5 detects that the power-on reset is completed by the control circuit 14, The control signal 6 is output so that the analog switch 4 is released from the interruption of the serial signal.

By this operation, the control master node 1 and the slave node A5 are electrically connected from the serial bus 2 through the branch line 3. At this time, other slave nodes B27 and slaves are connected. The node N33 is electrically cut off because the power-on reset time has not elapsed.

If the power-on reset time of the control master node 1 is set to the same T time as that of the slave node A5, the present serial communication system has the control master node 1
Then, only two nodes, the slave node A5 and the slave node A5, start operating. In this state, the control master node 1 may perform the address setting operation for the slave node A5.

Specifically, the control master node 1 releases the serial bus 2 after releasing its power-on reset.
Then, the serial signal output which is the unique address information of the slave node A5, for example, "01h" is output. power·
In the initial state after on-reset, slave node A
In addition to this, the control circuit 14 of 5 includes a 3-state buffer 9
The control signal TXC17 is controlled so that the output becomes high impedance.

Since the slave node A5 outputs the control signal 6 to the analog switch 4 so that the serial signal interruption is released, the serial signal from the control master node 1 is transmitted to the TX / RX of the slave node A5. Input terminal 7
Is transmitted to the slave node A5. Slave
The serial signal transmitted to the node A5 is serial /
The control circuit 14 inputs the data to the parallel conversion circuit 8.
Is also input to the control circuit 14, and the control circuit 14 detects that the first serial signal has been input after the power-on reset.

The serial / parallel conversion circuit 8 converts the input serial signal into a parallel signal, and the address register A11 stores the input address information "01h" via the parallel bus 10. At this time, since the control circuit 14 detects that it is the first serial signal input after the power-on reset, the address signal "01H" is also sent to the address register B12 via the parallel bus 10 by the control signal 15. Memorize

Since the contents of the address register A11 and the address register B12 are the same at this point, the comparator 13 activates the comparison match signal 18, but the control circuit 1
If a timer having a time t1 necessary and sufficient for setting its own address is provided in 4 and the control signal 16 is made inactive during the time t1 at which its own address setting ends, the logical product 19 is used. Since the control signal 20 outputs a deactivation signal, the data register 21 does not operate yet.

By the above operation, the slave node A5
Although the address setting operation is completed, the time from the start of the address setting to the end is t1 time as described above, and therefore T + t1 time has elapsed since the initial power-on. That is, at this point, the power-on reset time of the next slave node B27 has elapsed, the control circuit of the slave node B27 detects the end of the power-on reset, and the analog switch 26 is serialized. A control signal 28 is output so that the signal interruption is released.

By this operation, the control master node 1 and the slave node A5 are electrically connected from the serial bus 2 via the branch line 3, and the slave node B27 is electrically connected from the serial bus 2 via the branch line 25. Connected,
At this time, the other slave node N33 is powered on.
It has been electrically shut off because the reset time has not elapsed.

When the control master node 1 completes the address setting of the slave node A5,
The address setting operation of the node B27 is started.

That is, if the unique address information of the slave node B27 is "02h", the control master node 1
Outputs a serial signal of "02h".

This "02h" serial signal is input to slave node A5 and slave node B27.
The slave node B27 stores "02h" in the address register B in the slave node B27 by the same operation as that of the slave node A5 described above.

In the slave node A5, the input address information "02h" is transferred to the serial / parallel conversion circuit 8
It is converted into a parallel signal by and is stored in the address register A11 via the parallel bus 10. Control circuit 14
Is the second serial signal input after the power-on reset, so that it is not stored in the address register B12.

At this time, since "02h" is stored in the address register A11 and "01h" is stored in the address register B12, the comparator 13
Deactivates the compare match signal 18 so that the data register 21 does not operate. In other words, slave node A5
Address setting of the slave node B27 is completed.

Since the power-on reset of each slave node connected to the serial bus 2 is sequentially released, the control master node 1 also sequentially sets the address of each slave node, and At the stage where the address setting of the slave node N33 is completed, all the nodes are connected to the parallel bus 2 in the serial communication system of the present embodiment to become a complete bus type serial communication system.

In this way, after setting the address of each slave node once after the initial power is turned on, each slave node has its own address and the control master
It can be freely accessed from the node. Moreover, since the input terminal 39 for address setting unlike the conventional example shown in FIG. 5 is not required, the number of components, the size of the board, and the number of mounting points can be reduced, so that the reliability can be improved.

Further, in the conventional example shown in FIG. 6, the input terminal for address setting is not necessary, but the address of the slave node is fixed by the built-in ROM 40. Although the address cannot be changed easily and it has a drawback that it affects the flexibility of the system, in this embodiment, the unique address information of each slave node is determined by the control master node 1 after the initial power-on. Therefore, the address of each slave node can be easily changed, and the system has high flexibility.

Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a block diagram of an address control circuit for a bus type serial communication system according to the second embodiment.

In this embodiment, control master node 1, parallel bus 2, branch line 3, slave node A
5, TX / RX terminal 7, serial / parallel conversion circuit 8, 3-state buffer 9, parallel bus 10, address register A11, address register B12,
Comparator 13, control circuit 14, control signal 15, control signal 1
6, control signal TXC17, comparison match signal 18, logical product 1
9, the control signal 20, the data register 21, the power-on reset circuit 22, the capacitor C1 (23), and the resistor R1 (24) are the same as those in the first embodiment.

The control signal 37 is a control signal output from the control circuit 14 and controls whether the serial signal input from the TX / RX terminal 7 is transmitted to the internal circuit. The logical product 38 is the serial signal cutoff circuit of this embodiment, which cuts off the input serial signal when the control signal 37 is in the inactive state and cuts off the input serial signal when the control signal 37 is in the activated state. It has the function of transmitting signals inside.

FIG. 4 is a connection diagram of the serial communication system of the bus topology of this embodiment. In FIG. 4, control master node 1, serial bus 2, branch line 3, slave node A5, capacitor C1 (23), resistor R1
(24) is similar to FIG.

The branch lines 25 and 31 are branch lines having the same functions as the branch line 3. The slave node B27 is the second control slave node from the slave node A5, and the slave node N33 is the control slave node located Nth from the slave node A5. It is the same.

The capacitor C2 (29) and the resistor R2 (3
0) is a time constant circuit for setting the power-on reset time of the slave node B27, where 1 is the power-on reset time of the slave node A5.
It is also similar to the first embodiment that the time constant that is the power-on reset time of T + t1 is set by adding the time t1 necessary and sufficient for the address setting of one slave node.

The capacitor CN (35) and the resistor RN (3
6) is a time constant circuit for setting the power-on reset time of the slave node N33, where Tn is the power-on reset time of the slave node which is addressed one time before the slave node N33. It is also similar to the first embodiment that the time constant that is the power-on reset time of Tn + t1 is set by adding the time t1 necessary and sufficient for setting the address of one slave node.

Next, the operation of this embodiment will be described.
First, a description will be given of the point in time when the entire system is powered on and the communication system starts operating. At this time, slave node A5, slave node B27, slave node
Since the node N33 is in the power-on reset operation, the control circuit 14 of each slave node has a logical product 3
The control master node 1 initializes its own internal circuit by outputting the control signal 38 so that 7 becomes the serial signal cutoff operation.

Slave connected to serial bus 2
After the lapse of the power-on reset time T of the slave node A5 having the shortest power-on reset time among the nodes, the slave node A5 detects that the power-on reset is completed by the control circuit 14, A control signal 38 is output so that the product 37 is released from the interruption of the serial signal.

By this operation, the control master node 1 and the slave node A5 are electrically connected from the serial bus 2 through the branch line 3. At this time, other slave nodes B27 and slave nodes are connected. The node N33 is electrically cut off because the power-on reset time has not elapsed.

If the power-on reset time of the control master node 1 is set to the same T time as that of the slave node A5, the present serial communication system has the control master node 1
Then, only two nodes, the slave node A5 and the slave node A5, start operating. In this state, the control master node 1 may perform the address setting operation for the slave node A5.

More specifically, the control master node 1 releases the serial bus 2 after releasing its power-on reset.
Then, a serial signal that is unique address information of the slave node A5, for example, "01h" is output. In the initial state after power-on reset, slave node A5
In addition, the control circuit 14 controls the control signal TXC17 so that the output of the 3-state buffer 9 becomes high impedance. The slave node A5 outputs a control signal 38 to the logical product 37 so that the serial signal cutoff is released.
, The serial signal from the control master node 1 is transmitted from the TX / RX input terminal 7 of the slave node A5 into the slave node A5.

The serial signal transmitted to the slave node A5 is input to the serial / parallel conversion circuit 8 and also to the control circuit 14, and the control circuit 14
Detects the first serial signal input after power-on reset. The serial / parallel conversion circuit 8 converts the input serial signal into a parallel signal,
Further, the address information “01h” input to the address register A11 via the parallel bus 10 is stored.

At this time, since the control circuit 14 detects that it is the first serial signal input after the power-on reset, the control signal 15 causes the address register B12.
Also, the address information “01” is sent via the parallel bus 10.
Remember H ".

Since the contents of the address register A11 and the address register B12 are the same at this point, the comparator 13 activates the comparison match signal 18, but the control circuit 1
4 has a timer for a time t1 necessary and sufficient for setting its own address, and if the control signal 16 is inactivated during the time t1 at which its own address setting ends, the logical product 19 As a result, the control signal 20 which determines the operation of the data register 21 outputs a deactivation signal, and the data register 21 does not operate yet.

With the above operation, the address setting operation of the slave node A5 is completed in this embodiment as well.
Since the time from the start of address setting to the end thereof is t1 time as described above, it means that T + t1 time has elapsed since the initial power-on. That is, at this point, the power-on reset time of the next slave node B27 has elapsed, and the control circuit of the slave node B27 detects the end of the power-on reset, and the slave node B27 A control signal 38 is output so that the logical product 37 therein is released from the interruption of the serial signal.

By this operation, the control master node 1 and the slave node A5 are electrically connected from the serial bus 2 via the branch line 3, and the slave node B27 is electrically connected from the serial bus 2 via the branch line 25. This means that the slave node N33 is connected, and at this time, the other slave node N33 is electrically cut off because the power-on reset time has not elapsed.

At the time when the address setting of the slave node A5 is completed, the control master node 1 sends the next slave node
The address setting operation of the node B27 is started. That is, the unique address information of the slave node B27 is set to "02h".
Then, the control master node 1 outputs a serial signal of "02h". This "02h" serial signal is input to the slave node A5 and the slave node B27.

The slave node B27 operates in the same manner as the slave node A5 described above, and the slave node B27
"02h" is stored in the address register B12 in 27. In the slave node A5, the input address information "02h" is converted into a parallel signal by the serial / parallel conversion circuit 8 and stored in the address register A11 via the parallel bus 10.

Since the control circuit 14 receives the second serial signal after the power-on reset, it does not store it in the address register B12. At this point, since "02h" is stored in the address register A11 and "01h" is stored in the address register B12, the comparator 13 deactivates the comparison match signal 18, The data register 21 does not operate. That is,
The address setting of the slave node B27 is completed without affecting the slave node A5.

Since the power-on reset of each slave node connected to the serial bus 2 is sequentially released, the control master node 1 also sequentially sets the address of each slave node, and the last At the stage where the address setting of the slave node N33 is completed, all the nodes are connected to the parallel bus 2 in the serial communication system of the present embodiment to become a complete bus type serial communication system.

As described above, in the present embodiment, the advantage of the first embodiment is realized as it is because it does not have the input / output terminal 39 for address setting and the flexibility of the system.

[0069]

As described above, the present invention has a function of temporarily electrically disconnecting all the slave nodes from the serial bus by the serial signal cutoff circuit when the initial power is turned on. Then, the power-on reset time is set for each slave node by increasing the power-on reset time at a constant time interval by a resistor and a capacitor, and after that, each slave node cancels the power-on reset at a constant time interval. As such, each slave node is electrically connected to the serial bus at regular time intervals. Control master
Nodes are slaves connected in sequence within this fixed time.
By setting the address of the slave node to the node, the address setting of all slave nodes is performed. Therefore, since an input terminal for address setting is not required, the number of parts can be reduced, the size of the board can be reduced, and the number of mounting points can be reduced.

Further, since the unique address information of each slave node is determined by the control master node 1 after the initial power-on, the address of each slave node can be easily changed, and the system flexibility is high. have.

[Brief description of drawings]

FIG. 1 is a block diagram of an address control circuit for a bus-type serial communication system according to the present invention.

FIG. 2 is a connection diagram of the bus-type serial communication system according to the first embodiment.

FIG. 3 is a block diagram of an address control circuit for a bus type serial communication system according to a second embodiment.

FIG. 4 is a connection diagram of a bus type serial communication system according to a second embodiment.

FIG. 5 is a block diagram of a conventional address control circuit for a bus-type serial communication system having an address setting terminal.

FIG. 6 is a block diagram of a conventional address control circuit for a bus type serial communication system having no address setting terminal.

[Explanation of symbols]

 1 Control Master Node 2 Serial Bus 3 Branch Line 4 Analog Switch 5 Slave Node A 6 Control Signal 7 TX / RX Terminal 8 Serial / Parallel Conversion Circuit 9 3-State Buffer 10 Parallel Bus 11 Address Register A 12 Address register B 13 Comparator 14 Control circuit 15 Control signal 16 Control signal 17 Control signal TXC 18 Comparison match signal 19 Logical product 20 Control signal 21 Data register 22 Power-on reset circuit 23 Capacitor C1 24 Resistor R1 25 Branch line 26 Analog Switch 27 Slave Node B 28 Control Signal 29 Capacitor C2 30 Resistor R2 31 Branch Line 32 Analog Switch 33 Slave Node N 34 Control Signal 35 Capacitor CN 36 Resistor RN 37 Control Signal 38 Riseki 39 address setting terminals 40 built-in ROM

Claims (1)

Claims: 1. A serial / parallel conversion circuit connected to an input / output terminal of a slave node, and a serial connected from an input / output terminal of a master node to an input / output terminal of the slave node. / Serial to parallel conversion circuit
Via a serial signal cutoff circuit that performs serial signal cutoff and serial signal cutoff release by a control signal from the slave node after power-on on the bus signal branch line, and a parallel bus built in the slave node in the serial / parallel conversion circuit. And a serially connected first receive address register via the parallel bus.
A second address register connected to the parallel conversion circuit for storing the address information input first after the power-on reset, and writing to the second address register only once after the power-on reset The control signal that performs the operation, the control signal that generates the control signal for the serial signal cutoff circuit operation, and the control signal that indicates that the internal registers are being initialized and power-on-reset is being performed when the power is turned on The power-on reset circuit, the time constant setting circuit for setting the power-on reset time, the contents stored in the second address register, and the second and subsequent inputs to the first address register. When the comparison result is a match, the comparator that enables the operation of the data register and the power-on
The address information input first after reset is stored in the second address register as its own address, and the contents input after the second power-on reset to the first address register and its own address information And a means for permitting operation of the internal circuit if the comparison results are in agreement with each other.