JPH09321588A - Waveform shaping circuit for clock signal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a waveform shaping circuit for a clock signal in which electromagnetic noise radiated from a signal line is reduced, through which the clock signal is supplied. SOLUTION: A clock signal being a pulse signal outputted from an output terminal 32 of a clock signal output IC is given to a series resonance circuit consisting of an inductive element 22, a capacitive element 23 and an input capacitor 37 of a waveform shaping circuit 21, in which the signal is converted into a sine wave in which harmonic components are limited. Furthermore, the amplitude of the sine wave depends on the sets of capacitance C2, C1 of the capacitive element 23 and the input capacitor 37, and the DC voltage level of the sine wave depends on the sets of resistance values R2, R1 of a resistive element 24 and an input resistor 36.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit which is interposed between a digital device and a circuit which supplies a clock signal for controlling the operation of the digital device and shapes the waveform of the clock signal.

[0002]

2. Description of the Related Art FIG. 8 shows a conventional structure for reducing electromagnetic noise. A power supply voltage VCC and a ground voltage are connected to an integrated circuit (hereinafter referred to as “output IC”) 11 for outputting a clock signal. Output I
From C11, a pulsed clock signal with a predetermined frequency is output via the output terminal 12.

An integrated circuit that receives a clock signal (hereinafter referred to as
The power supply voltage VCC and the ground voltage are connected to the “reception IC” 13) as in the output IC 11. Receiving IC
An input terminal 14 for receiving a clock signal is provided at 13.

In the receiving IC 13, an allowable input value is set as a level of an operable signal. The input allowable value of the reception IC 13 is, for example, one is the ground voltage and the other is the power supply voltage VCC. If a voltage exceeding the input allowable value is applied, the reception IC 13 may malfunction. Further, the reception IC 13 has two threshold voltages VL, which are used as reference voltage levels for determining whether the allowable clock signal is at a high level or a low level.
VH is defined. The lower threshold voltage VL is
The threshold voltage VH is set higher than the ground voltage and lower than the power supply voltage VCC, and the higher threshold voltage VH is set lower than the threshold voltage VL and lower than the power supply voltage VCC. The reception IC 13 determines that the voltage equal to or lower than the lower threshold voltage VL is low level, and the voltage equal to or higher than the higher threshold voltage VH is high level.

The capacitance at the input terminal 14 is converted to the input capacitance 15
As shown. One end of the input capacitor 15 is connected to a signal line 16 connecting the output terminal 12 and the input terminal 14,
The other end is grounded.

[0006] As the frequency of the clock signal output from the output IC 11 increases, electromagnetic noise is generated from the signal line 16, causing malfunction of the receiving IC 13. In order to suppress the generation of the electromagnetic wave, the signal line 16
An inductance element 17 is inserted in the. Signal line 1
By inserting the inductance element 17 in 6, the high frequency current flowing through the signal line 16 is limited, and electromagnetic noise is reduced.

Z = 2πfL (1) In the formula (1), Z is the impedance generated in the signal line 16,
f is the frequency of the harmonic component of the clock signal, and L is the inductance value of the inductance element 17.

According to the equation (1), the inductance element 1
As the inductance value L of 7 increases, the impedance Z increases and the high frequency component of the clock signal decreases. Further, by increasing the inductance L of the inductance element 17, when the resonance frequency of the series circuit composed of the inductance element 17 and the input capacitance 15 matches the frequency of the clock signal, the inductance element 17 and the input terminal 14 are connected to each other. The basic sine wave of the clock signal is applied to the signal line 16 between them, which is ideal in terms of electromagnetic noise reduction. However, there is a problem that the Q of the resonance vibration is too high, and the input allowable value of the input terminal 14 is frequently exceeded, as shown by a signal 72 in FIG. 2 described later.

[0009]

In order to solve the above-mentioned problems, conventionally, a resonant vibration damping resistor is inserted in series with the inductance element 17. By inserting the resonance vibration damping resistor, the amplitude of the AC (Alternating current) component of the sine wave clock signal is reduced. Further, the unnecessary radiation can be reduced by reducing the amplitude of the clock signal.

FIG. 9 shows the waveform of the signal 18 whose amplitude is reduced by the resonant vibration damping resistor. In the signal 18, the DC (Direct curre
Since the DC voltage level which is the (nt) component does not change and the amplitude is the voltage Ve, it does not fall below the threshold voltage VL at the input terminal 14 and causes the operation failure of the reception IC 13.

It is an object of the present invention to provide a clock signal waveform shaping circuit capable of reducing electromagnetic noise radiated from a signal line supplying a clock signal.

[0012]

SUMMARY OF THE INVENTION The present invention is a circuit for shaping the waveform of a clock signal derived as a pulse signal having a predetermined period, and extracting a basic sine wave component from the clock signal, Of the fundamental sine wave component extracted by the fundamental wave extracting means, the amplitude setting means for setting the amplitude of the fundamental sine wave component extracted by the fundamental wave extracting means, and the DC voltage level of the fundamental sine wave component extracted by the fundamental wave extracting means. And a DC voltage level setting means for setting the above. According to the present invention, the fundamental sine wave component is extracted from the clock signal supplied to the waveform shaping circuit by the fundamental wave extracting means. The amplitude of the basic sine wave component of the clock signal is determined by the amplitude setting means, and the DC voltage level of the basic sine wave component is
It is determined by the DC voltage level setting means. Therefore, the waveform shaping circuit can output the basic sine wave component of the clock signal, which is a pulse signal, with the amplitude and DC voltage level determined so as to correspond to the threshold value of the circuit to which the clock signal is to be supplied. it can.

Further, the fundamental wave extracting means of the present invention is characterized by including a series resonance circuit. According to the present invention, the fundamental wave extracting means of the waveform shaping circuit includes a series resonance circuit. Therefore, by defining the series resonant frequency of the series resonant circuit equal to the frequency of the clock signal,
The fundamental sine wave component of the clock signal can be extracted.

Further, the DC voltage level setting means of the present invention is characterized by including a resistance element connected in parallel to at least a part of the series resonance circuit. According to the present invention, the DC voltage level of the signal output from the waveform shaping circuit is determined by the resistance value of the resistance element. Therefore, the signal having the DC voltage level corresponding to the circuit to which the signal is supplied can be output from the waveform shaping circuit.

Further, the present invention is characterized in that the amplitude setting means includes a voltage dividing circuit including a plurality of reactance elements. According to the present invention, the amplitude of the signal output from the waveform shaping circuit is determined by dividing the amplitude of the basic sine wave by the division ratio based on the reactance value of each reactance element included in the voltage dividing circuit. Therefore, a signal having an amplitude corresponding to the circuit to which the clock signal should be input can be output from the waveform shaping circuit.

The present invention is also characterized in that a capacitance on the input side of the clock signal is included as a part of the reactance element. According to the present invention, the amplitude of the basic sine wave is divided based on the capacitance in the circuit to which the signal is supplied from the waveform shaping circuit and the division ratio of the reactance values of the other reactance elements included in the voltage dividing circuit. The amplitude of the signal output from the shaping circuit is determined. Therefore, a signal having an amplitude corresponding to the circuit to which the clock signal should be input can be output from the waveform shaping circuit.

The present invention is also characterized in that, as a part of the reactance element, a capacitive element connected in parallel to the input side of the clock signal is included. According to the present invention, the amplitude of the basic sine wave is based on the voltage division ratio of the capacitance in the circuit to which the basic sine wave is supplied from the waveform shaping circuit and the capacitive element connected in parallel to the capacitance. The amplitude of the divided signal output from the waveform shaping circuit is determined. Therefore, a signal having an amplitude corresponding to the circuit to which the clock signal should be input can be output from the waveform shaping circuit.

Further, the DC voltage level setting means of the present invention is characterized in that it includes a voltage dividing circuit composed of a plurality of resistance elements. According to the invention, the DC voltage level of the signal output from the waveform shaping circuit is determined based on the voltage division ratio according to the resistance value of each resistance element included in the voltage dividing circuit. Therefore, the signal having the DC voltage level corresponding to the circuit to which the signal is supplied can be output from the waveform shaping circuit.

The present invention is also characterized in that a resistance on the input side of the clock signal is included as a part of the resistance element. According to the invention, the signal output from the waveform shaping circuit is based on the voltage division ratio of the resistance in the circuit to which the signal from the waveform shaping circuit is supplied and the other resistance element included in the voltage dividing circuit. The DC voltage level is defined. Therefore, the signal having the DC voltage level corresponding to the circuit to which the signal is supplied can be output from the waveform shaping circuit.

Further, the present invention is characterized in that the resistance element includes a resistance element connected between an input side of a clock signal and a power supply, as a part of the resistance element. According to the invention, the DC voltage level of the signal output from the waveform shaping circuit is determined by dividing the voltage from the power supply based on the voltage division ratio of the resistance element and the other resistance element in the voltage dividing circuit. .
Therefore, the signal having the DC voltage level corresponding to the circuit to which the signal is supplied can be output from the waveform shaping circuit.

[0021]

1 is a diagram showing a waveform shaping circuit 21 according to a first embodiment of the present invention and a configuration related to the waveform shaping circuit 21. As shown in FIG. The waveform shaping circuit 21 includes an inductance element 22, a capacitance element 23, and a resistance element 24. The inductance element 22 and the capacitance element 23 are connected in series. The resistance element 24 is connected in parallel to the inductance element 22 and the capacitance element 23, which are connected in series.

The clock signal output IC 31 creates a pulsed clock signal having a predetermined frequency and outputs it to the output terminal 3
2 via the inductance element 22 of the waveform shaping circuit 21
Give to. The clock signal receiving IC 33 has an input terminal 34.
It operates on the basis of a clock signal supplied via.
The reception IC 33 has the allowable input values and the threshold voltages VL and VH set similarly to the reception IC 13 shown in the related art. The output terminal 32 and the input terminal 34 are connected by the signal line 35 via the waveform shaping circuit 21. The clock signal output from the output terminal 32 is applied to the inductance element 22 and the resistance element 24.

The resistance at the input terminal 34 is the input resistance 36.
, And the capacitance is shown as the input capacitance 37. The resistance value of the input resistor 36 is R1, and the capacitance value of the input capacitor 37 is C1.
And The resistance value R1 of the input resistor 36 and the input capacitance 37
The capacitance value C1 of is determined when the reception IC 33 is formed.
The inductance value of the inductance element 22 is L1, the capacitance value of the capacitance element 23 is C2, and the resistance value of the resistance element 24 is R2.

The inductance element 22 and the capacitance element 23
And the serial resonance frequency of the series resonance circuit formed by the input capacitor 37 is determined to be the same as the frequency of the clock signal output from the output IC 31. Output I
Assuming that the frequency of the clock signal output from C31 is f, the inductance value L1 and the capacitance value C2 are as follows: f = 1 / 2π√ [L1 × {(C1 × C2) / (C1 + C2)}] (2) Is determined to meet.

FIG. 2 shows the waveform of the signal in the waveform shaping circuit 21. The clock signal 71 shown in FIG. 2 (1) output from the output terminal 32 is a pulse signal generated in each predetermined cycle. The clock signal 71 has a high level of the voltage VCC and a low level of the voltage GND. A voltage waveform at a connection point A between the inductance element 22 and the capacitance element 23 is indicated by a broken line and is a signal 72. Signal 7
2, the voltage Va indicating the amplitude becomes larger than the voltage between the voltage GND and VCC and exceeds the input allowable value of the reception IC 33, similarly to the signal given to the reception IC 13 in the related art.

The voltage Va of the signal 72 is determined by the Q of the series resonance circuit composed of the input capacitance 37, the capacitance element 23, and the inductance element 22, and the driving ability of the output terminal 32 of the output IC 31. However, since the inductance value L1 of the inductance element 22 and the output resistance value of the output IC 31 are not generally disclosed, the voltage Va is experimentally measured, and the capacitance value is measured based on the voltage level of the measured voltage Va. Calculate the ratio of C1 and C2.

A signal 73 indicated by a broken line in FIG. 2B is a signal given to the input terminal 34. In the signal 73, the voltage Vb indicating the amplitude is smaller than the voltage between the voltages GND and VCC, the voltage of one peak is equal to or higher than the threshold voltage VH, and the voltage of the other peak is equal to or lower than the threshold voltage VL. .

The voltage Vb is obtained by the following equation (3).

Vb = Va × C2 / (C1 + C2) (3) If the DC voltage level of the signal 72 at the output terminal 32 is Vc, the DC voltage level Vd of the signal 73 given to the input terminal 34 is the resistance element. Resistance value R2 of 24,
By the predetermined resistance value R1 of the input resistor 36,
It is calculated by the following equation (4).

Vd = Vc × R1 / (R1 + R2) (4) DC voltage level V of the signal 72 applied to the input terminal 34
d is, for example, an intermediate voltage between two threshold voltages VL and VH, one peak voltage of the signal 73 is equal to or higher than the threshold voltage VH, and the other peak voltage is the threshold voltage VH.
It is set to be L or less.

As described above, according to the present embodiment, the pulse waveform clock signal output from the output IC 31 is
The harmonic shaping component 21 and the input capacitance 36 and the input capacitance 37 of the input terminal 34 limit the harmonic components to shape the waveform into a sine wave, so that electromagnetic noise radiated from the signal line 35 can be reduced. . Further, in the waveform shaping circuit 21, since the amplitude of the sine wave and the DC voltage level are controlled by the capacitive element 23 and the resistive element 24, the amplitude is set to the minimum value within the range where the input allowable condition of the receiving IC 33 is satisfied. Therefore, the electromagnetic noise radiated from the signal line 35 can be reduced. The amplitude of the sine wave output from the waveform shaping circuit 21 is at least the threshold voltages VL and V so that it corresponds to the threshold voltage of the reception IC 33.
Since the width is set to be larger than the width of H, the receiving IC 33 can be operated without causing a malfunction.

FIG. 3 is a diagram showing a waveform shaping circuit 41 according to the second embodiment of the present invention and a configuration related to the waveform shaping circuit 41. In FIG. 3, the same components as those shown in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. The waveform shaping circuit 41 includes an inductance element 22,
The capacitive element 23, the resistive element 24, and the resistive element 42 are included. One end of the resistance element 42 is connected to the capacitance element 23.
Is connected to the signal line 35 between the input terminal 34 and the input terminal 34, and the other end is grounded. The characteristic of the waveform shaping circuit 41 is that a resistance element 42 is provided in addition to the configuration of the waveform shaping circuit 21.

When the receiving IC 33 is composed of, for example, a CMOS (complementary metal oxide semiconductor), the resistance value R1 of the input resistor 36 becomes substantially infinite. Since the resistance value R1 is substantially infinite, the DC voltage level of the sine wave supplied to the reception IC 33 cannot be determined. In the present embodiment, by providing the resistance element 42,
The resistance elements 24 and 42 define the sine wave DC voltage level. Assuming that the resistance value of the resistance element 42 is R3, the resistance values R2 and R3 are determined so as to satisfy Vd = Vc × RA / (RA + R2) (5). In formula (5), RA =
(R1 × R3) / (R1 + R3). The DC voltage level Vd and the frequency f of the clock signal are the same as those of the waveform shaping circuit 21.

As described above, according to the present embodiment, even if the receiving IC 33 is composed of CMOS and the resistance value R1 of the input resistor 36 is substantially infinite, the resistance element 24,
By setting the resistance values R2 and R3 of 42, respectively, the DC voltage level of the clock signal that has become a sine wave is controlled to set the amplitude of the sine wave to the minimum value within the range where the input acceptance condition of the reception IC 33 is satisfied. Can, signal line 3
It is possible to reduce the electromagnetic noise radiated from No. 5.

The inductance element 22 is constructed by, for example, penetrating a bead core with a conductive wire, but the inductance value generally realized by the bead core is not necessarily sufficiently large, and the inductance value L1 and the capacitance value C are not necessarily large.
1 and C2. It is not possible to exactly match the resonant frequency to the frequency of the clock signal.

FIG. 4 is a diagram showing a waveform shaping circuit 46 according to the third embodiment of the present invention and a configuration related to the waveform shaping circuit 46. 4, the same components as those shown in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. The waveform shaping circuit 46 includes the inductance element 22,
The capacitance element 23, the resistance element 24, and the capacitance element 47 are included. One end of the capacitive element 47 is connected to the capacitive element 23.
Is connected to the signal line 35 between the input terminal 34 and the input terminal 34, and the other end is grounded. In the waveform shaping circuit 46, the resonance frequency is matched with the frequency of the clock signal by the capacitance value C3 of the capacitance element 47.

In the waveform shaping circuit 46, capacitance values C2 and C
3 and the inductance value L1 satisfy f = 1 / 2π√ [L1 × {(C1 + C3) × C2} / {(C1 + C3) + C2}] (6) Vb = Va × C2 / (C1 + C2 + C3) (7) Is determined. Also, the DC voltage level Vd
Is the same as that of the waveform shaping circuit 21, and the resistance value R2 of the resistance element 24 is determined based on the equation (4).

Since the waveform shaping circuit 46 of this embodiment is provided with the capacitance element 47, the resonance frequency can be accurately matched with the frequency of the clock signal by adjusting the capacitance value C3 of the capacitance element 47. it can.

As described above, according to the present embodiment, the pulse waveform clock signal output from the output IC 31 is
The waveform shaping circuit 46, the input resistor 36 and the input capacitor 37 of the input terminal 34, and the capacitive element 47 limit the harmonic components and shape the signal into a sine wave, thereby reducing electromagnetic noise radiated from the signal line 35. Can be made.

In the present embodiment, the waveform shaping circuit 2
Although the capacitor element 47 is provided in the first embodiment, it may be provided in the waveform shaping circuit 41.

By providing the waveform shaping circuit 41 with the capacitive element 47, the resonance frequency in the series resonance circuit can be accurately matched with the frequency of the clock signal even if the reception IC 33 is a circuit composed of CMOS. it can.

In the waveform shaping circuits 21, 41 and 46, the DC voltage level of the clock signal when converted into a sine wave is
The voltage at the output terminal 32 and the resistance value R2 of the resistance element 24
Therefore, the DC voltage level Vd at the input terminal 34 cannot be set higher than the DC voltage level Vc at the output terminal 32.

FIG. 5 is a diagram showing a waveform shaping circuit 51 according to a fourth embodiment of the present invention and a configuration related to the waveform shaping circuit 51. 5, the same components as those shown in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. The waveform shaping circuit 51 includes an inductance element 22,
The capacitance element 23 and the resistance element 52 are included.
The inductance element 22 and the capacitance element 23 are connected in series, and a pulsed clock signal from the output IC 31 is applied to the inductance element 22.

The resistance element 52 is supplied with the power supply voltage VCC at one end and connected to the signal line 35 between the capacitance element 23 and the input terminal 34 at the other end. The DC voltage level of the sine wave signal is determined between the voltage VCC and the ground voltage GND by the division ratio based on the resistance value of the resistance element 52 and the input resistance 36.

The capacitance value C2 and the inductance value L1 are obtained based on the frequency f of the clock signal output from the output IC 31, and the amplitude is calculated using the equation (3) based on the capacitance values C1 and C2 and the amplitude voltage Va. The voltage Vb is calculated.

When the resistance value of the resistance element 52 is R4, the resistance value R4 is determined based on the DC voltage level Vd as follows: Vd = VCC × R1 / (R1 + R4) (8)

As described above, according to the present embodiment, the pulse waveform clock signal output from the output IC 31 is
By the waveform shaping circuit 51 and the input resistance 36 and the input capacitance 37 of the input terminal 34, the harmonic component is limited and shaped into a sine wave, so that the electromagnetic noise radiated from the signal line 35 can be reduced. Moreover, regardless of the DC voltage level Vc at the output terminal 32, the DC voltage level of the sine wave can be determined by the resistance value R4 of the resistance element 52 to which the power supply voltage VCC is applied at one end, and the amplitude I
It can be set to the minimum value within the range where the input acceptance condition of C33 is satisfied, and electromagnetic noise radiated from the signal line 35 can be reduced.

FIG. 6 is a diagram showing a waveform shaping circuit 56 according to the fifth embodiment of the present invention and a configuration related to the waveform shaping circuit 56. 6, the same components as those shown in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. The waveform shaping circuit 56 includes the inductance element 22,
The capacitance element 23 and the resistance elements 52 and 57 are included. One end of the resistance element 57 is connected to the signal line 35 between the capacitance element 23 and the input terminal 34, and the other end is grounded.

When the receiving IC 33 is composed of, for example, a CMOS, the resistance value R1 of the input resistor 36 becomes substantially infinite, so that the sine wave DC voltage level cannot be determined. In the present embodiment, resistance element 57 is provided and resistance elements 52 and 57 determine the DC voltage level of the sine wave with reference to power supply voltage VCC.

Based on the frequency f of the clock signal output from the output IC 31, the capacitance value C2 and the inductance value L1 are obtained by using the equation (2), and the equation ((2) is used based on the capacitance values C1 and C2 and the amplitude voltage Va. Amplitude voltage V using 3)
Find b.

Assuming that the resistance value of the resistance element 57 is R5, the resistance value R5 is determined based on the DC voltage level Vd as follows: Vd = VCC × RB / (RB + R4) (9) In the formula (9), RB = (R1 × R5) /
(R1 + R5).

Resistance values R4 and R5 of the resistance elements 52 and 57
By defining the above, even if the reception IC 33 is formed of CMOS and the resistance value R1 of the input resistor 36 is substantially infinite, the DC voltage level of the clock signal is set to a desired voltage level between the power supply voltage VCC and the ground voltage GND. Can be specified.

The resistance values R4 of the resistance elements 52 and 57 are
Unless R5 is set to a sufficiently large value, the Q of the series resonant circuit
Will decrease and the value of the amplitude voltage Vb will change.

As described above, according to the present embodiment, even if the reception IC 33 is formed of CMOS and the resistance value of the input resistance is substantially infinite, the resistance values R4 of the resistance elements 52 and 57 are R4. , R5, the DC voltage level of the sine wave clock signal can be set to a predetermined voltage value, and the amplitude can be set to the minimum value within the range where the input allowable condition of the receiving IC 33 is satisfied. The electromagnetic noise radiated from the signal line 35 can be reduced.

The inductance element 22 is constructed by, for example, penetrating a lead wire into a bead core. However, in general, the inductance value realized by the bead core is not necessarily sufficiently large, and the inductance value L1 and the capacitance value C are not necessarily large.
1 and C2. It is not possible to exactly match the resonant frequency to the frequency of the clock signal.

FIG. 7 is a diagram showing a waveform shaping circuit 61 according to the sixth embodiment of the present invention and a configuration related to the waveform shaping circuit 61. 7, the same components as those shown in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted. The waveform shaping circuit 61 includes an inductance element 22,
The capacitive element 23, the resistive element 52, and the capacitive element 62 are included. One end of the capacitive element 62 is connected to the capacitive element 23.
Is connected to the signal line 34 between the input terminal 34 and the input terminal 34, and the other end is grounded.

In the waveform shaping circuit 61, the resonance frequency is matched with the frequency of the clock signal by determining the capacitance value C5 of the capacitance element 62.

When the capacitance value of the capacitive element 62 is C5, the capacitance values C2 and C5 and the inductance value L1 are as follows: f = 1 / 2π√ [L1 × {(C1 + C5) × C2} / {(C1 + C5) + C2}] (10) Vb = Va × C2 / (C1 + C2 + C5) (11) Also, the DC voltage level Vd
Is the same as the waveform shaping circuit 51, and the resistance value R4 of the resistance element 52 is determined based on the equation (8).

As described above, according to the present embodiment, in the waveform shaping circuit 61, since the capacitive element 62 is provided, the inductance element 22 having the desired inductance value L1 cannot be used. However, by setting the capacitance value C5 of the capacitive element 62 to a predetermined value, the inductance element 22 and the capacitive element 23,
The resonance frequency of the series resonance circuit constituted by 62 and the input capacitor 37 can be accurately matched with the frequency of the clock signal, and the harmonic components are limited and transformed into a sine wave, so that the radiation from the signal line 35 is radiated. The electromagnetic noise generated can be reduced.

In the present embodiment, the waveform shaping circuit 5
Although the capacitive element 62 is provided in the first example, the capacitive element 62 may be provided in the waveform shaping circuit 56.

By providing the capacitive element 62 in the waveform shaping circuit 56, it is possible to accurately match the resonance frequency in the series resonance circuit with the frequency of the clock signal even if the receiving IC 33 is a circuit composed of CMOS. it can.

[0062]

As described above, according to the present invention, the waveform shaping circuit converts the clock signal, which is a pulse signal, into the sine wave by the fundamental wave extracting means, and the desired amplitude and DC voltage level of the sine wave. Since the value is set and output, a sine wave corresponding to the circuit to which the clock signal is to be supplied can be supplied, and electromagnetic noise radiated from the signal line for supplying the clock signal to the circuit to which the clock signal is to be supplied. Can be reduced.

Further, according to the present invention, since the basic sine wave component of the clock signal is extracted by the series resonance circuit in the fundamental wave extraction means, the clock signal of the clock signal can be formed by a simple structure in which the capacitance element and the inductance element are connected in series. The fundamental sine wave component can be extracted.

Further, according to the present invention, since the DC voltage level setting means includes the resistance element connected in parallel to at least a part of the series resonance circuit, the resistance value of the resistance element causes a sine wave. The DC voltage level of the clock signal can be set to a voltage level lower than the DC voltage level in the series resonance circuit to supply a sine wave corresponding to the circuit to which the clock signal is to be applied, and the circuit to which the clock signal is to be applied. It is possible to reduce electromagnetic noise radiated from the signal line for supplying the clock signal to the.

Furthermore, according to the present invention, since the amplitude of the basic sine wave output from the waveform shaping circuit is determined by the division ratio of the reactance values of the reactance elements included in the voltage dividing circuit, it becomes a sine wave. The peak of the clock signal can be made small enough to exceed the threshold voltage of the circuit to which the clock signal is applied, and electromagnetic noise radiated from the signal line for supplying the clock signal can be reduced. Further, since the amplitude of the sine wave clock signal is divided and reduced, it is possible to operate the circuit to which the clock signal should be applied so as not to cause a malfunction.

Further, according to the present invention, since the voltage dividing circuit of the amplitude setting means includes the capacitance on the input side of the clock signal corresponding to the reactance element, in the circuit to which the sine wave is supplied from the waveform shaping circuit. The amplitude of the sinusoidal clock signal is determined based on the voltage division ratio of the capacitance and other reactance elements included in the voltage divider circuit, and the peak of the signal is the threshold of the circuit to which the clock signal should be applied. It can be reduced to the extent that it exceeds the value voltage,
The electromagnetic noise radiated from the signal line for supplying the clock signal can be reduced. Further, since the amplitude of the sine wave clock signal is divided and reduced, it is possible to operate the circuit to which the clock signal should be applied so as not to cause a malfunction.

Further, according to the present invention, since the capacitive element which is the reactance element is connected in parallel to the capacitance on the input side of the clock signal in the voltage dividing circuit of the amplitude setting means, the sine wave is separated from the waveform shaping circuit. The amplitude of the sinusoidal clock signal is determined based on the voltage division ratio of the capacitance in the circuit to which the wave is supplied and the capacitive element connected in parallel to the capacitance, and the peak of the signal is clocked. It is possible to reduce the voltage so that it exceeds the threshold voltage of the circuit to which the signal is applied, and it is possible to reduce the electromagnetic noise radiated from the signal line for supplying the clock signal. Further, since the amplitude of the sine wave clock signal is divided and reduced, it is possible to operate the circuit to which the clock signal should be applied so as not to cause a malfunction.

Further, according to the present invention, since the DC voltage level setting means includes the voltage dividing circuit by the plurality of resistance elements, the DC voltage level of the clock signal which is a sine wave output from the waveform shaping circuit. Is determined based on the voltage division ratio by the resistance value of each resistance element included in the voltage divider circuit, controls the DC voltage level of the sine wave, and determines the peak of the sine wave of the circuit to which the clock signal is given. It can be set to exceed the threshold voltage. Since the DC voltage level can be set to a predetermined value, the amplitude of the sine wave clock signal can be set small, and electromagnetic noise radiated from the signal line for supplying the clock signal can be reduced. it can.

Further, according to the present invention, since the voltage dividing circuit of the DC voltage level setting means includes the resistance on the input side of the clock signal corresponding to the resistance element, the basic sine wave is supplied from the waveform shaping circuit. The DC voltage level of the sine wave is determined based on the voltage division ratio between the resistance in the circuit and the other resistance elements included in the voltage divider circuit, and the peak of the sine wave should be applied to the clock signal of the circuit. It can be set to exceed the threshold voltage. Since the DC voltage level can be set to a predetermined value, the amplitude of the sine wave clock signal can be set small, and electromagnetic noise radiated from the signal line for supplying the clock signal can be reduced. it can.

Further, according to the present invention, since the voltage dividing circuit of the DC voltage level setting means includes the resistance element connected between the input side of the clock signal and the power supply, the voltage is output from the waveform shaping circuit. The DC voltage level of the sine wave is determined based on the division ratio of the voltage from the power source due to the resistance element and other resistance elements in the voltage dividing circuit, and the DC voltage level of the signal is controlled to determine the peak of the sine wave. The clock signal can be defined to exceed the threshold voltage of the circuit to be provided. Since the DC voltage level can be set to a predetermined value, the amplitude of the sine wave clock signal can be set small, and electromagnetic noise radiated from the signal line for supplying the clock signal can be reduced. it can.

[Brief description of drawings]

FIG. 1 is a diagram showing a waveform shaping circuit 21 according to a first embodiment of the present invention and a configuration related to the waveform shaping circuit 21.

FIG. 2 is a diagram showing a waveform of a signal in a waveform shaping circuit 21.

FIG. 3 is a diagram showing a waveform shaping circuit 41 according to a second embodiment of the present invention and a configuration related to the waveform shaping circuit 41.

FIG. 4 is a diagram showing a waveform shaping circuit 46 according to a third embodiment of the present invention and a configuration related to the waveform shaping circuit 46.

FIG. 5 is a diagram showing a waveform shaping circuit 51 according to a fourth embodiment of the present invention and a configuration related to the waveform shaping circuit 51.

FIG. 6 is a diagram showing a waveform shaping circuit 56 according to a fifth embodiment of the present invention and a configuration related to the waveform shaping circuit 56.

FIG. 7 is a diagram showing a waveform shaping circuit 61 according to a sixth embodiment of the present invention and a configuration related to the waveform shaping circuit 61.

FIG. 8 is a diagram for explaining a configuration for electromagnetic noise reduction that is generally performed conventionally.

FIG. 9 is a waveform diagram of the signal 18 whose amplitude is reduced by the resonance vibration damping resistance.

[Explanation of symbols]

 21, 41, 46, 51, 56, 61 Wave shaping circuit 22 Inductance element 23 Capacitance element 24 Resistance element 31 Clock signal output IC 32 Output terminal 33 Clock signal reception IC 34 Input terminal 35 Signal line 36 Input resistance 37 Input capacitance

Claims (9)

[Claims] 1. A circuit for shaping a waveform of a clock signal derived as a pulse signal having a predetermined cycle, wherein a fundamental sine wave component is extracted from the clock signal to suppress other frequency components. Extraction means, amplitude setting means for setting the amplitude of the fundamental sine wave component extracted by the fundamental wave extraction means, and DC voltage level setting means for setting the DC voltage level of the fundamental sine wave component extracted by the fundamental wave extraction means A waveform shaping circuit for a clock signal, including: 2. The waveform shaping circuit for a clock signal according to claim 1, wherein the fundamental wave extracting means includes a series resonance circuit. 3. The waveform shaping circuit for a clock signal according to claim 1, wherein the DC voltage level setting means includes a resistance element connected in parallel to at least a part of the series resonance circuit. 4. The amplitude setting means includes a voltage dividing circuit including a plurality of reactance elements.
5. A clock signal waveform shaping circuit according to any one of 3 to 3. 5. The clock signal waveform shaping circuit according to claim 4, wherein a capacitance on the input side of the clock signal is included as a part of the reactance element. 6. The clock signal waveform shaping circuit according to claim 4, wherein a capacitive element connected in parallel to the input side of the clock signal is included as a part of the reactance element. 7. The waveform shaping circuit according to claim 1, wherein the DC voltage level setting means includes a voltage dividing circuit including a plurality of resistance elements. 8. The clock signal waveform shaping circuit according to claim 7, wherein a resistance on the input side of the clock signal is included as a part of the resistance element. 9. The clock signal waveform shaping circuit according to claim 7, wherein a resistor element connected between the input side of the clock signal and the power supply is included as a part of the resistor element.